Chip layout structure of power MOS (Metal Oxide Semiconductor) tube

Abstract

The utility model discloses a chip layout structure of a power MOS (Metal Oxide Semiconductor) tube, which comprises at least two groups of low-voltage power tube arrays, and each group of low-voltage power tube array comprises a plurality of rows of low-voltage power tubes arranged along a first direction; and a plurality of rows of first substrate selection tubes and second substrate selection tubes. Wherein at least one row of first substrate selection tubes and second substrate selection tubes are arranged among multiple rows of low-voltage power tubes of each group of low-voltage power tube arrays, so that the substrate parameter uniformity of the low-voltage power tubes can be improved, the risk that a chip is broken down due to the influence of a surge signal is reduced, and meanwhile, the chip area is saved to the maximum extent.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, in particular to a chip layout structure of a power MOS tube. Background Art

[0002] To ensure sufficient current flowing through power tubes to achieve their desired operation, existing technologies typically employ multiple MOS tube structures connected in parallel. This structured chip is generally referred to as a power MOS tube chip. To safeguard the safety of the power tubes within the chip, ensuring that they maintain normal operation and avoid avalanche issues when a reverse voltage appears at their source and drain terminals, and to ensure they can shut down under both forward and reverse voltages, a substrate selection module is added between the source and drain terminals of the power tubes. For example, in the case of NMOS power tubes, the substrate selection module includes two NMOS tubes, each smaller than the MOS tubes within the power tube. These NMOS tubes can be connected between the source and back gate, and between the drain and back gate, respectively, of the power tubes to control the back gate voltage based on the source and drain voltages of the power tubes.

[0003] Figure 1 The schematic diagram of the positions of substrate selection tubes and power tubes according to the prior art is shown. Figure 1 In the prior art, a substrate selector tube (SST) is typically placed on one side of a power tube as part of a substrate selector module. The SST's source and substrate potential are connected to the power tube's substrate via metal wires. This results in varying distances between the multiple MOS transistors that make up the power tube and the SST, and consequently, varying metal wire lengths. Longer wire lengths increase wire resistance, leading to varying voltage and current values ​​across the substrates of the various MOS transistors that comprise the power tube. This nonuniformity in substrate parameters impacts the performance and effectiveness of the power tube.

[0004] Therefore, a new chip layout structure of a power MOS tube needs to be proposed to solve the above problems. Utility Model Content

[0005] In view of the above problems, the purpose of the present invention is to provide a chip layout structure for a power MOS tube, so as to improve the uniformity of the substrate parameters of the low-voltage power tube, reduce the risk of the chip being broken down by the surge signal, and save the chip area to the maximum extent.

[0006] According to one aspect of the present invention, a chip layout structure of a power MOS tube is provided, comprising at least two groups of low-voltage power tube arrays, each group of low-voltage power tube arrays comprising multiple rows of low-voltage power tubes arranged along a first direction; and multiple rows of first substrate selection tubes and second substrate selection tubes; wherein at least one row of first substrate selection tubes and second substrate selection tubes is arranged between the multiple rows of low-voltage power tubes in each group of low-voltage power tube arrays.

[0007] Optionally, the chip layout structure further includes a plurality of third substrate selection tubes and a fourth substrate selection tube, and the plurality of third substrate selection tubes and the fourth substrate selection tubes are alternately arranged in sequence with the low-voltage power tube, the first substrate selection tube or the second substrate selection tube in the second direction, and the third substrate selection tubes and the fourth substrate selection tubes are alternately arranged in sequence with intervals between them, wherein the second direction is perpendicular to the first direction.

[0008] Optionally, the third substrate selection tube and the fourth substrate selection tube are continuous in the first direction.

[0009] Optionally, each group of low-voltage power tube arrays includes multiple rows of low-voltage power tubes in an even number, and the at least one row of first substrate selection tubes and the at least one row of second substrate selection tubes are arranged in the middle position of the multiple rows of low-voltage power tubes in each group of low-voltage power tube arrays.

[0010] Optionally, each low-voltage power tube has the same size as each first substrate selection tube and each second substrate selection tube, and are all MOS tubes of the first size; each third substrate selection tube has the same size as each fourth substrate selection tube, and are all MOS tubes of the second size, and the second size is different from the first size.

[0011] Optionally, the second size is smaller than the first size.

[0012] Optionally, each low-voltage power tube and each substrate selection tube are spaced apart from other MOS tubes via a substrate region of the MOS tube, and at least one layer of first metal wire is connected in parallel to the substrate region.

[0013] Optionally, each low-voltage power tube and each substrate selection tube includes an even number of polysilicon strips, and doped active regions are provided on both sides of each polysilicon strip. At least one layer of second metal wire is connected in parallel to the doped active region, and the doped active region includes a first doped active region and a second doped active region that are alternately arranged. The number of polysilicon strips in each substrate selection tube is equal to the number of polysilicon strips in each low-voltage power tube.

[0014] Optionally, the first doped active area of ​​the low-voltage power tube is connected to the first potential through at least one layer of second metal wire and contact hole, the second doped active area is connected to the second potential through at least one layer of second metal wire and contact hole, and an even number of polysilicon strips are connected to the external circuit through at least one layer of third metal wire and contact hole.

[0015] Optionally, the first doped active region of each first substrate selection tube and the third substrate selection tube is connected to its substrate through at least one layer of second metal wire, the second doped active region is connected to the first potential through at least one layer of second metal wire and contact hole, an even number of polysilicon strips are interconnected through at least one layer of third metal wire and contact hole and connected to the second potential through at least one layer of third metal wire and contact hole, and the substrate is connected to the substrate of the low-voltage power tube through at least one layer of first metal wire; the first doped active region of each second substrate selection tube and the fourth substrate selection tube is connected to its substrate through at least one layer of second metal wire, the second doped active region is connected to the second potential through at least one layer of second metal wire and contact hole, an even number of polysilicon strips are interconnected through at least one layer of third metal wire and contact hole and connected to the first potential through at least one layer of third metal wire and contact hole, and the substrate is connected to the substrate of the low-voltage power tube through at least one layer of first metal wire.

[0016] The chip layout structure of a power MOS tube provided by the present invention includes at least two groups of low-voltage power tube arrays, each group of low-voltage power tube arrays including multiple rows of low-voltage power tubes arranged along a first direction; and multiple rows of first substrate selection tubes and second substrate selection tubes. Among them, at least one row of first substrate selection tubes and second substrate selection tubes is arranged between the multiple rows of low-voltage power tubes in each group of low-voltage power tube arrays, thereby improving the uniformity of the low-voltage power tube substrate parameters, reducing the risk of chip breakdown due to surge signals, and maximally saving chip area.

[0017] In a preferred embodiment, the chip layout structure of the power MOS tube also includes multiple third substrate selection tubes and fourth substrate selection tubes. The multiple third substrate selection tubes and fourth substrate selection tubes are alternately arranged in the second direction with the low-voltage power tube, the first substrate selection tube or the second substrate selection tube, and the intervals between the third substrate selection tubes and the fourth substrate selection tubes are alternately arranged in sequence, thereby further improving the uniformity of the low-voltage power tube substrate parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram showing the positions of substrate selection tubes and power tubes according to the prior art is shown;

[0020] Figure 2 A schematic diagram showing the circuit connection relationship of a chip layout structure of a power MOS tube;

[0021] Figure 3 A schematic structural diagram of a chip layout structure of a power MOS tube according to a first embodiment of the present utility model is shown;

[0022] Figure 4 A schematic structural diagram of a chip layout structure of a power MOS tube according to a second embodiment of the present invention is shown.

[0023] Figure 5 A two-dimensional schematic diagram of a low-voltage power tube according to an embodiment of the present utility model is shown;

[0024] Figure 6 A two-dimensional schematic diagram of a substrate selection tube according to an embodiment of the present utility model is shown;

[0025] Figure 7 A two-dimensional schematic diagram of the connection between the substrate selection tube and the low-voltage power tube according to the first embodiment of the utility model is shown. DETAILED DESCRIPTION

[0026] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements or modules are represented by identical or similar reference numerals. For clarity, the various parts in the accompanying drawings are not drawn to scale.

[0027] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0028] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will appreciate that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality.

[0029] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0030] Figure 2 A schematic diagram showing the circuit connection relationship of a chip layout structure of a power MOS tube is shown.

[0031] To ensure safe operation of power transistors, existing technologies incorporate a substrate selection module. This module controls the substrate or backgate voltage of the power transistor to always select the lower potential between points A and B, ensuring normal operation regardless of the voltages at points A and B.

[0032] Specifically, the substrate selection module is connected to the first substrate selection tube and the second substrate selection tube in parallel between the first doped active area and the back gate of the power tube and between the second doped active area and the back gate, respectively. The first substrate selection tube and the second substrate selection tube both adopt MOS tube structure.

[0033] The source and back gate of the first substrate selection transistor are connected to the substrate, or back gate, of the power transistor. The drain of the first substrate selection transistor is connected to point A, and the gate is connected to point B. The source and back gate of the second substrate selection transistor are respectively connected to the substrate of the power transistor. The drain of the second substrate selection transistor is connected to point B, and the gate is connected to point A. The first doped active region and the second doped active region of the power transistor are connected to points A and B, respectively. That is, due to the symmetrical structure of the power transistor design, it has two doped active regions. The first doped active region, hereinafter referred to as the first doped active region, is connected to point A and is connected to the drain of the first substrate selection transistor and the gate of the second substrate selection transistor, respectively. The second doped active region, hereinafter referred to as the second doped active region, is connected to point B and is connected to the drain of the second substrate selection transistor and the gate of the first substrate selection transistor, respectively. When the potential at point A is greater than the potential at point B, due to the action of the substrate voltage, the first doped active region automatically forms the drain of the power tube, and the second doped active region automatically forms the source of the power tube. When the potential at point B is greater than the potential at point A, the working state of the power tube is reversed, and the first doped active region becomes the source of the power tube, and the second doped active region becomes the drain of the power tube.

[0034] If adopted Figure 1 The chip layout structure shown will result in a large line resistance at both ends of the substrate selection tube. When a large instantaneous surge signal appears at potential A or B, part of the coupling current will flow from the substrate (bulk) of the power tube through the substrate selection tube, generating a voltage drop on the substrate selection tube, making the voltage difference between the substrate and source of the power tube larger. The power tube may generate a parasitic NPN tube to break down the power tube.

[0035] Figure 3 The figure shows a schematic structural diagram of the chip layout structure of the power MOS tube according to the first embodiment of the present utility model.

[0036] The chip layout structure of a power MOS transistor of the present invention includes at least two groups of low-voltage power transistor arrays and multiple rows of first and second substrate selection transistors. Each group of low-voltage power transistor arrays includes multiple rows of low-voltage power transistors arranged along a first direction. At least one row of first and second substrate selection transistors is disposed between the multiple rows of low-voltage power transistors in each group of low-voltage power transistor arrays, thereby ensuring that the distance between each low-voltage power transistor in each row and the substrate selection transistor is equal. In other words, the metal wire lengths between each low-voltage power transistor in each row and the substrate selection transistor are equal, and the metal wire resistances are consistent, thereby achieving a more uniform substrate potential within each row of low-voltage power transistors. When a large instantaneous surge signal occurs at potential A or B, the voltage difference between the substrate and source of the power transistor can be reduced, thereby reducing the risk of power transistor breakdown.

[0037] Optionally, the number of substrate selection tubes in each row of substrate selection tubes is equal to the number of low-voltage power tubes in each row of low-voltage power tubes. The low-voltage power tubes are connected in parallel via multiple layers of metal wires; the first substrate selection tubes are connected in parallel via multiple layers of metal wires; and the second substrate selection tubes are connected in parallel via multiple layers of metal wires. As permitted by chip area and process technology, the metal wires used to connect the low-voltage power tubes in parallel, the first substrate selection tubes in parallel, and the second substrate selection tubes in parallel should have as many layers and widths as possible to minimize the line resistance of the metal wires.

[0038] Optionally, each group of low-voltage power tube arrays includes multiple rows of low-voltage power tubes that are continuous and even in number, and at least one row of first substrate selection tubes and second substrate selection tubes is arranged in the middle position of the multiple rows of low-voltage power tubes in each group of low-voltage power tube arrays. Preferably, a row of first substrate selection tubes and a row of second substrate selection tubes are arranged in the middle position of the multiple rows of low-voltage power tubes in each group of low-voltage power tube arrays. Preferably, the number of rows of low-voltage power tubes in each group is the same. Taking the example of 12 rows of low-voltage power tubes and a total of 3 groups of low-voltage power tube arrays, the first four rows of low-voltage power tubes form a group of low-voltage power tube arrays, the middle four rows of low-voltage power tubes form a group of low-voltage power tube arrays, and the last four rows of low-voltage power tubes form a group of low-voltage power tube arrays.

[0039] Optionally, each first substrate selection tube, each second substrate selection tube, and each low-voltage power tube have the same size, and are all MOS tubes of the first size. Compared to the prior art, which uses a MOS tube structure smaller than the low-voltage power tube as the substrate selection tube, the present application designs the substrate selection tube to have the same size as the low-voltage power tube, which can reduce the impedance of the substrate selection tube itself and improve the performance of the power tube.

[0040] Optionally, each low-voltage power transistor, each first substrate selection transistor, and each second substrate selection transistor are isolated from other MOS transistors by the substrate region of the MOS transistor. This isolation distance can be set based on comprehensive considerations and design requirements, such as chip area, MOS transistor size, and metal line width. When the chip area allows, this distance is as wide as possible.

[0041] The number of rows of low voltage power tubes can be flexibly set according to circuit parameters and chip size, usually set to 6-12 rows. Figure 3In the embodiment, there are eight rows of low-voltage power tubes. The eight rows of low-voltage power tubes are divided into two low-voltage power tube arrays along the dotted line in the figure. Each low-voltage power tube array includes four rows of low-voltage power tubes. In the middle of each low-voltage power tube array, i.e., between the second and third rows of low-voltage power tubes, a row of first substrate selection tubes and a row of second substrate selection tubes are sequentially arranged. This approach ensures that the distances between each row of low-voltage power tubes and the first and second substrate selection tubes are exactly the same, making the substrate potential of each row of low-voltage power tubes more uniform. Furthermore, the distances between low-voltage power tubes in different rows and the first and second substrate selection tubes do not differ significantly, making the substrate potentials of low-voltage power tubes in different rows relatively uniform. This reduces chip line resistance while sacrificing a smaller chip area, thereby reducing the risk of power tube breakdown.

[0042] Figure 3 The border of the solid line portion is the isolation area between each low-voltage power tube and the substrate selection tube, namely the substrate. At least one layer of metal wire is connected in parallel on the substrate. If conditions permit, as many layers of metal wires as possible can be connected in parallel, and the width of the metal wires can be as wide as possible to reduce the line resistance of the metal wires.

[0043] If the substrate selection tube mentioned in the first embodiment of the present invention is not marked as the first substrate selection tube or the second substrate selection tube, it means that it includes the first substrate selection tube and the second substrate selection tube.

[0044] Figure 4 A schematic structural diagram of a chip layout structure of a power MOS tube according to a second embodiment of the present invention is shown.

[0045] The second embodiment of the present invention is an improvement on the first embodiment. Based on the first embodiment, it further includes a plurality of third and fourth substrate selection tubes. These tubes are arranged alternately with the low-voltage power tubes, the first and second substrate selection tubes in the second direction, with the third and fourth substrate selection tubes spaced apart and arranged alternately. Furthermore, the third and fourth substrate selection tubes extend in the first direction.

[0046] The first direction is perpendicular to the second direction. When the first direction is horizontal, the second direction is vertical. When the first direction is vertical, the second direction is horizontal. The embodiment of the present invention is described by taking the first direction as horizontal and the second direction as vertical as an example.

[0047] While adding a third substrate selection transistor and a fourth substrate selection transistor to the power MOS transistor chip layout can make the substrate parameters of each low-voltage power transistor more uniform, it also increases the chip area. Therefore, in practical applications, the first embodiment or the second embodiment can be selected for the power MOS transistor chip layout based on the chip area.

[0048] Optionally, the third substrate selection tube and the fourth substrate selection tube have the same size, and are both MOS tubes of a second size, where the second size is different from the first size.

[0049] Optionally, the second size is smaller than the first size.

[0050] exist Figure 4 In the embodiment, there are eight rows of low-voltage power tubes, two rows of first substrate selection tubes, and two rows of second substrate selection tubes. The number of columns of low-voltage power tubes, first substrate selection tubes, and second substrate selection tubes is six, the number of columns of third substrate selection tubes is three, and the number of columns of fourth substrate selection tubes is four. Then, the first, second, fifth, sixth, seventh, eighth, eleventh, and twelfth rows of the chip are low-voltage power tubes, the third and ninth rows are first substrate selection tubes, and the fourth and tenth rows are second substrate selection tubes; the first, fifth, ninth, and thirteenth rows of the chip are fourth substrate selection tubes, and the third, seventh, and eleventh rows are third substrate selection tubes. Of course, the third and ninth rows of the chip can also be designed as second substrate selection tubes, the fourth and tenth rows as first substrate selection tubes, the first, fifth, ninth, and thirteenth rows of the chip as third substrate selection tubes, and the third, seventh, and eleventh rows as fourth substrate selection tubes. This is not a specific limitation in this application.

[0051] Optionally, each third substrate selection tube and each fourth substrate selection tube are isolated from other MOS tubes through the substrate region of the MOS tube.

[0052] Optionally, the connection method between the third substrate selection tube and the low-voltage power tube is the same as that between the first substrate selection tube, and the connection method between the fourth substrate selection tube and the low-voltage power tube is the same as that between the second substrate selection tube.

[0053] Figure 5 The figure shows a schematic structural diagram of a low-voltage power tube according to an embodiment of the present utility model.

[0054] See also Figure 5The bulk (substrate) ring forms the isolation region between the low-voltage power transistors. These low-voltage power transistors refer to MOS transistor structures composed of multiple N-type or P-type dopants. This MOS transistor structure can have more than one polysilicon strip, correspondingly with multiple N-type or P-type doped active regions. At least one first metal wire layer is connected in parallel to the bulk ring. The first metal wire is designed to be as wide as possible within the chip area. Where possible, multiple layers of metal wires are connected in parallel to the first metal wire. Polysilicon strips are generally used as the gates of MOS transistors.

[0055] exist Figure 5 In the example, each low-voltage power transistor has four polysilicon strips, each flanked by doped active regions. That is, the four polysilicon strips are alternately arranged with five doped active regions, which are alternately connected to potentials A and B. The doped active region connected to potential A is the first doped active region, and the doped active region connected to potential B is the second doped active region. At least one layer of second metal wire is connected in parallel to the doped active region. The doped active region is connected to potentials A and B via at least one second metal wire and contact holes, with the locations of the contact holes representing the connection points. The black boxes surrounding A and B in the figure can be considered the metal layers connecting potentials A and B, respectively. The second metal wire can be located on the same layer as the first metal wire and formed simultaneously using the same process. The second metal wire is designed to be as wide as possible, as long as the chip area allows. When conditions permit, as many layers of metal wires as possible are connected in parallel to the second metal wire. The polysilicon strips in the low-voltage power transistor are connected to external circuits via third metal wires and contact holes.

[0056] Optionally, when the polysilicon strips are placed horizontally, the two ends of each polysilicon strip in each column of adjacent low-voltage power tubes are connected by two third metal wires respectively, and connected to the external circuit through the third metal wires, and the location of the contact hole is the connection point.

[0057] Optionally, when the polysilicon strips are placed vertically, both ends of each polysilicon strip in each row of low-voltage power tubes are connected via two third metal wires, and are connected to an external circuit via the third metal wires, and the location of the contact hole is the connection point.

[0058] Figure 6 A schematic structural diagram of a substrate selection tube according to an embodiment of the present utility model is shown.

[0059] See also Figure 6The bulk (substrate) ring forms the isolation region between the substrate select transistors (SSTs). Here, SSTs refer to MOS transistors constructed with multiple N-type or P-type dopants. This MOS structure can contain more than one polysilicon strip, correspondingly with multiple N-type or P-type doped active regions. At least one first metal wire layer is connected in parallel to the substrate ring. The first metal wire is designed to be as wide as possible within the chip area. When conditions permit, multiple layers of metal wires are connected in parallel to the first metal wire. Polysilicon strips are generally used as the gates of MOS transistors.

[0060] Optionally, the number of polysilicon strips in each substrate selection tube is equal to the number of polysilicon strips in each low-voltage power tube.

[0061] exist Figure 6 In the example, each substrate selection transistor has four polysilicon strips, each with doped active regions on both sides. That is, the four polysilicon strips are alternately arranged with the five doped active regions. At least one layer of second metal wire is connected in parallel to the doped active region. The second metal wire and the first metal wire can be located on the same layer and formed simultaneously using the same process. The second metal wire is designed to be as wide as possible when the chip area allows. When conditions permit, as many layers of metal wires as possible are connected in parallel to the second metal wire. In the first substrate selection transistor, the first doped active region is connected to its substrate via at least one layer of second metal wire, and the second doped active region is connected to the potential at point A via at least one layer of second metal wire and a contact hole. The polysilicon strips of each first substrate selection transistor are interconnected via at least one layer of third metal wire and a contact hole, and connected to the potential at point B via at least one layer of third metal wire and a contact hole. The first doped active region serves as the source of the first substrate selection transistor, and the second doped active region serves as the drain of the first substrate selection transistor. In the second substrate selection transistor, the first doped active region is connected to the substrate via at least one layer of second metal wires, and the second doped active region is connected to the potential at point B via at least one layer of second metal wires and contact holes. The polysilicon strips of each second substrate selection transistor are interconnected and connected to the potential at point A via at least one layer of third metal wires and contact holes. The first doped active region serves as the source of the second substrate selection transistor, and the second doped active region serves as the drain of the second substrate selection transistor. The black boxes surrounding A and B in the figure can be considered the metal layers connecting the potentials at points A and B, respectively.

[0062] Optionally, the polysilicon strips in the substrate selection tube and the polysilicon strips in the low-voltage power tube are in the same direction.

[0063] In the pair Figure 6 If the substrate selection tube mentioned in the description is not marked as the first substrate selection tube or the second substrate selection tube, it means that it includes the first substrate selection tube and the second substrate selection tube.

[0064] It is understandable that Figure 5 The structure and Figure 6 The structures of the substrate selection tubes in the figure are exemplary. To ensure the symmetry of the substrate selection tube wiring and the accuracy of the connection line resistance, the number of polysilicon strips is generally set to an even number, such as 2 or 4, and the number of doped active regions is correspondingly set to 3 or 5.

[0065] Optionally, the structural schematic diagram of the third substrate selection tube is the same as that of the first substrate selection tube. The structural schematic diagram of the fourth substrate selection tube is the same as that of the second substrate selection tube.

[0066] Figure 7 A two-dimensional schematic diagram of the connection between the substrate selection tube and the low-voltage power tube according to the first embodiment of the utility model is shown.

[0067] See also Figure 7 Taking the horizontal placement of polysilicon strips in low-voltage power tubes as an example, it shows a schematic diagram of the connection between the first row of low-voltage power tubes, the second row of low-voltage power tubes, the first substrate selection tube, and the second substrate selection tube in one group of low-voltage power tube arrays when the number of rows of low-voltage power tubes in each group of low-voltage power tube arrays is 4 and each row of low-voltage power tubes includes 2 low-voltage power tubes.

[0068] The chip layout structure of a power MOS tube provided by the present invention includes at least two groups of low-voltage power tube arrays, each group of low-voltage power tube arrays including multiple rows of low-voltage power tubes arranged along a first direction; and multiple rows of first substrate selection tubes and second substrate selection tubes. Among them, at least one row of first substrate selection tubes and second substrate selection tubes is arranged between the multiple rows of low-voltage power tubes in each group of low-voltage power tube arrays, thereby improving the uniformity of the low-voltage power tube substrate parameters, reducing the risk of chip breakdown due to surge signals, and maximally saving chip area.

[0069] In a preferred embodiment, the chip layout structure of the power MOS tube also includes multiple third substrate selection tubes and fourth substrate selection tubes. The multiple third substrate selection tubes and fourth substrate selection tubes are alternately arranged in the second direction with the low-voltage power tube, the first substrate selection tube or the second substrate selection tube, and the intervals between the third substrate selection tubes and the fourth substrate selection tubes are alternately arranged in sequence, thereby further improving the uniformity of the low-voltage power tube substrate parameters.

[0070] While the embodiments of the present invention are described above, these embodiments do not exhaustively describe all details, nor do they limit the present invention to specific embodiments. Clearly, many modifications and variations are possible based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A chip layout structure of a power MOS tube, characterized in that: include: At least two groups of low-voltage power tube arrays, each group of low-voltage power tube arrays includes multiple rows of low-voltage power tubes arranged along a first direction; and a plurality of rows of first substrate selection tubes and second substrate selection tubes; At least one row of first substrate selection tubes and second substrate selection tubes is arranged between multiple rows of low-voltage power tubes in each group of low-voltage power tube arrays.

2. The chip layout structure according to claim 1, characterized in that: Also includes: A plurality of third substrate selection tubes and a fourth substrate selection tube are arranged alternately in sequence with the low-voltage power tube, the first substrate selection tube or the second substrate selection tube in a second direction, and the third substrate selection tubes and the fourth substrate selection tubes are arranged alternately in sequence with intervals between them, wherein the second direction is perpendicular to the first direction.

3. The chip layout structure according to claim 2, characterized in that: The third substrate selection tube and the fourth substrate selection tube are continuous in the first direction.

4. The chip layout structure according to claim 3, characterized in that: in, Each group of low-voltage power tube arrays includes multiple rows of low-voltage power tubes in an even number, and the at least one row of first substrate selection tubes and the at least one row of second substrate selection tubes are arranged in the middle position of the multiple rows of low-voltage power tubes in each group of low-voltage power tube arrays.

5. The chip layout structure according to claim 4, characterized in that: Each low-voltage power tube has the same size as each first substrate selection tube and each second substrate selection tube, and all are MOS tubes of the first size; Each third substrate selection tube and each fourth substrate selection tube have the same size, and are both MOS tubes of a second size, where the second size is different from the first size.

6. The chip layout structure according to claim 5, characterized in that: The second size is smaller than the first size.

7. The chip layout structure according to claim 6, characterized in that: Each low-voltage power tube and each substrate selection tube are spaced apart from other MOS tubes by a substrate region of the MOS tube, and at least one layer of first metal wire is connected in parallel to the substrate region.

8. The chip layout structure according to claim 7, characterized in that: Each low-voltage power tube and each substrate selection tube includes an even number of polysilicon strips. Doped active regions are provided on both sides of each polysilicon strip. At least one layer of second metal wire is connected in parallel to the doped active region. The doped active region includes alternating first doped active regions and second doped active regions. The number of polysilicon strips in each substrate selection tube is equal to the number of polysilicon strips in each low-voltage power tube.

9. The chip layout structure according to claim 8, characterized in that: The first doped active area of ​​each low-voltage power tube is connected to the first potential through at least one layer of second metal wire and contact hole, the second doped active area is connected to the second potential through at least one layer of second metal wire and contact hole, and an even number of polysilicon strips are connected to the external circuit through at least one layer of third metal wire and contact hole.

10. The chip layout structure according to claim 8, characterized in that: The first doped active region of each first substrate selection transistor and the third substrate selection transistor is connected to its substrate through at least one layer of second metal wire, the second doped active region is connected to the first potential through at least one layer of second metal wire and contact holes, an even number of polysilicon strips are interconnected through at least one layer of third metal wire and contact holes and connected to the second potential through at least one layer of third metal wire and contact holes, and the substrate is connected to the substrate of the low-voltage power transistor through at least one layer of first metal wire; The first doped active region of each second substrate selection tube and the fourth substrate selection tube is connected to its substrate through at least one layer of second metal wire, the second doped active region is connected to the second potential through at least one layer of second metal wire and contact hole, an even number of polysilicon strips are interconnected through at least one layer of third metal wire and contact hole and connected to the first potential through at least one layer of third metal wire and contact hole, and the substrate is connected to the substrate of the low-voltage power tube through at least one layer of first metal wire.

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