Semiconductor device and system for semiconductor device

Abstract

The utility model provides a semiconductor device and a system used for the semiconductor device. The metal grid of the pixel array may be patterned to have openings of different sizes over the photodiodes. Accordingly, a uniform pixel array having photodiodes of different sensitivities can be formed. For example, a pixel array may include a low sensitivity photodiode (LSPD), a medium sensitivity photodiode (MSPD), and a high sensitivity photodiode (HSPD). The LSPD, the MSPD, and the HSPD have different capture rates. Accordingly, a higher dynamic range can be achieved by combining the signals of the LSPD, MSPD, and HSPD.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a system for the semiconductor device. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensors use light-sensitive CMOS circuitry to convert light energy into electrical energy. The light-sensitive CMOS circuitry can include a photodiode formed in a silicon substrate. When the photodiode is exposed to light, an electrical charge (called photocurrent) is induced in the photodiode. The photodiode can be coupled to a switching transistor that samples the charge in the photodiode. Color can be determined by placing a filter across the light-sensitive CMOS circuitry.

[0003] The light received by a CMOS pixel sensor is typically based on three primary colors: red, green, and blue (R, G, B). A pixel sensor that senses each color of light can be defined by using a color filter that allows specific wavelengths of light to enter the photodiode. Some pixel sensors can include a near-infrared (NIR) pass-through filter that blocks visible light while allowing NIR light to pass through to the photodiode. Utility Model Content

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a first photodiode associated with a first opening in a metal layer; and a second photodiode associated with a second opening in the metal layer, wherein the second opening is smaller than the first opening, and wherein a ratio of a size of the first photodiode to a size of the second photodiode is in a range of approximately 0.9 to approximately 1.1.

[0005] An embodiment of the present invention provides a system for a semiconductor device, comprising: a pixel sensor, comprising: a metal layer configured to reflect light; a group of first photodiodes associated with a group of corresponding first openings in the metal layer; a group of second photodiodes, each of the second photodiodes having approximately the same size as each of the first photodiodes, associated with a group of corresponding second openings in the metal layer, each of the second openings being smaller than each of the first openings; an isolation structure; and a circuit configured to output electrical signals from the group of the first photodiodes and the group of the second photodiodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a diagram of an exemplary pixel array described herein.

[0008] Figures 2A-2C is a diagram of an exemplary semiconductor structure described herein.

[0009] Figures 3A-3C is a diagram of exemplary subpixels described herein.

[0010] Figures 4A-4C is a diagram of an exemplary pixel sensor as described herein.

[0011] Figures 5A-5C is a diagram of an exemplary pixel sensor described herein.

[0012] Figures 6A-6C is a diagram of an exemplary pixel sensor described herein.

[0013] Figures 7A-7C is a diagram of an exemplary pixel sensor described herein.

[0014] Figures 8A-8C is a diagram of an exemplary pixel sensor described herein.

[0015] Figures 9A-9E is a diagram of an exemplary implementation described herein.

[0016] Figure 10 is a flow chart of an exemplary process associated with forming the semiconductor structures described herein.

[0017] [Explanation of Reference Numerals]

[0018] 100, 360: pixel array

[0019] 102, 200, 230, 260: pixel sensors

[0020] 202: Photodiode

[0021] 204: Isolation Structure

[0022] 206: substrate

[0023] 208:Metal layer

[0024] 210, 232, 262, 902, 904, 906: Open

[0025] 212, 212a, 212b, 212c: District

[0026] 908, 908a, 908b, 908c: passivation layer

[0027] 214: Microlens

[0028] 300, 330: Pixel array

[0029] 302: Sub-pixel

[0030] 304, 400, 500, 600, 700, 800: pixels

[0031] 402, 402a, 402b: Node

[0032] 404, 534: Gate

[0033] 404a, 404b, 404c, 404d: transfer gates

[0034] 430, 530, 630, 730, 830: Circuit

[0035] 434: Reset gate

[0036] 436:Capacitor

[0037] 438, 440: Transistors

[0038] 442, 442a, 442b: Ground nodes

[0039] 444: Read out node

[0040] 460, 560, 660, 760, 860: Chart

[0041] 536:GC Gate

[0042] 900: Exemplary Implementation

[0043] 910: dielectric layer

[0044] 1000: Craftsmanship

[0045] 1010, 1020, 1030: Blocks DETAILED DESCRIPTION

[0046] The following utility model content provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the utility model content. Of course, these specific examples are merely examples and are not intended to be restrictive. For example, in the following description, a first feature is formed above or on a second feature, which may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature can be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the utility model content may repeat the figure numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0047] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of a component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0048] The dynamic range of an image sensor is based on the capacitance of the sensor relative to the noise in the image sensor (e.g., measured in electrons). This range is typically expressed in decibels (dB). To increase the dynamic range, an image sensor can include a pixel array with a large photodiode (LPD) and a small photodiode (SPD). The LPD and SPD have different capture rates. By combining the signals from the LPD and SPD, the capacitance of the sensor is increased, thereby achieving a larger dynamic range. However, due to the different sizes of the LPD and SPD, the pixel array is somewhat irregular, which reduces the effectiveness of the isolation structures (e.g., shallow trench isolation (STI) and backside deep trench isolation (BDTI)). In addition, the formation of the isolation structures can be complex (e.g., resulting in increased power, process resource and raw material consumption, and an increased process window). As a result, dark performance is degraded due to increased photodiode leakage.

[0049] One way to increase dynamic range is to use a lateral overflow integrated capacitance (LOFIC) sensor. Due to the increased capacitance of a LOFIC sensor compared to a combined LPD and SPD, a dynamic range of approximately 120 dB can be achieved. However, to further increase the dynamic range of a LOFIC sensor (e.g., to 140 dB or more), additional exposures are required, which can result in motion artifacts and image blur.

[0050] In order to reduce crosstalk between pixel sensors on a pixel array, a metal grid is typically deposited over the openings on the photodiodes of the pixel array. Photodiodes Some of the embodiments described herein above provide techniques and apparatus for patterning a metal grid with openings of different sizes over a photodiode. Thus, a uniform pixel array of photodiodes of different sensitivities can be formed. For example, a pixel array can include a low-sensitivity photodiode (LSPD), a medium-sensitivity photodiode (MSPD), and a high-sensitivity photodiode (HSPD). The LSPD, MSPD, and HSPD have different capture rates. Therefore, a higher dynamic range can be achieved by combining the signals of the LSPD, MSPD, and HSPD. For example, due to the increased capacitance, the pixel array can achieve a dynamic range of approximately 140 dB or more. In addition, the pixel array exhibits better dark performance than a pixel array combining LPDs and SPDs. Since each photodiode in the pixel array is approximately the same size, photodiode leakage is reduced compared to an irregular pixel array including a combination of LPDs and SPDs.

[0051] In some examples, the dynamic range is further extended by adding LOFIC to the LSPD used in the pixel array. Additionally or alternatively, multiple photodiodes in the pixel array can share a single microlens. Thus, phase detection auto focus (PDAF) can be performed using the signal from the HSPD of the shared single microlens.

[0052] Figure 1 is a diagram of an exemplary pixel array 100 (or portion thereof) described herein. Pixel array 100 may be included in an image sensor, such as a complementary metal oxide semiconductor (CMOS) image sensor, a backside illuminated (BSI) CMOS image sensor, or other type of image sensor.

[0053] Figure 1 1 shows a top view of the pixel array 100. Figure 1 As shown, the pixel array 100 may include a plurality of pixel sensors 102. Figure 1 As further shown, pixel sensors 102 can be configured as a grid. In some examples, pixel sensors 102 are square (as exemplarily shown in FIG. 2 ). In some examples, pixel sensors 102 include other shapes, such as circular, octagonal, diamond, and / or other shapes.

[0054] Pixel sensor 102 may be configured to sense and / or accumulate incident light (e.g., light directed toward pixel array 100). For example, pixel sensor 102 may absorb photons of incident light and accumulate them in a photodiode. The accumulation of photons in the photodiode may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a greater intensity or brightness, and a lower amount of charge may correspond to a lower intensity or brightness).

[0055] Pixel array 100 may be electrically connected to a back-end-of-line (BEOL) metallization stack (not shown) of an image sensor. The BEOL metallization stack may electrically connect pixel array 100 to control circuitry that may be used to measure the accumulation of incident light in pixel sensor 102 and convert the measurement into an electrical signal.

[0056] As described above, FIG2 is provided as an example. Other examples may differ from the description in FIG2. For example, the pixel sensor 102 may be provided by an isolation structure (e.g., such as a combination of Figure 2A and 2C The isolation structure may include a plurality of interconnected trenches filled with a dielectric material, such as an oxide material, for electrical and optical isolation. The trenches of the isolation structure may be included around the periphery of the pixel sensor 102 so that the isolation structure surrounds the pixel sensor 102. In addition, the trenches of the isolation structure may extend into the substrate in which the pixel sensor 102 is formed to surround the photodiodes and other structures of the pixel sensor 102 in the substrate. In some examples, the isolation structure includes a backside DTI (BDTI) structure having a high aspect ratio formed by the back side of the pixel array 100.

[0057] Figure 2A is a diagram of an exemplary pixel sensor 200 described herein. The exemplary pixel sensor 200 includes a metal grid opening associated with a large capacitance; therefore, the photodiode in the exemplary pixel sensor 200 is a HSPD. In some examples, Figure 2A The exemplary pixel sensor 200 shown in FIG. 1 may include the pixel array 100 (or a portion thereof), or may be included in the pixel array 100 (or a portion thereof). In some examples, the exemplary pixel sensor 200 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0058] Pixel sensor 200 may include a photodiode 202. Photodiode 202 may include a region of a substrate (e.g., substrate 206) doped with multiple types of ions to form a PN junction or a PIN junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, the substrate may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of photodiode 202 and a p-type dopant to form a second portion (e.g., a p-type portion) of photodiode 202. Photodiode 202 may be configured to absorb incident light photons. The absorption of photons causes photodiode 202 to accumulate charge (referred to as photocurrent) due to the photoelectric effect. Here, photons strike photodiode 202, resulting in the emission of electrons from photodiode 202. The emission of electrons results in the formation of electron-hole pairs, where the electrons migrate toward the cathode of photodiode 202 and the holes migrate toward the anode, generating photocurrent.

[0059] Isolation structure 204 can surround photodiode 202. Isolation structure 204 provides optical isolation by blocking or preventing light from diffusing or leaking from pixel sensor 200 to another pixel sensor, thereby reducing crosstalk between adjacent pixel sensors. Isolation structure 204 can include a trench or DTI structure coated or lined with an anti-reflective coating (ARC) and filled with a dielectric layer (e.g., above the ARC). Isolation structure 204 can be formed in a grid layout, where isolation structure 204 extends around the perimeter of the pixel sensors in a pixel array (e.g., pixel array 100) and intersects at various locations in the pixel array. In some examples, isolation structure 204 is formed in the back side of substrate 206 and can be referred to as a BDTI structure.

[0060] Substrate 206 may include a semiconductor die substrate, a semiconductor wafer, or another type of substrate in which semiconductor pixels may be formed. In some examples, substrate 206 is formed of silicon (Si), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon-on-insulator (SOI), or another type of semiconductor material that enables it to generate charge from photons of incident light.

[0061] Metal layer 208 may be included on and / or over substrate 206 (e.g., over photodiode 202 and isolation structure 204). Metal layer 208 may include a metal material, such as tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), another conductive material, and / or an alloy including one or more of the foregoing. Metal layer 208 may be etched to form a grid structure between pixel sensors in a pixel array (e.g., pixel array 100). For example, the grid structure may include a plurality of interconnected pillars of metal layer 208, wherein the cross-section of the pillars is Figure 2A The grid structure may surround the perimeter of the pixel sensor 200 and may be configured to provide additional crosstalk reduction and / or mitigation in conjunction with the isolation structure 204 .

[0062] In some examples, to further reduce crosstalk, a dielectric layer and / or air gap is included in the grid structure. For example, the dielectric layer may include an oxide material, such as silicon oxide (SiO x ) (e.g., silicon dioxide (SiO2)), silicon nitride (SiN x ), silicon carbide (SiC x ), titanium nitride (TiN x ), tantalum nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), or aluminum oxide (AlO x ), or another dielectric material capable of providing optical isolation. Additionally or alternatively, an air gap can provide optical isolation because the refractive index of air is very low (approximately less than 1.0001, which is very close to the refractive index of a vacuum defined as 1), so incident light is likely to be totally reflected in the air gap.

[0063] like Figure 2A As shown, opening 210 is formed in metal layer 208 and above photodiode 202. In some examples, the ratio of the width associated with opening 210 (e.g., represented by w1 in pixel sensor 200) to the pitch associated with pixel sensor 200 is in a range of about 0.8 to about 1.0. By selecting a ratio of at least 0.8, photodiode 202 of pixel sensor 200 is used as an HSPD - selecting a smaller ratio may result in excessive light being blocked. Figure 2A As shown, the width associated with the opening 210 can be approximately equal to the length associated with the opening 210 (e.g., within a 5% or 10% error range). Thus, the opening 210 is approximately square. Alternatively, the width associated with the opening 210 can be greater than the length associated with the opening 210, as shown in FIG. Figure 3C As stated.

[0064] In some examples, pixel sensor 200 further includes at least one light reduction filter (LRF). For example, the LRF can be formed above photodiode 202 and below metal layer 208 and / or can be formed above metal layer 208 and below color filter region 212. The at least one LRF can be combined with opening 210 to allow for adjustment of the amount of light reaching photodiode 202.

[0065] A passivation layer may be included over metal layer 208 and over portions of substrate 206 not covered by metal layer 208. The passivation layer may include an oxide material to provide protection for layers below the passivation layer and structures formed above the passivation layer.

[0066] A color filter region 212 may be included above the photodiode 202 and on the passivation layer. The color filter region 212 may be configured to filter incident light to allow specific wavelengths of incident light to pass through the photodiode 202. For example, the color filter region 212 may filter red light (thus, the pixel sensor 200 may be a red pixel sensor), the color filter region 212 may filter green light (thus, the pixel sensor 200 may be a green pixel sensor), or the color filter region 212 may filter blue light (thus, the pixel sensor 200 may be a blue pixel sensor). The blue filter region may allow incident light with a wavelength of 450 nanometers (nm) near the component to pass through the color filter region 212 and block other wavelengths. The green filter region may allow incident light with a wavelength of 550 nanometers near the component to pass through the color filter region 212 and block other wavelengths. The red filter region may allow incident light with a wavelength of 650 nanometers near the component to pass through the color filter region 212 and block other wavelengths. The yellow filter region may allow components of incident light near a 580 nanometer wavelength to penetrate the color filter region 212 and block other wavelengths from passing through.

[0067] In some examples, color filter region 212 is non-discriminating or non-filtering (thus, pixel sensor 200 can be a white pixel sensor). A non-discriminating or non-filtering color filter region can include a material that allows all wavelengths of light to enter an associated photodiode 202 (e.g., to determine overall brightness to increase the light sensitivity of the image sensor). In some examples, color filter region 212 can be a near infrared (NIR) bandpass color filter region (thus, pixel sensor 200 can be an NIR pixel sensor). An NIR bandpass color filter region can include a material that allows a portion of incident light in the NIR wavelength range to pass to an associated photodiode 202 while blocking visible light.

[0068] Microlens 214 may be included on and / or above color filter region 212. Microlens 214 may be formed to focus incident light toward photodiode 202 of pixel sensor 200. Since photodiode 202 of pixel sensor 200 is an HSPD, microlens 214 may be set to have a larger focal length.

[0069] Figure 2Bis a diagram of an exemplary pixel sensor 230 described herein. The exemplary pixel sensor 230 includes a metal grid opening associated with a medium capacitance; accordingly, the photodiode in the exemplary pixel sensor 230 is a MSPD. In some examples, Figure 2B The exemplary pixel sensor 230 shown in FIG may include pixel array 100 (or a portion thereof), or may be included in pixel array 100 (or a portion thereof). In some examples, the exemplary pixel sensor 230 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0070] Figure 2B An exemplary pixel sensor 230 with Figure 2A The exemplary pixel sensor 200 is similar to that of FIG. Figure 2B As shown, the width associated with the opening 232 in the metal layer 208 (e.g., Figure 2B The ratio of the pitch associated with the pixel sensor 230 (denoted by w2 in FIG. 1 ) to the pitch associated with the pixel sensor 230 is in the range of about 0.5 to about 0.8. Selecting a ratio of at least 0.5 allows the photodiode 202 of the pixel sensor 200 to function as an MSPD—selecting a smaller ratio would block too much light. Selecting a ratio of no more than 0.8 also allows the photodiode 202 of the pixel sensor 200 to function as an MSPD—selecting a larger ratio would allow too much light to enter. Figure 2B As shown, the width associated with the opening 232 can be approximately equal to the length associated with the opening 232 (e.g., within a 5% or 10% error range). Thus, the opening 232 is approximately square. Alternatively, the width associated with the opening 232 can be greater than the length associated with the opening 232, as shown in FIG. Figure 3C As stated.

[0071] Figure 2C is a diagram of an exemplary pixel sensor 260 described herein. The exemplary pixel sensor 260 includes a metal grid opening associated with low capacitance; therefore, the photodiode in the exemplary pixel sensor 260 is a LSPD. In some examples, Figure 2C The exemplary pixel sensor 260 shown in FIG may include pixel array 100 (or a portion thereof), or may be included in pixel array 100 (or a portion thereof). In some examples, exemplary pixel sensor 260 may be included in an image sensor. The image sensor may be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0072] Figure 2C An exemplary pixel sensor 260 with Figure 2A The exemplary pixel sensor 200 is similar to that of FIG. Figure 2CAs shown, the width associated with the opening 262 in the metal layer 208 (e.g., Figure 2C The ratio of the spacing associated with the pixel sensor 260 (represented by w3 in FIG) is in the range of about 0.2 to about 0.5. Selecting a ratio of at least 0.2 allows the photodiode 202 of the pixel sensor 200 to function - selecting a smaller ratio would block too much light and allow the light from the photodiode 202 to generate a detectable current. Selecting a ratio of no more than 0.5 allows the photodiode 202 of the pixel sensor 200 to function as an LSPD, and selecting a larger ratio would allow too much light to enter. Figure 2C As shown, the width associated with the opening 262 can be approximately equal to the length associated with the opening 262 (e.g., within a 5% or 10% error range. Thus, the opening 262 is approximately square. Alternatively, the width associated with the opening 262 can be greater than the length associated with the opening 262, as shown in conjunction with Figure 3C As stated.

[0073] Pixel sensors 200, 230, and / or 260 may be combined in a pixel array (e.g., Figure 1 Pixel array 100). Pixel sensors 200, 230, and 260 have different capture rates. Therefore, by combining the signals from pixel sensors 200, 230, and / or 260, a higher dynamic range can be achieved. Consequently, due to the increased capacitance of the pixel array, the pixel array can achieve a dynamic range of approximately 140 dB or higher. Furthermore, the pixel array exhibits improved dark performance compared to a pixel array combining LPD and SPD.

[0074] Furthermore, pixel sensors 200, 230, and 260 are all formed to be approximately the same size (e.g., each photodiode 202 has a volume that is within a 5% or 10% error range of the other photodiodes). For example, the ratio of the size of one photodiode to the size of another photodiode is in the range of about 0.9 to about 1.1. Consequently, leakage from the photodiodes in the pixel array is reduced compared to an irregular pixel array including a combination of LPDs and SPDs.

[0075] As mentioned above, providing Figures 2A-2C As an example. Other examples may be Figures 2A-2C Different than described.

[0076] Figure 3A is a diagram of an exemplary pixel array 300 described herein. Exemplary pixel array 300 includes a combination of approximately square HSPDs and approximately square LSPDs. In some examples, exemplary pixel array 300 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0077] like Figure 3A As shown, pixel array 300 includes HSPD (e.g., included in pixel sensor 200, as combined with Figure 2A ) and LSPD (e.g., included in pixel sensor 260, as combined Figure 2C ). The pixel array 300 may include a plurality of sub-pixels, such as sub-pixel 302. For example, each sub-pixel is Figure 3A A single pixel sensor 200 or a single pixel sensor 260 in the embodiment of the present invention. A "sub-pixel" is at least one pixel sensor that shares circuitry and / or microlenses with at least one other sub-pixel (e.g., as combined with Figures 4A-4C , 5A-5C, 6A-6C, 7A-7C and 8A-8C). Figure 3A In FIG. 3 , three HSPDs and one LSPD may include four sub-pixels that share circuitry and / or microlenses and form a pixel 304 in the pixel array 300 .

[0078] Figure 3B is a diagram of an exemplary pixel array 330 described herein. Exemplary pixel array 330 includes a combination of approximately square HSPDs, approximately square MSPDs, and approximately square LSPDs. In some examples, exemplary pixel array 330 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0079] like Figure 3B As shown, pixel array 330 includes HSPD (e.g., included in pixel sensor 200, as in combination with Figure 2A ), MSPD (eg, included in pixel sensor 230, as combined with Figure 2B ) and LSPD (e.g., included in pixel sensor 260, as combined Figure 2C ). Pixel array 330 may include a plurality of sub-pixels, such as sub-pixel 302. Figure 3B In FIG. 3 , two HSPDs, one MSPD, and one LSPD may include four sub-pixels that share circuitry and / or microlenses and form a pixel 304 in the pixel array 300 .

[0080] Figure 3Cis a diagram of an exemplary pixel array 360 described herein. Exemplary pixel array 330 includes a combination of elongated HSPDs and elongated LSPDs. In some examples, exemplary pixel array 360 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0081] like Figure 3C As shown, pixel array 360 includes HSPD (e.g., included in pixel sensor 200, as in combination with Figure 2A ) and LSPD (e.g., included in pixel sensor 260, as combined Figure 2C ). Pixel array 360 may include a plurality of sub-pixels, such as sub-pixel 302. Each sub-pixel is associated with an opening in a metal layer having a width greater than a length, such as Figure 3C In addition, Figure 3C In FIG. 3 , one HSPD and one LSPD may include two sub-pixels that share circuitry and / or microlenses and form a pixel 304 in the pixel array 300 .

[0082] As mentioned above, providing Figures 3A-3C As an example. Other examples may be related to Figures 3A-3C Different than described.

[0083] Figure 4A is a diagram of an exemplary pixel 400 described herein. Exemplary pixel 400 includes pixel sensor 200 having an HSPD (as a subpixel) and pixel sensor 260 having an LSPD (as a subpixel). In some examples, exemplary pixel 400 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0084] like Figure 4A As shown, pixel sensor 200 and pixel sensor 260 share a floating diffusion (FD) node 402. Therefore, transfer gate 404a associated with pixel sensor 200 and transfer gate 404b associated with pixel sensor 260 both direct signals to the same FD node 402. Using the same FD node 402 can simplify the design, thereby saving power, process resources, and material resources during manufacturing.

[0085] In some implementations, pixel sensors 200 and 260 can share a microlens. Using a shared microlens can simplify the design, thereby saving power, process resources, and material resources during manufacturing. Alternatively, pixel sensor 200 can use a different microlens than pixel sensor 260 (e.g., a microlens with a shorter focal length). Using different microlenses can increase the accuracy of the signal from each pixel sensor.

[0086] Figure 4B is a diagram of an exemplary circuit 430 described herein. Figure 4A 4 shows an exemplary circuit 430. In some examples, the exemplary circuit 430 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0087] like Figure 4B As shown, the signal from the photodiode of pixel sensor 200 is controlled by transfer gate 404a, and the signal from the photodiode of pixel sensor 260 is controlled by transfer gate 404b. In addition, reset gate 434 resets pixel 400 to zero charge using ground node 442. In some examples, to store additional charge from pixel sensors 200 and 260 under brighter conditions, a dual conversion gain (DCG) capacitor 436 is included near FD node 402. Source follower (SF) transistor 438 and row selector (RS) transistor 440 control the output of signals from pixel sensors 200 and 260 to readout node 444.

[0088] Figure 4C is a diagram of an exemplary range chart 460 described herein. Figure 4A An exemplary range chart 460 is shown for an exemplary pixel 400. Figure 4C As shown, the total capacitance of pixel 400 increases because the exposure time associated with pixel sensor 260 follows the exposure time associated with pixel sensor 200. Therefore, the total signal obtained by combining the signals from pixel sensors 200 and 260 is larger, and thus a greater dynamic range (e.g., at least 140 dB) is achieved for pixel 400.

[0089] As mentioned above, providing Figures 4A-4C As an example. Other examples may be related to Figures 4A-4C For example, MSPD can be used instead of HSPD or LSPD.

[0090] Figure 5Ais a diagram of an exemplary pixel 500 described herein. Exemplary pixel 500 includes pixel sensor 200 having an HSPD (as a subpixel) and pixel sensor 260 having an LSPD (as a subpixel). In some examples, exemplary pixel 500 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0091] like Figure 5A As shown, pixel sensor 200 is associated with first FD node 402a, and pixel sensor 260 is associated with second FD node 402b. Furthermore, transfer gate 404a directs the signal from pixel sensor 200 to first FD node 402a, and transfer gate 404b directs the signal from pixel sensor 260 to second FD node 402b. Using separate FD nodes allows the use of LOFIC to further increase the dynamic range of pixel 500.

[0092] In some embodiments, pixel sensors 200 and 260 can share a microlens. Using a shared microlens can simplify the design, thereby saving power, process resources, and raw material resources during manufacturing. Alternatively, pixel sensor 200 can use a different microlens than pixel sensor 260 (e.g., a microlens with a shorter focal length). Using different microlenses can increase the accuracy of the signal from each pixel sensor.

[0093] Figure 5B is a diagram of an exemplary circuit 530 described herein. Figure 5A 5. Example pixel 500 of FIG. 5 shows example circuit 530. In some examples, example circuit 530 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0094] like Figure 5BAs shown, the signal from the photodiode of pixel sensor 200 is directed to FD node 402a by transfer gate 404a, and the signal from the photodiode of pixel sensor 260 is directed to FD node 402b by transfer gate 404b. In addition, reset gate 434 resets pixel 500 to zero charge using ground node 442a. In some examples, to store additional charge from pixel sensor 200 under brighter conditions, DCG capacitor 436 is included near FD node 402a. Similarly, to store additional charge from pixel sensor 200, LOFIC 532 is included near FD node 402b and controlled by gain control (GC) gate 534. LOFIC 532 is also associated with ground node 442b. SF transistor 438 and RS transistor 440, combined with GC gate 536, control the output of signals from pixel sensors 200 and 260 to readout node 444.

[0095] Figure 5C is a diagram of an exemplary range chart 560 described herein. Figure 5A An exemplary range chart 560 is shown for an exemplary pixel 500. Figure 5C As shown, the total capacitance of pixel 500 increases because the exposure time associated with pixel sensor 260 follows the exposure time associated with pixel sensor 200. In addition, LOFIC 532 further increases the exposure time associated with pixel sensor 260. Therefore, the total signal achieved is greater, and thus a greater dynamic range (e.g., at least 140 dB) is achieved for pixel 500.

[0096] As mentioned above, providing Figures 5A-5C As an example. Other examples may be related to Figures 5A-5C For example, MSPD can be used instead of HSPD or LSPD.

[0097] Figure 6A is a diagram of an exemplary pixel 600 described herein. Exemplary pixel 600 includes pixel sensor 200 having three HSPDs (as subpixels) and pixel sensor 260 having one LSPD (as subpixel). In some examples, exemplary pixel 600 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSICMOS image sensor, or another type of image sensor.

[0098] like Figure 6AAs shown, pixel sensor 200 and pixel sensor 260 share a common FD node 402. Therefore, transfer gates 404a, 404b, and 404c associated with pixel sensor 200 and transfer gate 404d associated with pixel sensor 260 all direct signals to the same FD node 402. Using the same FD node 402 can simplify the design, thereby saving power, process resources, and material resources during manufacturing.

[0099] In some embodiments, pixel sensors 200 and 260 can share a microlens. Using a shared microlens can simplify the design, thereby saving power, process resources, and raw material resources during manufacturing. In addition, the use of a shared microlens allows PDAF to be performed using signals from different HSPDs in pixel 600. For example, PDAF in the horizontal direction can be performed by using a transfer gate 404a that is separate from the transfer gate 404b. Similarly, PDAF in the vertical direction can be performed by using a transfer gate 404b that is separate from the transfer gate 404c. Alternatively, pixel sensor 200 can use a different microlens from pixel sensor 260 (for example, a microlens with a shorter focal length). Using different microlenses can increase the accuracy of the signal from each pixel sensor.

[0100] Figure 6B is a diagram of an exemplary circuit 630 described herein. Figure 6A 6 shows an exemplary circuit 630. In some examples, the exemplary circuit 630 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0101] like Figure 6B As shown, the signal from the photodiode of pixel sensor 200 is controlled by transfer gates 404a, 404b, 404c, and the signal from the photodiode of pixel sensor 260 is controlled by transfer gate 404d. In addition, reset gate 434 resets pixel 600 to zero charge using ground node 442. In some examples, to store additional charge from pixel sensors 200 and 260 under brighter conditions, a DCG capacitor 436 is included near FD node 402. SF transistor 438 and RS transistor 440 control the output of signals from pixel sensors 200 and 260 to readout node 444.

[0102] Figure 6C is a diagram of an exemplary range chart 660 described herein. Figure 6A An exemplary range chart 660 is shown for an exemplary pixel 600. Figure 6CAs shown, the total capacitance of pixel 600 increases because the exposure time associated with pixel sensor 260 follows the exposure time associated with pixel sensor 200. Therefore, the total signal obtained by combining the signals from pixel sensors 200 and 260 is larger, and thus a greater dynamic range (e.g., at least 140 dB) is achieved for pixel 600.

[0103] As mentioned above, providing Figures 6A-6C As an example. Other examples may be related to Figures 6A-6C For example, different combinations of LSPDs and HSPDs may be used (eg, two LSPDs and two HSPDs, among other examples).

[0104] Figure 7A is a diagram of an exemplary pixel 700 described herein. Exemplary pixel 700 includes two pixel sensors 200 with HSPDs (as subpixels), one pixel sensor 230 with MSPDs (as subpixels), and one pixel sensor 260 with LSPDs (as subpixels). In some examples, exemplary pixel 700 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0105] like Figure 7A As shown, pixel sensors 200, 230, and 260 share a common FD node 402. Therefore, transfer gates 404a and 404b associated with pixel sensor 200, transfer gate 404c associated with pixel sensor 230, and transfer gate 404d associated with pixel sensor 260 all direct signals to the same FD node 402. Using the same FD node 402 can simplify the design, thereby saving power, process resources, and material resources during manufacturing.

[0106] In some examples, pixel sensors 200, 230, and 260 can share a microlens. Using a shared microlens can simplify the design, thereby saving power, process resources, and raw material resources during manufacturing. Alternatively, pixel sensor 200 can use a different microlens (e.g., a microlens with a shorter focal length) than pixel sensor 230 and pixel sensor 260. Using different microlenses can increase the accuracy of the signal from each pixel sensor.

[0107] Figure 7B is a diagram of an exemplary circuit 730 described herein. Figure 7A 7 shows an exemplary circuit 730. In some examples, the exemplary circuit 730 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0108] like Figure 7B As shown, the signal from the photodiode of pixel sensor 200 is controlled by transfer gates 404a and 404b, the signal from the photodiode of pixel sensor 230 is controlled by transfer gate 404c, and the signal from the photodiode of pixel sensor 260 is controlled by transfer gate 404d. In addition, reset gate 434 resets pixel 700 to zero charge using ground node 442. In some examples, to store additional charge from pixel sensors 200, 230, and 260 under brighter conditions, a DCG capacitor 436 is included near FD node 402. SF transistor 438 and RS transistor 440 control the output of the control signal from pixel sensors 200, 230, and 260 to readout node 444.

[0109] Figure 7C is a diagram of an exemplary range chart 760 described herein. Figure 7A An exemplary range chart 760 is shown for an exemplary pixel 700. Figure 7C As shown, the total capacitance of pixel 700 increases because the exposure time associated with pixel sensor 260 follows the exposure time associated with pixel sensor 230, and the exposure time associated with pixel sensor 230 follows the exposure time associated with pixel sensor 200. Therefore, the total signal obtained by combining the signals from pixel sensors 200, 230, and 260 is larger, and thus a larger dynamic range (e.g., at least 140 dB) is achieved for pixel 700.

[0110] As mentioned above, providing Figures 7A-7C As an example. Other examples may be related to Figures 7A-7C For example, different combinations of LSPDs, MSPDs, and HSPDs may be used (e.g., two LSPDs with an MSPD and an HSPD, among other examples).

[0111] Figure 8A is a diagram of an exemplary pixel 800 described herein. Exemplary pixel 800 includes three pixel sensors 200 with HSPDs (as subpixels) and one pixel sensor 260 with LSPDs (as subpixels). In some examples, exemplary pixel 800 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSICMOS image sensor, or another type of image sensor.

[0112] like Figure 8AAs shown, pixel sensor 200 is associated with first FD node 402a, and pixel sensor 260 is associated with second FD node 402b. Additionally, transfer gates 404a, 404b, and 404c direct the signal from pixel sensor 200 to first FD node 402a, and transfer gate 404 directs the signal from pixel sensor 260 to second FD node 402b. Using separate FD nodes allows the use of LOFIC to further increase the dynamic range of pixel 800.

[0113] In some implementations, pixel sensors 200 and 260 can share a microlens. Using a shared microlens can simplify the design, thereby saving power, process resources, and raw material resources during manufacturing. In addition, using a shared microlens allows PDAF to be performed using signals from different HSPDs in pixel 800. For example, PDAF in the horizontal direction can be performed by using a transfer gate 404a that is separate from the transfer gate 404b. Similarly, PDAF in the vertical direction can be performed by using a transfer gate 404b that is separate from the transfer gate 404c. Alternatively, pixel sensor 200 can use a different microlens (e.g., a microlens with a shorter focal length) than pixel sensor 260. Using different microlenses can increase the accuracy of the signal from each pixel sensor.

[0114] Figure 8B is a diagram of an exemplary circuit 830 described herein. Figure 8A 8 shows an exemplary circuit 830. In some examples, the exemplary circuit 830 can be included in an image sensor. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or another type of image sensor.

[0115] like Figure 8B As shown, the signal from the photodiode of pixel sensor 200 is directed to FD node 402a by transfer gates 404a, 404b, and 404c, and the signal from the photodiode of pixel sensor 260 is directed to FD node 402b by transfer gate 404d. Furthermore, reset gate 434 resets pixel 800 to zero charge using ground node 442a. In some examples, to store additional charge from pixel sensor 200 under brighter conditions, DCG capacitor 436 is included near FD node 402a. Similarly, to store additional charge from pixel sensor 200, LOFIC 532 is included near FD node 402b and controlled by GC gate 534. LOFIC 532 is also associated with ground node 442b. SF transistor 438 and RS transistor 440, in combination with GC gate 536, control the output of signals from pixel sensors 200 and 260 to readout node 444.

[0116] Figure 8C is a diagram of an exemplary range chart 860 described herein. Figure 8A An exemplary range chart 860 is shown for an exemplary pixel 800. Figure 8C As shown, because the exposure time associated with pixel sensor 260 follows the exposure time associated with pixel sensor 200, the total capacitance of pixel 800 increases. Furthermore, LOFIC 532 further extends the exposure time associated with pixel sensor 260. Consequently, the total signal achieved is greater, and thus, a greater dynamic range (e.g., at least 140 dB) is achieved for pixel 800.

[0117] As mentioned above, providing Figures 8A-8C As an example. Other examples may be related to Figures 8A-8C For example, different combinations of LSPDs and HSPDs can be used (e.g., two LSPDs and two HSPDs, etc.).

[0118] Figures 9A-9E is a diagram of an exemplary embodiment 900 described herein. Exemplary embodiment 900 may be an exemplary process or method for forming a pixel array with openings of different sizes in a metal grid. Figures 9A-9E The result of the technique described in , produces photodiodes of approximately the same size but associated with openings of different sizes in the metal grid.

[0119] like Figure 9A As shown, an exemplary process for forming a pixel array can be performed in conjunction with substrate 206. As described above, substrate 206 can include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate in which semiconductor pixels can be formed. For example, substrate 206 can be made of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), SOI, or another type of semiconductor material capable of generating charge from photons of incident light. In some examples, substrate 206 is formed of a doped material (e.g., a p-type doped material or an n-type doped material) such as doped silicon.

[0120] Additionally, substrate 206 may have photodiodes 202 formed therein. For example, an ion implantation tool may use ion implantation techniques to dope portions of substrate 206 to form photodiodes 202. Substrate 206 may be doped with multiple types of ions to form a PN junction for each photodiode 202. For example, substrate 206 may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of photodiode 202 and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of photodiode 202. In some examples, photodiode 202 is formed using another technique, such as diffusion.

[0121] like Figure 9A As further shown in FIG, an isolation structure 204 (eg, a DTI structure) can be included in substrate 206 at least partially surrounding photodiode 202. Isolation structure 204 can be coated or lined with an ARC and filled with a dielectric layer (eg, over the ARC).

[0122] like Figure 9A As shown, metal layer 208 can be formed. For example, a deposition tool can form metal layer 208 on and / or over the front side surface of substrate 206 (e.g., over photodiode 202, isolation structure 204, and exposed portions of substrate 206) using spin coating, chemical vapor deposition (CVD), physical vapor deposition, PVD, atomic layer deposition (ALD), and / or other deposition techniques. In some examples, metal layer 208 can be formed over dielectric layers and / or buffer layers over photodiode 202, isolation structure 204, and exposed portions of substrate 206. In some embodiments, after deposition, a planarization tool planarizes metal layer 208 (e.g., using chemical mechanical planarization (CMP)). Although exemplary embodiment 900 shows metal layer 208 formed directly on isolation structure 204, other embodiments can include a passivation layer formed on isolation structure 204 (and optionally over photodiode 202 and / or exposed portions of substrate 206). Thus, the passivation layer may protect isolation structure 204 and / or photodiode 202 during the formation and patterning of metal layer 208. Additionally, the passivation layer may serve as an etch stop layer (ESL) during the formation of openings 902, 904, and 906, as described below.

[0123] like Figure 9BAs shown, metal layer 208 is patterned. For example, portions of metal layer 208 may be removed. In some examples, a deposition tool may form a photoresist layer on and / or over the front surface of metal layer 208, an exposure tool may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and a developer tool may develop the pattern and remove the photoresist layer to expose the pattern. Thus, an etching tool may etch (e.g., using a wet etching technique, a dry etching technique, a plasma-enhanced etching technique, and / or other types of etching techniques) portions of metal layer 208 to create an opening in metal layer 208 over photodiode 202. In some examples, as Figure 9B As shown, the surface of the photodiode 202 may be exposed. Alternatively, the surface of a dielectric layer or buffer layer disposed above the photodiode 202 may be exposed. After patterning the metal layer 208, a photoresist removal tool may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma asher, and / or another technique).

[0124] Although photodiodes 202 are approximately the same size, the sizes of their openings vary. For example, opening 902 can be larger than openings 904 and 906, allowing the photodiode associated with opening 902 to function as a HSPD. Similarly, opening 904 can be smaller than opening 902 but larger than opening 906, allowing the photodiode associated with opening 904 to function as a MSPD and the photodiode associated with opening 906 to function as a LSPD. Because photodiodes 202 are approximately the same size, the pixel array is regular, which improves the efficiency of the isolation structure and reduces photodiode leakage. Furthermore, compared to forming isolation structures in irregular pixel arrays, the formation of isolation structure 204 is simplified, saving power, process resources, and raw materials, and also reducing the process window. Furthermore, due to the different openings 902, 904, and 906, the capture rate of photodiode 202 also varies. Consequently, a higher dynamic range (e.g., approximately 140 dB or higher) is achieved due to the increased capacitance of the pixel array. Furthermore, the pixel array exhibits better dark performance than a pixel array combining LPDs and SPDs.

[0125] like Figure 9C As shown, a passivation layer 908a is formed in the opening 902, a passivation layer 908b is formed in the opening 904, and a passivation layer 908c is formed in the opening 906. For example, the deposition tool can use a spin coating technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique to form the passivation layer 908. The passivation layer 908 may include an oxide material, such as silicon oxide (SiOx). Additionally and / or alternatively, the passivation layer 908 may include silicon nitride (Si i Nx), silicon carbide (Si Cx) or a mixture thereof, such as silicon carbon nitride (SiCN), silicon oxynitride (SiON) or another dielectric material. In some embodiments, after deposition, the passivation layer 908 is planarized using a planarization tool (eg, using chemical mechanical polishing).

[0126] like Figure 9D As shown, color filter regions 212a, 212b, and 212c are formed for each photodiode 202. In exemplary embodiment 900, color filter regions 212a, 212b, and 212c are formed above passivation layers 908a, 908b, and 908c. Thus, color filter regions 212a, 212b, and 212c can be formed above metal layer 208. Additionally or alternatively, color filter regions 212a, 212b, and 212c can be at least partially formed within openings 902, 904, and 906. Thus, passivation layer 908 can be thinner than metal layer 208 or can be omitted entirely. In some examples, a deposition tool can deposit color filter regions 212 using a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, and / or another deposition technique. In some embodiments, after deposition, color filter regions 212 are planarized using a planarization tool (e.g., using chemical mechanical polishing).

[0127] like Figure 9E As shown, a microlens 214 is formed for each of the photodiodes 202. In exemplary embodiment 900, microlenses 214 are formed on and / or over color filter region 212. Because photodiodes 202 are associated with openings of different sizes in metal layer 208, microlenses 214 can be associated with different focal lengths. For example, microlenses associated with HSPDs can be associated with a longer focal length than microlenses associated with MSPDs or LSPDs. Similarly, microlenses associated with LSPDs can be associated with a shorter focal length than microlenses associated with MSPDs or HSPDs. Alternatively, as in combination with Figure 4A 、 5A As described in Figures 6A, 7A, and 8A, the photodiode 202 may be a shared microlens. Therefore, a signal separate from the photodiode 202 may be used for PDAF.

[0128] like Figure 9E As further shown in FIG. 4 , an FD node 402 may be provided for each of the photodiodes 202. The FD nodes 402 may each include a drain region, such as a highly doped n-type region (e.g., n +doped regions). The photodiode 202 thus generates a photocurrent that flows from the photodiode 202 to the corresponding FD node 402. Although the exemplary embodiment 900 shows each photodiode 202 having a corresponding FD node 402, other exemplary embodiments may include one or more photodiodes 202 that share a common FD node 402 (e.g., Figure 4A 、 Figure 6A or Figure 7A etc.).

[0129] In addition, a transfer (TX) gate 404 may be provided for each photodiode 202 to control the photocurrent between the photodiode 202 and the FD node 402. The TX gate 404 may be energized (e.g., by applying a voltage or current to the TX gate 404) to form a conductive channel between the photodiode 202 and the corresponding FD node 402. The conductive channel may be removed or closed by de-energizing the TX gate 404, which blocks and / or prevents the flow of photocurrent between the photodiode 202 and the corresponding FD node 402. The TX gate 404 may be included in one or more dielectric layers 910.

[0130] As mentioned above, providing Figures 9A-9E As an example. Other examples may be related to Figures 9A-9E 1. The metal layer 208 may be patterned using multiple layers rather than a single photoresist layer. For example, the multiple layers may include a bottom layer, an intermediate layer, and a photoresist layer. Additionally or alternatively, although exemplary embodiment 900 is described with respect to photolithography, multiple patterning techniques such as sidewall image transfer, pitch splitting, self-aligned double patterning (SADP), or directed self-assembly (DSA) may be used.

[0131] Figure 10 is a flow chart of an example process 1000 associated with the manufacture of pixel sensors and methods. In some examples, a method of Figures 9A-9E One or more semiconductor process tools referenced in Figure 10 Additionally or alternatively, Figure 10 One or more process blocks in the embodiment may be performed using another apparatus or a group of apparatuses separate from or including one or more semiconductor process tools, such as process tools that may be included in a pixel sensor fabrication facility.

[0132] like Figure 10As shown, process 1000 may include forming a metal layer over a plurality of photodiodes in a substrate (block 1010). For example, one or more semiconductor processing tools may be used to form metal layer 208 over a plurality of photodiodes 202 in substrate 206, as described herein.

[0133] like Figure 10 As further shown, the process 1000 may include patterning the metal layer to form a first opening above a first photodiode in the plurality of photodiodes and a second opening above a second photodiode in the plurality of photodiodes, such that the second opening is smaller than the first opening (block 1020). For example, one or more semiconductor process tools may be used to pattern the metal layer 208 to form the first opening 902 above the first photodiode in the plurality of photodiodes 202 and the second opening 906 above the second photodiode in the plurality of photodiodes 202, such that the second opening 906 is smaller than the first opening 902, as described herein.

[0134] like Figure 10 As further shown, process 1000 may include forming a passivation layer in the first opening and the second opening (block 1030 ). For example, one or more semiconductor processing tools may be used to form passivation layer 908 in first opening 902 and second opening 906 , as described herein.

[0135] Process 1000 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0136] In a first implementation, the metal layer 208 is configured to reduce crosstalk between the first photodiode and the second photodiode.

[0137] In a second implementation, either alone or in combination with the first implementation, each opening has a width that is approximately the same as the height of the opening.

[0138] In a third implementation, either alone or in combination with the first implementation, each opening has a width that is longer than the height of the opening.

[0139] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, the process 1000 includes patterning the metal layer 208 to form a third opening 904 over a third photodiode in the plurality of photodiodes 202 , wherein the third opening 904 is larger than the second opening 906 and smaller than the first opening 902 .

[0140] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process 1000 includes forming a first microlens associated with the first photodiode and a second microlens associated with the second photodiode, wherein the second microlens is associated with a shorter focal length than the first microlens.

[0141] In a sixth implementation, alone or in combination with one or more of the first to fifth implementations, process 1000 includes forming a first color filter associated with the first photodiode and a second color filter associated with the second photodiode.

[0142] although Figure 10 illustrative blocks of process 1000 are shown, but in some embodiments, process 1000 may be Figure 10 1000 may include additional blocks, fewer blocks, different blocks, or blocks arranged differently than those shown in 1000. Additionally or alternatively, two or more of the blocks or processes 1000 may be performed in parallel.

[0143] In this way, the metal grid of the pixel array is patterned to form a metal grid with openings of different sizes above the photodiodes, resulting in a uniform pixel array with photodiodes of different sensitivities. For example, the pixel array can include LSPDs, MSPDs, and HSPDs. LSPDs, MSPDs, and HSPDs have different capture rates. Therefore, a higher dynamic range can be achieved by combining the signals of LSPDs, MSPDs, and HSPDs. For example, due to the increased capacitance, the pixel array can achieve a dynamic range of approximately 140 dB or more. In addition, the pixel array exhibits better dark performance than a pixel array combining LPDs and SPDs. Because each photodiode in the pixel array is approximately the same size, photodiode leakage is reduced compared to an irregular pixel array including a combination of LPDs and SPDs.

[0144] In some embodiments, a semiconductor device includes: a first photodiode associated with a first opening in a metal layer; and a second photodiode associated with a second opening in the metal layer, wherein the second opening is smaller than the first opening, and wherein a ratio of a size of the first photodiode to a size of the second photodiode is in a range of approximately 0.9 to approximately 1.1.

[0145] In some embodiments, the ratio of the width of the first opening to the spacing associated with the first photodiode is in a range of about 0.8 to about 1.0. In some embodiments, the ratio of the width of the second opening to the spacing associated with the second photodiode is in a range of about 0.2 to about 0.5. In some embodiments, further comprising: a third photodiode associated with a third opening in the metal layer, wherein the third opening is larger than the second opening and smaller than the first opening. In some embodiments, the ratio of the width of the third opening to the spacing associated with the third photodiode is in a range of about 0.5 to about 0.8. In some embodiments, further comprising: a first microlens associated with the first photodiode; and a second microlens associated with the second photodiode, wherein the second microlens is associated with a shorter focal length than the first microlens. In some embodiments, further comprising: a first color filter associated with the first photodiode; and a second color filter associated with the second photodiode.

[0146] In some embodiments, a method of manufacturing a semiconductor device includes: forming a metal layer above a plurality of photodiodes in a substrate; patterning the metal layer to form a first opening above at least a first photodiode among the plurality of photodiodes and a second opening above a second photodiode among the plurality of photodiodes, wherein the second opening is smaller than the first opening; and forming a passivation layer in the first opening and the second opening.

[0147] In some embodiments, the metal layer is configured to reduce crosstalk between the first photodiode and the second photodiode. In some embodiments, each opening has a width that is approximately the same length as the height of the opening. In some embodiments, each opening has a width that is longer than the height of the opening. In some embodiments, the method further includes: patterning the metal layer to form a third opening above a third photodiode among the plurality of photodiodes, wherein the third opening is larger than the second opening and smaller than the first opening. In some embodiments, the method further includes: forming a first microlens associated with the first photodiode and a second microlens associated with the second photodiode, wherein the second microlens is associated with a shorter focal length than the first microlens. In some embodiments, the method further includes: forming a first color filter associated with the first photodiode and a second color filter associated with the second photodiode.

[0148] In some embodiments, a system for a semiconductor device includes: a pixel sensor, including: a metal layer configured to reflect light; a group of first photodiodes associated with a corresponding group of first openings in the metal layer; a group of second photodiodes, each second photodiode having approximately the same size as each first photodiode, associated with a corresponding group of second openings in the metal layer, each second opening being smaller than each first opening; an isolation structure; and a circuit configured to output electrical signals from the group of first photodiodes and the group of second photodiodes.

[0149] In some embodiments, the system further comprises: a floating diffusion node shared by the group of the first photodiodes and the group of the second photodiodes. In some embodiments, the system further comprises: a first floating diffusion node for the group of the first photodiodes; and a second floating diffusion node for the group of the second photodiodes. In some embodiments, the system further comprises: a lateral overflow integration capacitor associated with the group of the second photodiodes. In some embodiments, the pixel sensor further comprises a group of third photodiodes, each of the third photodiodes having approximately the same size as each of the first photodiodes, associated with a corresponding group of third openings in the metal layer, each of the third openings being larger than each of the second openings and smaller than each of the first openings, and wherein the system further comprises: a floating diffusion node shared by the group of the first photodiodes, the group of the second photodiodes, and the group of the third photodiodes. In some embodiments, the pixel sensor is associated with a dynamic range of at least 140 decibels (dB).

[0150] As used herein, "satisfies a threshold value" may mean, depending on the context, that a value is greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, equal to a threshold value, not equal to a threshold value, etc.

[0151] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that they can readily use the present invention as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a first photodiode associated with the first opening in the metal layer; as well as a second photodiode associated with the second opening in the metal layer, wherein the second opening is smaller than the first opening, and Wherein a ratio of a size of the first photodiode to a size of the second photodiode is in a range of 0.9 to 1.

1.

2. The semiconductor device according to claim 1, wherein A ratio of a width of the first opening to a pitch associated with the first photodiode is in a range of 0.8 to 1.

0.

3. The semiconductor device according to claim 1, wherein A ratio of a width of the second opening to a pitch associated with the second photodiode is in a range of 0.2 to 0.

5.

4. The semiconductor device according to claim 1, wherein Also includes: a third photodiode associated with a third opening in the metal layer, The third opening is larger than the second opening and smaller than the first opening.

5. A system for a semiconductor device, characterized in that include: Pixel sensor, including: a metal layer configured to reflect light; a group of first photodiodes associated with a corresponding group of first openings in the metal layer; a group of second photodiodes, each second photodiode having approximately the same size as each first photodiode, associated with a corresponding group of second openings in the metal layer, each second opening being smaller than each first opening; Isolation structures; and The circuit is configured to output electrical signals from the group of the first photodiodes and the group of the second photodiodes.

6. The system according to claim 5, characterized in that Also includes: The floating diffusion node is shared by the first photodiode group and the second photodiode group.

7. The system according to claim 5, characterized in that Also includes: a first floating diffusion node for the first photodiode group; as well as A second floating diffusion node is provided for the second photodiode group.

8. The system according to claim 5, wherein: Also includes: A lateral overflow integration capacitance is associated with the second photodiode group.

9. The system according to claim 5, characterized in that The pixel sensor further includes a group of third photodiodes, each of the third photodiodes having approximately the same size as each of the first photodiodes, associated with a respective group of third openings in the metal layer, each of the third openings being larger than each of the second openings and smaller than each of the first openings, and wherein the system further includes: The floating diffusion node is shared by the first photodiode group, the second photodiode group, and the third photodiode group.

10. The system according to claim 5, wherein: The pixel sensor is associated with a dynamic range of at least 140 decibels.

Images