Display panel and display device

Abstract

The utility model discloses a display panel and a display device. The display panel comprises a display area, the display area comprises a plurality of pixel circuits arranged in an array mode, the pixel circuits comprise the first pixel circuit, the second pixel circuit and the third pixel circuit, and the first pixel circuit, the second pixel circuit and the third pixel circuit are connected with light-emitting elements of different colors respectively. The display panel further comprises a plurality of data signal lines, the data signal lines comprise the first data signal line, the second data signal line and the third data signal line, the first data signal line is electrically connected with the first pixel circuit, the second data signal line is electrically connected with the second pixel circuit, and the third data signal line is electrically connected with the third pixel circuit. According to the display panel and the display device provided by the embodiment of the utility model, the data signal line is only connected with the sub-pixels emitting the same color light, so that the overall power consumption of the display panel is reduced.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to improve the display effect of the display panel, in the related art, there is a situation where sub-pixels of different colors receive data signals transmitted by the same data signal line. This configuration method increases the power consumption of the display panel. Utility Model Content

[0003] The utility model provides a display panel and a display device, which can reduce the power consumption of the display panel while ensuring the display effect.

[0004] According to one aspect of the present invention, a display panel is provided, comprising a display area, wherein the display area comprises a plurality of pixel circuits arranged in an array, wherein the plurality of pixel circuits comprises a first pixel circuit, a second pixel circuit, and a third pixel circuit;

[0005] The first pixel circuit, the second pixel circuit, and the third pixel circuit are respectively connected to light-emitting elements of different colors;

[0006] The display panel further comprises a plurality of data signal lines, wherein the plurality of data signal lines comprises a first data signal line, a second data signal line and a third data signal line;

[0007] The first data signal line is electrically connected to the first pixel circuit, the second data signal line is electrically connected to the second pixel circuit, and the third data signal line is electrically connected to the third pixel circuit.

[0008] According to another aspect of the present invention, a display device is provided, comprising the display panel described in the first aspect.

[0009] The display panel and display device provided by the embodiments of the present invention set a data signal line connected only to sub-pixels emitting light of the same color, so that one data signal line only needs to transmit the data signal corresponding to sub-pixels of one color, thereby reducing the hopping frequency and hopping amplitude of the data signal on a single data signal line, and further reducing the power consumption of the integrated circuit (IC) providing the data signal, which is beneficial to reducing the overall power consumption of the display panel.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 Schematic diagram of the structure of a display panel in related art;

[0013] Figure 2 for Figure 1 The data signal timing diagram of the data signal line in the display panel shown;

[0014] Figure 3 A schematic structural diagram of a display panel provided by an embodiment of the present utility model;

[0015] Figure 4 A schematic structural diagram of a pixel circuit provided by an embodiment of the present utility model;

[0016] Figure 5 A schematic diagram of a cross-sectional structure of a sub-pixel provided in an embodiment of the present utility model;

[0017] Figure 6 A data signal timing diagram on a data signal line provided by an embodiment of the present utility model;

[0018] Figure 7 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0019] Figure 8 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0020] Figure 9 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0021] Figure 10 A schematic diagram of a partial cross-sectional structure of a display panel provided by an embodiment of the present utility model;

[0022] Figure 11 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0023] Figure 12 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0024] Figure 13 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present utility model;

[0025] Figure 14 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present utility model;

[0026] Figure 15 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0027] Figure 16 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0028] Figure 17 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0029] Figure 18 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0030] Figure 19 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0031] Figure 20 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0032] Figure 21 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0033] Figure 22 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0034] Figure 23 The embodiment of the present invention provides a drive cycle to Figure 4 A signal timing diagram of the pixel circuit shown in ;

[0035] Figure 24 A schematic diagram of a film structure of a display panel provided by an embodiment of the present utility model;

[0036] Figure 25 for Figure 24 A schematic structural diagram of a first semiconductor layer in a display panel shown;

[0037] Figure 26 for Figure 24 A schematic structural diagram of a first metal layer in a display panel shown;

[0038] Figure 27 for Figure 24 A schematic structural diagram of a second metal layer in a display panel shown;

[0039] Figure 28 for Figure 24 A schematic structural diagram of a second semiconductor layer in a display panel shown;

[0040] Figure 29 for Figure 24 A schematic structural diagram of a third metal layer in a display panel shown;

[0041] Figure 30 for Figure 24 A schematic structural diagram of a fourth metal layer in a display panel shown;

[0042] Figure 31 for Figure 24 A schematic structural diagram of a fifth metal layer in a display panel shown;

[0043] Figure 32 for Figure 24 A schematic structural diagram of a sixth metal layer in a display panel shown;

[0044] Figure 33 for Figure 24 A schematic structural diagram of an anode layer in a display panel shown;

[0045] Figure 34 for Figure 24 A schematic diagram of a laminated structure of a partial film layer in a display panel shown;

[0046] Figure 35 for Figure 24 A schematic diagram of a stacked structure of all film layers in a display panel shown;

[0047] Figure 36 for Figure 24 A schematic diagram of a film layer structure of a pixel circuit in a display panel is shown;

[0048] Figure 37 for Figure 24 A schematic diagram of a partial film layer structure of a pixel circuit in a display panel shown;

[0049] Figure 38 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0050] Figure 39 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0051] Figure 40 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0052] Figure 41 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0053] Figure 42 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0054] Figure 43 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0055] Figure 44 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0056] Figure 45 for Figure 24 A schematic diagram of another partial laminate structure of a film layer in a display panel is shown;

[0057] Figure 46 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0058] Figure 47 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0059] Figure 48 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present utility model;

[0060] Figure 49 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present utility model;

[0061] Figure 50 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0062] Figure 51 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0063] Figure 52 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0064] Figure 53 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0065] Figure 54 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0066] Figure 55 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0067] Figure 56 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present utility model;

[0068] Figure 57 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0069] Figure 58 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0070] Figure 59 A schematic structural diagram of another pixel circuit provided by an embodiment of the present utility model;

[0071] Figure 60 The embodiment of the present invention provides a drive cycle to Figure 59 A signal timing diagram of the pixel circuit shown in ;

[0072] Figure 61 A schematic diagram of a film layer structure of another display panel provided by an embodiment of the present utility model;

[0073] Figure 62 for Figure 61 A schematic structural diagram of a first semiconductor layer in a display panel shown;

[0074] Figure 63 for Figure 61 A schematic structural diagram of a first metal layer in a display panel shown;

[0075] Figure 64 for Figure 61 A schematic structural diagram of a second metal layer in a display panel shown;

[0076] Figure 65 for Figure 61 A schematic structural diagram of a fourth metal layer in a display panel shown;

[0077] Figure 66 for Figure 61 A schematic structural diagram of a fifth metal layer in a display panel shown;

[0078] Figure 67 for Figure 61 A schematic structural diagram of a sixth metal layer in a display panel shown;

[0079] Figure 68 for Figure 61 A schematic structural diagram of an anode layer in a display panel shown;

[0080] Figure 69 for Figure 61 A schematic diagram of a stacked structure of all film layers in a display panel shown;

[0081] Figure 70 for Figure 61A schematic diagram of a film layer structure of a pixel circuit in a display panel is shown;

[0082] Figure 71 for Figure 61 A schematic diagram of a partial film layer structure of a pixel circuit in a display panel shown;

[0083] Figure 72 A schematic diagram of a film structure of a pixel circuit provided by an embodiment of the present utility model;

[0084] Figure 73 A schematic diagram of a film layer structure of another pixel circuit provided by an embodiment of the present utility model;

[0085] Figure 74 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0086] Figure 75 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0087] Figure 76 A schematic diagram of a film structure of another pixel circuit provided by an embodiment of the present utility model;

[0088] Figure 77 A schematic structural diagram of another display panel provided by an embodiment of the present utility model;

[0089] Figure 78 A schematic diagram of a film structure of another pixel circuit provided by an embodiment of the present utility model;

[0090] Figure 79 for Figure 24 A schematic diagram of a laminated structure of a partial film layer in a display panel shown;

[0091] Figure 80 for Figure 61 A schematic diagram of a laminated structure of a partial film layer in a display panel shown;

[0092] Figure 81 A schematic diagram of the overlapping relationship between a third power signal line and a green light-emitting element provided in an embodiment of the present utility model;

[0093] Figure 82 A schematic diagram of the overlapping relationship between a first power signal line and a green light-emitting element provided in an embodiment of the present utility model;

[0094] Figure 83 A schematic diagram of the overlapping relationship between another first power signal line and a green light emitting element provided in an embodiment of the present utility model;

[0095] Figure 84A schematic structural diagram of a display device provided in an embodiment of the present utility model. DETAILED DESCRIPTION

[0096] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0097] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0098] Figure 1 This is a schematic diagram of the structure of a display panel in a related technology provided by an embodiment of the present utility model. Figure 2 for Figure 1 The data signal timing diagram of the data signal line in the display panel shown in FIG. Figure 1 and Figure 2 As shown, in order to improve the display effect of the display panel, there is a situation where sub-pixels of different colors are located in the same pixel column. In the related art, sub-pixels of different colors in a sub-pixel column will be connected to the same data signal line and receive the data signal transmitted by the same data signal line, so that sub-pixels of different colors share the same data signal line.

[0099] For example, Figure 1 As shown, the four columns of sub-pixels are respectively connected to four data signal lines, which are S1, S2, S3 and S4 respectively. Among them, the first and third columns of sub-pixel columns include red sub-pixels R and blue sub-pixels B, and the red sub-pixels R and blue sub-pixels B in the first and third columns of sub-pixel columns are connected to the same data signal line.

[0100] Figure 2The timing diagram of the data signal data on the data signal line S1 is shown as an example. Figure 1 and Figure 2 As shown, the inventors have found through research that when the display panel is displaying, the data signal line S1 needs to provide corresponding data signals data to the red sub-pixel R and the blue sub-pixel B respectively. Since the data signals data corresponding to the red sub-pixel R and the blue sub-pixel B are usually different, the data signal data on the data signal line S1 will jump between the data signal data corresponding to the red sub-pixel R and the data signal data corresponding to the blue sub-pixel B.

[0101] For example, taking the display of a red image as an example, when scanning the first row of sub-pixels, the data signal line S1 provides a high-level data signal data to the red sub-pixel R. When scanning the second row of sub-pixels, the data signal line S1 provides a low-level data signal data to the blue sub-pixel B, and so on. In this way, the data signal data on the data signal line S1 jumps between different levels.

[0102] Among them, each jump of the data signal on the data signal line will cause the load capacitance on the data signal line to be charged or discharged, thereby consuming some energy, and then causing the integrated circuit (IC) that provides the data signal to the data signal line to need to provide a large amount of current in a short period of time to charge or discharge the load capacitance on the data signal line, which greatly increases the power consumption of the IC.

[0103] Furthermore, the power consumption power1 added to the IC can satisfy the following formula:

[0104] power1=V dd 2 *C loading *f;

[0105] Among them, V dd is the voltage variation range on the data signal line, C loading is the load capacitance of the data signal line, and f is the frequency of the rising or falling edge of the data signal.

[0106] As can be seen from the above formula, the voltage jump on the data signal line will increase the power consumption of the IC, and the higher the jump frequency and the larger the jump amplitude, the higher the increased power consumption of the IC.

[0107] Based on the above technical issues, Figure 3 A schematic structural diagram of a display panel provided by an embodiment of the present utility model is shown in FIG. Figure 4 A schematic diagram of a pixel circuit structure provided by an embodiment of the present invention is shown in FIG. Figure 3 and Figure 4As shown, the display panel provided by the embodiment of the present invention includes a display area AA, which includes a plurality of pixel circuits 10 arranged in an array. The plurality of pixel circuits 10 include a first pixel circuit 101, a second pixel circuit 102, and a third pixel circuit 103. The first pixel circuit 101, the second pixel circuit 102, and the third pixel circuit 103 are respectively connected to light-emitting elements 20 of different colors. The display panel also includes a plurality of data signal lines 30. The plurality of data signal lines 30 include a first data signal line 301, a second data signal line 302, and a third data signal line 303. The first data signal line 301 is electrically connected to the first pixel circuit 101, the second data signal line 302 is electrically connected to the second pixel circuit 102, and the third data signal line 303 is electrically connected to the third pixel circuit 103.

[0108] Specifically, display area AA is provided with a plurality of pixel circuits 10 arranged in an array and a plurality of light-emitting elements 20 arranged in an array. The plurality of pixel circuits 10 and the plurality of light-emitting elements 20 are electrically connected to each other. The pixel circuits 10 are used to transmit driving current to the light-emitting elements 20 in response to signals from driving signal lines (such as scan signal lines, data signal lines, power signal lines, etc.) on the display panel, thereby driving the light-emitting elements 20 to emit light. The light-emitting elements 20 and the pixel circuits 10 electrically connected thereto together constitute the sub-pixels of the display panel. The multiple sub-pixels are arranged according to a certain pattern. By precisely controlling the brightness of different sub-pixels, a complete image can be displayed.

[0109] It should be noted that the arrangement of the plurality of pixel circuits 10 and the plurality of light emitting elements 20 can be set according to actual needs, and the embodiment of the present invention does not impose any specific limitation on this.

[0110] Figure 5 A schematic diagram of a cross-sectional structure of a sub-pixel provided in an embodiment of the present invention is shown in FIG. Figure 5 As shown, optionally, the pixel circuit 10 may include at least one thin film transistor T, wherein the thin film transistor T may include an active layer 1 , a gate 2 , and a source-drain electrode 3 that are stacked.

[0111] The light-emitting element 20 may include an organic light-emitting diode (OLED), a micro light-emitting diode (such as Micro-LED, Mini-LED) or other types of light-emitting devices, which are not specifically limited in the embodiment of the present invention.

[0112] Continue to refer Figure 5Optionally, taking the light-emitting element 20 as an organic light-emitting diode as an example, the light-emitting element 20 may include a stacked anode 111, a light-emitting layer 112 and a cathode 113. When the pixel circuit 10 provides a driving current to the light-emitting element 20, electrons are injected into the light-emitting layer 112 through the cathode 113, and holes are injected into the light-emitting layer 112 through the anode 111. The electrons and holes recombine in the light-emitting layer 112 to release energy, thereby causing the light-emitting layer 112 to emit visible light.

[0113] By setting the light-emitting layer 112 to be made of different materials, it is possible to emit visible light of different colors.

[0114] For example, the light-emitting element 20 may include a red light-emitting element that emits red light, a blue light-emitting element that emits blue light, and a green light-emitting element that emits green light to achieve color image display, but is not limited to this. In some embodiments, the light-emitting element 20 may also include a white light-emitting element that emits white light, and the embodiments of the present utility model do not specifically limit this.

[0115] Furthermore, the pixel circuit 10 includes a first pixel circuit 101, a second pixel circuit 102 and a third pixel circuit 103, wherein the first pixel circuit 101, the second pixel circuit 102 and the third pixel circuit 103 are respectively connected to light-emitting elements 20 of different colors to form sub-pixels emitting light of different colors.

[0116] Continue to refer Figure 3 and Figure 4 The display panel is further provided with a plurality of data signal lines 30 , and the data signal lines 30 are used to provide data signals to the pixel circuits 10 .

[0117] Continue to refer Figure 4 Exemplarily, the pixel circuit 10 includes a driving transistor T3 for providing a driving current to the light-emitting element 20. The driving transistor T3 and the light-emitting element 20 are connected in series between a first power signal line and a second power signal line. The first power signal line and the second power signal line are both used to transmit a power voltage, and the power voltage on the first power signal line can be greater than the power voltage on the second power signal line. The driving current is generated by the potential difference between the first power signal line and the second power signal line, thereby driving the light-emitting element 20 to emit light.

[0118] Among them, the working process of the pixel circuit 10 can include a data writing stage. In the data writing stage, the data signal line 30 writes a data signal to the gate of the driving transistor T3, and the driving transistor T3 is turned on according to the voltage of the data signal written to its gate. The driving current formed by its conduction is used to drive the light-emitting element 20 to emit light.

[0119] It can be understood that the gate potential of the driving transistor T3 determines the size of the driving current formed by its conduction, and the size of the driving current can determine the brightness of the light-emitting element 20. Therefore, the gate potential of the driving transistor T3 can be controlled by the data signal to adjust the brightness of the light-emitting element 20, thereby controlling the display grayscale of the sub-pixel.

[0120] Furthermore, the data signal lines 30 include a first data signal line 301, a second data signal line 302, and a third data signal line 303. The first data signal line 301 is electrically connected to the first pixel circuit 101, the second data signal line 302 is electrically connected to the second pixel circuit 102, and the third data signal line 303 is electrically connected to the third pixel circuit 103. A data signal line is connected only to the pixel circuits 10 in sub-pixels that emit light of the same color. Therefore, a data signal line only needs to transmit data signals corresponding to sub-pixels of one color. This reduces the hopping frequency and hopping amplitude of the data signal on a single data signal line, thereby reducing the power consumption of the integrated circuit (IC) that provides the data signal, and thus helps reduce the overall power consumption of the display panel.

[0121] For example, Figure 6 This is a data signal timing diagram on a data signal line provided by an embodiment of the present utility model, wherein: Figure 6 The timing diagram of the data signal data on the first data signal line 301 is shown as an example. Figure 6 As shown, taking the first data signal line 301 providing a data signal to the red sub-pixel as an example, when the display panel displays a red image, the first data signal line 301 only needs to provide a high-level data signal data to the red sub-pixel. In this way, the data signal data on the first data signal line 301 only needs to be maintained at the same potential and does not need to jump, thereby reducing the jumping frequency and jumping amplitude of the data signal data on the first data signal line 301, and further reducing the power consumption of the integrated circuit (IC) providing the data signal.

[0122] Similarly, the second data signal line 302 and the third data signal line 303 provide data signals for sub-pixels of other colors except the red sub-pixel. Therefore, when the display panel displays a red image, the second data signal line 302 and the third data signal line 303 only need to provide low-level data signals. In this way, the second data signal line 302 and the third data signal line 303 only need to remain at the same potential and do not need to jump, thereby reducing the jumping frequency and jumping amplitude of the data signals on the second data signal line 302 and the third data signal line 303, and thus reducing the power consumption of the integrated circuit (IC) providing the data signal.

[0123] According to the test results, Table 1 exemplarily shows the reduced power consumption of the integrated circuit (IC) when the display panel displays different images after adopting the solution provided by the embodiment of the utility model.

[0124] Table 1 shows the power consumption reduction of the display panel when displaying different images.

[0125] picture Reduced power consumption (%) White screen 14％ Red screen 37％ Blue screen 43％ Smiley face screen 11％

[0126] As shown in Table 1, by adopting the solution provided by the embodiment of the utility model, the comprehensive power consumption of the integrated circuit (IC) can be reduced by about 25% when the display panel displays different images.

[0127] To sum up, the display panel provided by the embodiment of the present invention sets a data signal line to be connected only to sub-pixels emitting light of the same color, so that one data signal line only needs to transmit the data signal corresponding to sub-pixels of one color, thereby reducing the jump frequency and jump amplitude of the data signal on a single data signal line, and then reducing the power consumption of the integrated circuit (IC) providing the data signal, which is beneficial to reducing the overall power consumption of the display panel.

[0128] Continue to refer Figure 3 Optionally, the plurality of pixel circuits 10 form a plurality of first pixel circuit columns Z1, the first pixel circuit columns Z1 including first pixel circuits 101 and second pixel circuits 102 arranged alternately along the column direction. The plurality of pixel circuits 10 form a plurality of second pixel circuit columns Z2, the second pixel circuit columns Z2 including third pixel circuits 103 arranged along the column direction, and the first pixel circuit columns Z1 and the second pixel circuit columns Z2 are arranged alternately along the row direction. The plurality of data signal lines 30 extend along the column direction and are arranged along the row direction. The first data signal line 301 is electrically connected to the first pixel circuit 101 in the same first pixel circuit column Z1, the second data signal line 302 is electrically connected to the second pixel circuit 102 in the same first pixel circuit column Z1, and the third data signal line 303 is electrically connected to the third pixel circuit 103 in the same second pixel circuit column Z2.

[0129] Specifically, such as Figure 3 As shown, the display area AA is provided with a first pixel circuit column Z1 and a second pixel circuit column Z2 arranged alternately along the row direction. In the first pixel circuit column Z1, the first pixel circuits 101 and the second pixel circuits 102 are arranged alternately in the column direction; in the second pixel circuit column Z2, a plurality of third pixel circuits 103 are arranged sequentially in the column direction.

[0130] With this arrangement, each pixel unit can be composed of two sub-pixels of different colors instead of a complete red sub-pixel, a green sub-pixel, and a blue sub-pixel. For example, adjacent red and green sub-pixels can be combined into one pixel unit, or adjacent blue and green sub-pixels can be combined into one pixel unit. This arrangement allows each pixel unit to contain only two sub-pixels instead of three, allowing more pixel units to be placed in the same area, achieving a higher pixel density, which is beneficial for improving resolution and making the picture display more delicate.

[0131] Further, if Figure 3 As shown, the data signal lines 30 extend along the column direction and are arranged along the row direction. The data signal lines 30 are correspondingly arranged with the pixel circuit columns, wherein each data signal line 30 can be connected to at least part of the pixel circuits in only one pixel circuit column.

[0132] Specifically, such as Figure 3 As shown, the first data signal line 301 is electrically connected to the first pixel circuit 101 in the same first pixel circuit column Z1. Therefore, the first data signal line 301 only needs to provide data signals to the first pixel circuit 101 in the same first pixel circuit column Z1. The second data signal line 302 is electrically connected to the second pixel circuit 102 in the same first pixel circuit column Z1. Therefore, the second data signal line 302 only needs to provide data signals to the second pixel circuit 102 in the same first pixel circuit column Z1. The third data signal line 303 is electrically connected to the third pixel circuit 103 in the same second pixel circuit column Z2. Therefore, the third data signal line 303 only needs to provide data signals to the third pixel circuit 103 in the same second pixel circuit column Z2. This configuration enables a data signal line to transmit data signals corresponding to sub-pixels of only one color, thereby reducing the hopping frequency and hopping amplitude of the data signal on a single data signal line and lowering the power consumption of the integrated circuit (IC) providing the data signal.

[0133] Figure 7 A schematic diagram of another display panel structure provided by an embodiment of the present invention is shown in FIG. Figure 7As shown, optionally, the plurality of first pixel circuit columns Z1 are divided into a plurality of first pixel circuit column groups G1, wherein the first pixel circuit column group G1 includes two first pixel circuit columns Z1, namely a first pixel circuit column Z11 and a second pixel circuit column Z12. The first data signal line 301 connected to the first pixel circuit 101 in the first pixel circuit column Z11 is the first data signal line L1 within the first group, the second data signal line 302 connected to the second pixel circuit 102 in the first pixel circuit column Z11 is the second data signal line L2 within the second group, the first data signal line 301 connected to the first pixel circuit 101 in the second pixel circuit column Z12 is the third data signal line L3 within the second group, and the second data signal line 302 connected to the second pixel circuit 102 in the second pixel circuit column Z12 is the fourth data signal line L4 within the second group. In the first pixel circuit column group G1, the data signal line L1 within the first group is electrically connected to the data signal line L3 within the third group, and the data signal line L2 within the second group is electrically connected to the data signal line L4 within the fourth group. The first pixel circuit 101 connected to the data signal line L1 within the first group and the first pixel circuit 101 connected to the data signal line L3 within the third group are located in different pixel circuit rows, and the second pixel circuit 102 connected to the data signal line L2 within the second group and the second pixel circuit 102 connected to the data signal line L4 within the fourth group are located in different pixel circuit rows.

[0134] Specifically, such as Figure 7 As shown, in the display area AA, multiple first pixel circuit column groups G1 are arranged along the row direction, wherein the first pixel circuit column group G1 includes a first-group pixel circuit column Z11 and a second-group pixel circuit column Z12, the first-group pixel circuit column Z11 includes a first pixel circuit 101 and a second pixel circuit 102 alternately arranged along the column direction, and the second-group pixel circuit column Z12 includes a first pixel circuit 101 and a second pixel circuit 102 alternately arranged along the column direction.

[0135] In this embodiment, the first pixel circuits 101 in the first group pixel circuit column Z11 are all connected to the first group data signal line L1, and the first pixel circuits 101 in the second group pixel circuit column Z12 are connected to the third group data signal line L3, wherein the first group data signal line L1 and the third group data signal line L3 in the first pixel circuit column group G1 are electrically connected. With such an arrangement, the data signals on the first group data signal line L1 and the third group data signal line L3 can be provided by the same pin of the IC, thereby ensuring that one data signal line only transmits the data signal corresponding to one color sub-pixel while reducing the number of pins providing data signals in the IC, which is beneficial to reducing the size and cost of the IC.

[0136] Furthermore, the first pixel circuit 101 connected to the data signal line L1 in the first group and the first pixel circuit 101 connected to the data signal line L3 in the third group are located in different pixel circuit rows, so as to avoid the situation where the same pin of the IC provides data signals to two first pixel circuits 101 located in different pixel circuit columns at the same time when scanning a certain row of pixel circuits. Therefore, when scanning any row of pixel circuits, each IC pin only provides a data signal to one first pixel circuit 101, ensuring that in one frame of display image, the brightness of the sub-pixel corresponding to each first pixel circuit 101 can be independently controlled, thereby ensuring the display quality of the display panel.

[0137] Continue to refer Figure 7 The second pixel circuits 102 in the first group of pixel circuit columns Z11 are all connected to the second group of data signal lines L2, and the second pixel circuits 102 in the second group of pixel circuit columns Z12 are all connected to the fourth group of data signal lines L4, wherein the second group of data signal lines L2 and the fourth group of data signal lines L4 in the first pixel circuit column group G1 are electrically connected. With this arrangement, the data signals on the second group of data signal lines L2 and the fourth group of data signal lines L4 can be provided by the same pin of the IC, thereby ensuring that one data signal line only transmits the data signal corresponding to one color sub-pixel while reducing the number of pins providing data signals in the IC, which is beneficial to reducing the size and cost of the IC.

[0138] Furthermore, the second pixel circuit 102 connected to the data signal line L2 in the second group and the second pixel circuit 102 connected to the data signal line L4 in the fourth group are located in different pixel circuit rows, so as to avoid the situation where the same pin of the IC simultaneously provides data signals to two second pixel circuits 102 located in different pixel circuit columns when scanning a certain row of pixel circuits. Therefore, when scanning any row of pixel circuits, each IC pin only provides a data signal to one second pixel circuit 102, ensuring that in one frame of display image, the brightness of the sub-pixel corresponding to each second pixel circuit 102 can be independently controlled, thereby ensuring the display quality of the display panel.

[0139] Continue to refer Figure 7 Optionally, the first pixel circuits 101 and the second pixel circuits 102 are alternately arranged along the row direction, and the first pixel circuit column group G1 includes two adjacent first pixel circuit columns Z1.

[0140] Specifically, such as Figure 7As shown, in the row direction, the first pixel circuit 101 and the second pixel circuit 102 are arranged alternately, and a third pixel circuit 103 is provided between the first pixel circuit 101 and the second pixel circuit 102. Such an arrangement can make the arrangement of the first pixel circuit 101 and the second pixel circuit 102 more dispersed, so that the display panel is less likely to produce local bright lines, which is beneficial to improving the display uniformity of the display panel.

[0141] Continue to refer Figure 7 Optionally, the display panel provided by the embodiment of the present invention further includes a non-display area NAA located on at least one side of the display area AA. In the first pixel circuit column group G1, the data signal line L1 in the first group and the data signal line L3 in the third group are electrically connected through the first data connection line L13, and the data signal line L2 in the second group and the data signal line L4 in the fourth group are electrically connected through the second data connection line L24. The first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA.

[0142] Specifically, such as Figure 7 As shown, the non-display area NAA may be a lower frame area located on one side of the display area AA along the column direction, but is not limited thereto. The embodiment of the present invention does not specifically limit the positional relationship between the display area AA and the non-display area NAA.

[0143] In this embodiment, if Figure 7 As shown, by providing a first data connection line L13 extending in the row direction, the first data signal line L1 within the first pixel circuit column group G1 and the third data signal line L3 within the first pixel circuit column group G1 are electrically connected via the first data connection line L13. Furthermore, by providing a second data connection line L24 extending in the row direction, the second data signal line L2 within the first pixel circuit column group G1 and the fourth data signal line L4 within the first pixel circuit column group G1 are electrically connected via the second data connection line L24.

[0144] Among them, the first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA, which can avoid the first data connection line L13 and the second data connection line L24 from blocking the display area AA, thereby reducing the impact of the first data connection line L13 and the second data connection line L24 on the display effect.

[0145] Figure 8 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 8As shown, optionally, in the first pixel circuit column group G1, the data signal line L1 in the first group and the data signal line L3 in the third group are electrically connected through the first data connection line L13, and the data signal line L2 in the second group and the data signal line L4 in the fourth group are electrically connected through the second data connection line L24, and the first data connection line L13 and the second data connection line L24 are both located in the display area AA.

[0146] Specifically, such as Figure 8 As shown, by providing a first data connection line L13 extending in the row direction, the first data signal line L1 within the first pixel circuit column group G1 and the third data signal line L3 within the first pixel circuit column group G1 are electrically connected via the first data connection line L13. Furthermore, by providing a second data connection line L24 extending in the row direction, the second data signal line L2 within the first pixel circuit column group G1 and the fourth data signal line L4 within the first pixel circuit column group G1 are electrically connected via the second data connection line L24.

[0147] Among them, the first data connection line L13 and the second data connection line L24 are both located in the display area AA, which is different from the solution of setting the first data connection line L13 and the second data connection line L24 in the non-display area NAA. It can reduce the number of wirings in the non-display area NAA, thereby helping to reduce the area used for wiring in the non-display area NAA and realize a narrow bezel design.

[0148] Continue to refer Figure 8 Optionally, the first data connection line L13 and the second data connection line L24 are located between adjacent rows of pixel circuits 10 in the display area AA, which can avoid the formation of parasitic capacitance between the first data connection line L13 and the second data connection line L24 and each metal film layer in the pixel circuit 10, thereby reducing the impact of the first data connection line L13 and the second data connection line L24 on the performance of the pixel circuit 10, but is not limited to this.

[0149] In other embodiments, along a direction perpendicular to the plane of the display panel, the first data connection line L13 and the second data connection line L24 may also at least partially overlap with the pixel circuit 10, so that the first data connection line L13 and the second data connection line L24 do not need to occupy additional space, which is beneficial to improving the pixel density of the display panel. The embodiments of the present invention do not specifically limit this.

[0150] Figure 9 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 9As shown, optionally, the display panel provided by the embodiment of the present invention further includes a plurality of data signal output lines 40 and a plurality of gating circuits 50. The data signal output lines 40 include a first data signal output line 401 and a second data signal output line 402. The gating circuit 50 includes a first gating circuit 501 and a second gating circuit 502. In the first pixel circuit column group G1, the first group data signal line L1 and the third group data signal line L3 are electrically connected to the same first data signal output line 401 via the first gating circuit 501. The first gating circuit 501 is used to transmit the data signal output by the first data signal output line 401 to the first group data signal line L1 and the third group data signal line L3 in time-sharing. In the first pixel circuit column group G1, the data signal line L2 in the second group and the data signal line L4 in the fourth group are electrically connected to the same second data signal output line 402 through the second selection circuit 502. The second selection circuit 502 is used to transmit the data signal output by the second data signal output line 402 to the data signal line L2 in the second group and the data signal line L4 in the fourth group in a time-sharing manner.

[0151] Among them, such as Figure 7 and Figure 9 As shown, a plurality of data signal output lines 40 are provided on the display panel. The data signal output lines 40 are electrically connected to the pins of the integrated circuit IC and the data signal lines 30 respectively. The integrated circuit IC provides data signals to the data signal lines 30 through the data signal output lines 40 .

[0152] Specifically, such as Figure 7 and Figure 9 As shown, the data signal output lines 40 include a first data signal output line 401 and a second data signal output line 402. In the first pixel circuit column group G1, the first group data signal line L1 and the third group data signal line L3 are both electrically connected to the same first data signal output line 401. In this case, the first data signal output line 401 simultaneously provides data signals to the first group data signal line L1 and the third group data signal line L3. Similarly, in the first pixel circuit column group G1, the second group data signal line L2 and the fourth group data signal line L4 are both electrically connected to the same second data signal output line 402. In this case, the second data signal output line 402 simultaneously provides data signals to the second group data signal line L2 and the fourth group data signal line L4.

[0153] Continue to refer Figure 7A data signal output line 40 needs to provide data signals to two data signal lines 30 at the same time. Each data signal line 30 is connected to a certain number of pixel circuits 10, and each pixel circuit 10 has its own parasitic capacitance. Therefore, when a data signal output line 40 provides data signals to two data signal lines 30 at the same time, the capacitive load on the integrated circuit IC pin includes the parasitic capacitance of the pixel circuits 10 connected to the two data signal lines 30, which will cause a large capacitive load problem. The larger the capacitive load, the more energy required for charging and discharging, and the higher the power consumption.

[0154] Based on the above technical problems, in this embodiment, if Figure 9 As shown, a plurality of gating circuits 50 are further provided on the display panel. The gating circuits 50 are used to transmit the data signal from the data signal output line 40 to different data signal lines 30 in a time-sharing manner, so that at the same time point, the gating circuit 50 will selectively transmit the data signal to one data signal line 30, ensuring that the pin of each integrated circuit IC only provides a data signal to one data signal line 30 at any time, thereby effectively reducing the capacitive load on the pin of the integrated circuit IC and thereby reducing power consumption.

[0155] Specifically, such as Figure 9 As shown, the gating circuit 50 includes a first gating circuit 501 and a second gating circuit 502. In the first pixel circuit column group G1, the data signal line L1 in the first group and the data signal line L3 in the third group are electrically connected to the same first data signal output line 401 through the first gating circuit 501, so that the data signal output by the first data signal output line 401 is transmitted to the data signal line L1 in the first group and the data signal line L3 in the third group through the first gating circuit 501 in a time-sharing manner, ensuring that the integrated circuit IC pin connected to the first data signal output line 401 only provides a data signal to the data signal line L1 in the first group or the data signal line L3 in the third group at any time, thereby reducing the capacitive load on the integrated circuit IC pin and further reducing power consumption.

[0156] Similarly, in the first pixel circuit column group G1, the data signal line L2 in the second group and the data signal line L4 in the fourth group are electrically connected to the same second data signal output line 402 through the second selection circuit 502, so that the data signal output by the second data signal output line 402 is transmitted to the data signal line L2 in the second group and the data signal line L4 in the fourth group through the second selection circuit 502 in a time-sharing manner, ensuring that the integrated circuit IC pin connected to the second data signal output line 402 only provides a data signal to the data signal line L2 in the second group or the data signal line L4 in the fourth group at any time, thereby reducing the capacitive load on the integrated circuit IC pin and further reducing power consumption.

[0157] According to the test results, after adopting the solution provided by the embodiment of the utility model, the power consumption of the integrated circuit IC can be reduced by 10% when the display panel displays a white picture, and the power consumption of the integrated circuit IC can be reduced by about 40% when the display panel displays a red or blue picture.

[0158] Continue to refer Figure 9 Optionally, the data signal output line 40, the gating circuit 50 and the integrated circuit IC are all located in the non-display area NAA, which can avoid the data signal output line 40, the gating circuit 50 and the integrated circuit IC from blocking the display area AA, thereby reducing the impact of the data signal output line 40, the gating circuit 50 and the integrated circuit IC on the display effect.

[0159] In other embodiments, the integrated circuit IC may also be disposed on a flexible circuit board bound and connected to the display panel, which is beneficial for reducing the area of ​​the non-display area NAA and achieving a narrow frame design. The embodiments of the present utility model do not specifically limit this.

[0160] Continue to refer Figure 9 Optionally, the data signal output line 40 extends in the column direction and is arranged in the row direction, which facilitates the electrical connection between the data signal output line 40 and the pin of the integrated circuit IC and the data signal line 30 while avoiding short circuits between different data signal output lines 40, but is not limited to this. The embodiments of the present utility model do not make specific limitations on this.

[0161] Continue to refer Figure 9 Optionally, the first gating circuit 501 includes a first switching transistor M1 and a second switching transistor M2. The first switching transistor M1 is connected between the data signal line L1 within the first group and the first data signal output line 401, and the second switching transistor M2 is connected between the data signal line L3 within the third group and the first data signal output line 401. The second gating circuit 502 includes a third switching transistor M3 and a fourth switching transistor M4. The third switching transistor M3 is connected between the data signal line L2 within the second group and the second data signal output line 402, and the fourth switching transistor M4 is connected between the data signal line L4 within the fourth group and the second data signal output line 402. The gates of the first switching transistor M1 and the fourth switching transistor M4 receive a first switching signal SW1, and the gates of the second switching transistor and the third switching transistor M3 receive a second switching signal SW2.

[0162] Specifically, such as Figure 9As shown, the first selection circuit 501 is composed of a first switching transistor M1 and a second switching transistor M2, wherein one end of the first switching transistor M1 is connected to the data signal line L1 in the first group, and the other end is connected to the first data signal output line 401; one end of the second switching transistor M2 is connected to the data signal line L3 in the third group, and the other end is connected to the first data signal output line 401.

[0163] Furthermore, the gate of the first switching transistor M1 receives a first switching signal SW1, and the first switching signal SW1 is used to control the first switching transistor M1 to be turned on or off. When the first switching transistor M1 is turned on, the data signal line L1 in the first group and the first data signal output line 401 are connected. At this time, the first data signal output line 401 provides a data signal to the data signal line L1 in the first group; when the first switching transistor M1 is turned off, the data signal line L1 in the first group and the first data signal output line 401 are insulated.

[0164] The gate of the second switching transistor M2 receives a second switching signal SW2, and the second switching signal SW2 is used to control the second switching transistor M2 to be turned on or off. When the second switching transistor M2 is turned on, the data signal line L3 in the third group and the first data signal output line 401 are connected. At this time, the first data signal output line 401 provides a data signal to the data signal line L3 in the third group; when the second switching transistor M2 is turned off, the data signal line L3 in the third group and the first data signal output line 401 are insulated.

[0165] Among them, the gate of the first switching transistor M1 and the gate of the second switching transistor M2 receive different first switching signals SW1 and second switching signals SW2, so that the first switching transistor M1 and the second switching transistor M2 are turned on in a time-sharing manner, thereby realizing the time-sharing transmission of the data signal output by the first data signal output line 401 to the data signal line L1 in the first group and the data signal line L3 in the third group, ensuring that the integrated circuit IC pin connected to the first data signal output line 401 only provides data signals to the data signal line L1 in the first group or the data signal line L3 in the third group at any time, thereby reducing the capacitive load on the integrated circuit IC pin and reducing power consumption.

[0166] Similarly, continue to refer to Figure 9 The second selection circuit 502 is composed of a third switching transistor M3 and a fourth switching transistor M4, wherein one end of the third switching transistor M3 is connected to the data signal line L2 in the second group, and the other end is connected to the second data signal output line 402; one end of the fourth switching transistor M4 is connected to the data signal line L4 in the fourth group, and the other end is connected to the second data signal output line 402.

[0167] The gate of the third switching transistor M3 receives the second switching signal SW2, and the second switching signal SW2 is used to control the third switching transistor M3 to be turned on or off. When the third switching transistor M3 is turned on, the data signal line L2 in the second group is connected to the second data signal output line 402. At this time, the second data signal output line 402 provides a data signal to the data signal line L2 in the second group; when the third switching transistor M3 is turned off, the data signal line L2 in the second group and the second data signal output line 402 are insulated.

[0168] The gate of the fourth switching transistor M4 receives the first switching signal SW1, and the first switching signal SW1 is used to control the fourth switching transistor M4 to be turned on or off. When the fourth switching transistor M4 is turned on, the data signal line L4 in the fourth group and the second data signal output line 402 are connected. At this time, the second data signal output line 402 provides a data signal to the data signal line L4 in the fourth group; when the fourth switching transistor M4 is turned off, the data signal line L4 in the fourth group and the second data signal output line 402 are insulated.

[0169] Among them, the gate of the third switching transistor M3 and the gate of the fourth switching transistor M4 receive different second switching signals SW2 and first switching signals SW1, so that the third switching transistor M3 and the fourth switching transistor M4 are turned on in a time-sharing manner, thereby realizing the time-sharing transmission of the data signal output by the second data signal output line 402 to the second-group data signal line L2 and the fourth-group data signal line L4, ensuring that the integrated circuit IC pin connected to the second data signal output line 402 only provides the data signal to the second-group data signal line L2 or the fourth-group data signal line L4 at any time, thereby reducing the capacitive load on the integrated circuit IC pin and reducing power consumption.

[0170] Further, if Figure 9 As shown, the first pixel circuit 101 connected to the data signal line L1 in the first group and the second pixel circuit 102 connected to the data signal line L4 in the fourth group are located in the same pixel circuit row. Therefore, the gate of the first switching transistor M1 and the gate of the fourth switching transistor M4 can be set to receive the first switching signal SW1, so that the first switching transistor M1 and the fourth switching transistor M4 are turned on at the same time, ensuring that the first pixel circuit 101 and the second pixel circuit 102 located in the same row receive the data signal at the same time. Such a setting can reduce the number of switching signals, simplify the control logic, and help reduce the number of switching signal lines that transmit switching signals, thereby reducing costs.

[0171] Similarly, the second pixel circuit 102 connected to the data signal line L2 in the second group and the first pixel circuit 101 connected to the data signal line L3 in the third group are located in the same pixel circuit row. Therefore, the gate of the second switching transistor M2 and the gate of the third switching transistor M3 can be set to receive the second switching signal SW2, so that the second switching transistor M2 and the third switching transistor M3 are turned on at the same time, ensuring that the first pixel circuit 101 and the second pixel circuit 102 located in the same row receive the data signal at the same time. Such a setting can reduce the number of switching signals, simplify the control logic, and help reduce the number of switching signal lines that transmit switching signals, thereby reducing costs.

[0172] Continue to refer Figure 7-Figure 9 Optionally, the plurality of first pixel circuit columns Z1 are divided into a plurality of first pixel circuit column groups G1, wherein the first pixel circuit column group G1 includes two adjacent first pixel circuit columns Z1, namely a first pixel circuit column Z11 and a second pixel circuit column Z12. The first data signal line 301 connected to the first pixel circuit 101 in the first pixel circuit column Z11 is the first data signal line L1 within the group, the second data signal line 302 connected to the second pixel circuit 102 in the first pixel circuit column Z11 is the second data signal line L2 within the group, the first data signal line 301 connected to the first pixel circuit 101 in the second pixel circuit column Z12 is the third data signal line L3 within the group, and the second data signal line 302 connected to the second pixel circuit 102 in the second pixel circuit column Z12 is the fourth data signal line L4 within the group. In the row direction, the first group data signal line L1 and the second group data signal line L2 are located on different sides of the first group pixel circuit column Z11, and the third group data signal line L3 and the fourth group data signal line L4 are located on different sides of the second group pixel circuit column Z12.

[0173] Among them, the structure of the first group pixel circuit column Z11 and the second group pixel circuit column Z12 in the first pixel circuit column group G1, as well as the connection structure of the first group data signal line L1, the second group data signal line L2, the third group data signal line L3 and the fourth group data signal line L4 can refer to the above embodiments and will not be repeated here.

[0174] In this embodiment, if Figure 7-Figure 9As shown, along the row direction, the first-group data signal line L1 and the second-group data signal line L2 are respectively located on different sides of the first-group pixel circuit column Z11. On the one hand, in the row direction, the first-group data signal line L1 and the second-group data signal line L2 are each spaced a certain distance from the first-group pixel circuit column Z11. This can prevent parasitic capacitance from forming between the first-group data signal line L1 and the second-group data signal line L2 and the various metal film layers of the pixel circuits 10 in the first-group pixel circuit column Z11, thereby reducing the impact of the first-group data signal line L1 and the second-group data signal line L2 on the performance of the pixel circuits 10. On the other hand, in the row direction, a larger distance can be provided between the first-group data signal line L1 and the second-group data signal line L2, thereby reducing mutual interference of data signals between the first-group data signal line L1 and the second-group data signal line L2.

[0175] Similarly, along the row direction, the third and fourth data signal lines L3 and L4 are located on different sides of the second pixel circuit column Z12. On the one hand, along the row direction, the third and fourth data signal lines L3 and L4 are spaced a certain distance from the second pixel circuit column Z12. This prevents parasitic capacitance from forming between the third and fourth data signal lines L3 and L4 and the metal film layers of the pixel circuits 10 in the second pixel circuit column Z12, thereby reducing the impact of the third and fourth data signal lines L3 and L4 on the performance of the pixel circuits 10. On the other hand, along the row direction, a larger distance can be provided between the third and fourth data signal lines L3 and L4, thereby reducing mutual interference of data signals between the third and fourth data signal lines L3 and L4.

[0176] Continue to refer Figure 7-Figure 9Optionally, the plurality of first pixel circuit columns Z1 are divided into a plurality of first pixel circuit column groups G1, wherein the first pixel circuit column group G1 includes two adjacent first pixel circuit columns Z1, namely a first pixel circuit column Z11 and a second pixel circuit column Z12. The first data signal line 301 connected to the first pixel circuit 101 in the first pixel circuit column Z11 is the first data signal line L1 within the group, the second data signal line 302 connected to the second pixel circuit 102 in the first pixel circuit column Z11 is the second data signal line L2 within the group, the first data signal line 301 connected to the first pixel circuit 101 in the second pixel circuit column Z12 is the third data signal line L3 within the group, and the second data signal line 302 connected to the second pixel circuit 102 in the second pixel circuit column Z12 is the fourth data signal line L4 within the group. In the first pixel circuit column group G1 , the second intra-group data signal line L2 and the fourth intra-group data signal line L4 are located between the first intra-group data signal line L1 and the third intra-group data signal line L3 .

[0177] Among them, the structure of the first group pixel circuit column Z11 and the second group pixel circuit column Z12 in the first pixel circuit column group G1, as well as the connection structure of the first group data signal line L1, the second group data signal line L2, the third group data signal line L3 and the fourth group data signal line L4 can refer to the above embodiments and will not be repeated here.

[0178] In this embodiment, if Figure 7-Figure 9 As shown, the data signal line L1 in the first group and the data signal line L3 in the third group are both connected to the first pixel circuit 101, and the first pixel circuits 101 are all located in sub-pixels of the same color; the data signal line L2 in the second group and the data signal line L4 in the fourth group are both connected to the second pixel circuit 102, and the second pixel circuits 102 are all located in sub-pixels of the same color.

[0179] In the first pixel circuit column group G1, the second group of data signal lines L2 and the fourth group of data signal lines L4 are disposed between the first group of data signal lines L1 and the third group of data signal lines L3. Thus, along the row direction, the first group of data signal lines L1, the second group of data signal lines L2, the fourth group of data signal lines L4, and the third group of data signal lines L3 may be arranged sequentially. With this arrangement, the second group of data signal lines L2 and the fourth group of data signal lines L4 may be symmetrically distributed relative to the central axis of the first pixel circuit column group G1, and the first group of data signal lines L1 and the third group of data signal lines L3 may also be symmetrically distributed relative to the central axis of the first pixel circuit column group G1. That is, the data signal lines 30 connecting sub-pixels of the same color may be symmetrically distributed relative to the central axis of the first pixel circuit column group G1. This facilitates more symmetrical color shift of the displayed image, thereby improving four-way color shift. That is, regardless of the direction from which the displayed image is viewed, color consistency and accuracy are improved. Furthermore, the displayed image can be viewed from a wider range of angles without noticeable color shift, thereby enhancing the user experience.

[0180] It should be noted that the central axis of the first pixel circuit column group G1 is a central axis extending along the column direction.

[0181] Continue to refer Figure 7 Optionally, the display panel provided by the embodiment of the present invention further includes a non-display area NAA located on at least one side of the display area AA. In the first pixel circuit column group G1, the data signal line L1 within the first group and the data signal line L3 within the third group are electrically connected via a first data connection line L13, and the data signal line L2 within the second group and the data signal line L4 within the fourth group are electrically connected via a second data connection line L24. The first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA, and the second data connection line L24 is located on a side of the first data connection line L13 that is closer to the display area AA.

[0182] Among them, the positional relationship between the display area AA and the non-display area NAA, the connection relationship between the data signal line L1 in the first group, the data signal line L2 in the second group, the data signal line L3 in the third group, the data signal line L4 in the fourth group, the first data connection line L13 and the second data connection line L24 can be referred to the above embodiments and will not be repeated here.

[0183] In this embodiment, if Figure 7 As shown, the first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA, which can prevent the first data connection line L13 and the second data connection line L24 from blocking the display area AA, thereby reducing the impact of the first data connection line L13 and the second data connection line L24 on the display effect.

[0184] Further, if Figure 7 As shown, the second data connection line L24 is located on the side of the first data connection line L13 close to the display area AA. Such an arrangement can avoid overlapping of the first data connection line L13 and the data signal lines L2 in the second group and the data signal lines L4 in the fourth group in a direction perpendicular to the plane where the display panel is located, thereby reducing the coupling capacitance between the first data connection line L13, the data signal lines L2 in the second group and the data signal lines L4 in the fourth group, and reducing the mutual interference between the data signal on the first data connection line L13 and the data signals on the data signal lines L2 in the second group and the data signal lines L4 in the fourth group.

[0185] Figure 10 A partial cross-sectional structural diagram of a display panel provided by an embodiment of the present utility model is shown in FIG. Figure 7 and Figure 10 As shown, the display panel provided in this embodiment of the present invention optionally further includes a plurality of data signal output lines 40. The data signal output lines 40 include a first data signal output line 401 and a second data signal output line 402. In the first pixel circuit column group G1, the first data connection line L13 is electrically connected to the first data signal output line 401, and the second data connection line L24 is electrically connected to the second data signal output line 402. The first data connection line L13 and the second data signal output line 402 are located in different film layers.

[0186] The structure of the data signal output line 40 and the connection relationship between the first data signal output line 401 and the second data signal output line 402 may refer to the above embodiment and will not be described in detail here.

[0187] In this embodiment, if Figure 7 and Figure 10 As shown, in the direction perpendicular to the plane where the display panel is located, there is an overlap between the first data connection line L13 and the second data signal output line 402. Therefore, by arranging the first data connection line L13 and the second data signal output line 402 in different film layers, a short circuit between the first data connection line L13 and the second data signal output line 402 can be avoided.

[0188] For example, Figure 5 and Figure 10 As shown, the pixel circuit 10 and the light-emitting element 20 can be arranged on one side of the base substrate 60, wherein the pixel circuit 10 also includes a storage capacitor Cst, and the storage capacitor Cst includes a first electrode plate C1 and a second electrode plate C2 that are stacked, and the first electrode plate C1 is located on the side of the second electrode plate C2 close to the base substrate 60.

[0189] like Figure 10As shown, the second data signal output line 402 can be located in the same film layer as the first electrode C1 and / or the second electrode C2, the data signal line 30 can be located in the same film layer as the source and drain electrode 3, and the first data connection line L13 can be located in the same film layer as the data signal line 30, but is not limited to this.

[0190] It can be understood that, under the condition of ensuring that the first data connection line L13 and the second data signal output line 402 are located in different film layers, the first data connection line L13 can be selected to be set in the same layer as the existing metal film layer structure in the pixel circuit 10, thereby reducing the number of metal layers set, which is beneficial to reducing the thickness of the display panel; at the same time, the first data connection line L13 can also be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, thereby shortening the process time and reducing manufacturing costs.

[0191] Figure 11 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 11 As shown, optionally, the plurality of first pixel circuit columns Z1 are divided into a plurality of first pixel circuit column groups G1, wherein the first pixel circuit column group G1 includes two first pixel circuit columns Z1, namely a first pixel circuit column Z11 and a second pixel circuit column Z12. The first data signal line 301 connected to the first pixel circuit 101 in the first pixel circuit column Z11 is the first data signal line L1 within the first group, the second data signal line 302 connected to the second pixel circuit 102 in the first pixel circuit column Z11 is the second data signal line L2 within the second group, the first data signal line 301 connected to the first pixel circuit 101 in the second pixel circuit column Z12 is the third data signal line L3 within the second group, and the second data signal line 302 connected to the second pixel circuit 102 in the second pixel circuit column Z12 is the fourth data signal line L4 within the second group. In the first pixel circuit column group G1 , the first group data signal line L1 , the second group data signal line L2 , the third group data signal line L3 , and the fourth group data signal line L4 are sequentially arranged along the row direction.

[0192] Among them, the structure of the first group pixel circuit column Z11 and the second group pixel circuit column Z12 in the first pixel circuit column group G1, as well as the connection structure of the first group data signal line L1, the second group data signal line L2, the third group data signal line L3 and the fourth group data signal line L4 can refer to the above embodiments and will not be repeated here.

[0193] In this embodiment, if Figure 11As shown, the data signal line L1 in the first group and the data signal line L3 in the third group are both connected to the first pixel circuit 101, and the first pixel circuits 101 are all located in sub-pixels of the same color; the data signal line L2 in the second group and the data signal line L4 in the fourth group are both connected to the second pixel circuit 102, and the second pixel circuits 102 are all located in sub-pixels of the same color.

[0194] Among them, such as Figure 11 As shown, in the first pixel circuit column group G1, the data signal line L1 in the first group, the data signal line L2 in the second group, the data signal line L3 in the third group and the data signal line L4 in the fourth group are arranged in sequence along the row direction. Then, along the row direction, the data signal line L1 in the first group is located on the left side of the pixel circuit column Z11 in the first group, and the data signal line L3 in the third group is located on the left side of the pixel circuit column Z12 in the second group; the data signal line L2 in the second group is located on the right side of the pixel circuit column Z11 in the first group, and the data signal line L4 in the fourth group is located on the right side of the pixel circuit column Z12 in the second group, that is, the data signal lines 30 connecting sub-pixels of the same color are located on the same side of the first pixel circuit column Z1 to which they are connected. On the other hand, such an arrangement can make the positional relationship between the data signal line 30 connecting the sub-pixels of the same color and the first pixel circuit column Z1 connected thereto more consistent. At this time, the parasitic capacitances between the data signal line 30 connecting the sub-pixels of the same color and the metal film layers or signal nodes in the first pixel circuit column Z1 connected thereto are at similar levels. In the process of preparing the display panel, even if there are process fluctuations, the overlapping deviations between the data signal line 30 connecting the sub-pixels of the same color and the metal film layers or signal nodes in the first pixel circuit column Z1 connected thereto also have the same trend change, thereby improving the display uniformity of the display panel and avoiding the vertical stripe phenomenon caused by brightness differences.

[0195] Continue to refer Figure 11 Optionally, the display panel provided by the embodiment of the present invention further includes a non-display area NAA located on at least one side of the display area AA. In the first pixel circuit column group G1, the data signal lines L1 within the first group and the data signal lines L3 within the third group are electrically connected via a first data connection line L13, and the data signal lines L2 within the second group and the data signal lines L4 within the fourth group are electrically connected via a second data connection line L24. Both the first data connection line L13 and the second data connection line L24 are located in the non-display area NAA.

[0196] The second data connection line L24 is located on a side of the first data connection line L13 close to the display area AA. The second data connection line L24 and the data signal line L3 in the third group are located in different film layers.

[0197] or,

[0198] The first data connection line L13 is located on a side of the second data connection line L24 close to the display area AA. The first data connection line L13 and the second group of data signal lines L2 are located in different film layers.

[0199] Among them, the positional relationship between the display area AA and the non-display area NAA, the connection relationship between the data signal line L1 in the first group, the data signal line L2 in the second group, the data signal line L3 in the third group, the data signal line L4 in the fourth group, the first data connection line L13 and the second data connection line L24 can be referred to the above embodiments and will not be repeated here.

[0200] In this embodiment, if Figure 11 As shown, the first data connection line L13 and the second data connection line L24 are both located in the non-display area NAA, which can prevent the first data connection line L13 and the second data connection line L24 from blocking the display area AA, thereby reducing the impact of the first data connection line L13 and the second data connection line L24 on the display effect.

[0201] Further, if Figure 11 As shown, the second data connection line L24 can be located on the side of the first data connection line L13 that is closer to the display area AA. In this case, the second data connection line L24 and the data signal line L3 in the third group overlap in a direction perpendicular to the plane of the display panel. Therefore, in this embodiment, by arranging the second data connection line L24 and the data signal line L3 in the third group in different film layers, a short circuit between the first data connection line L13 and the second data signal output line 402 is avoided.

[0202] Figure 12 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 12 As shown, optionally, the first data connection line L13 is located on the side of the second data connection line L24 that is closer to the display area AA. In this case, the first data connection line L13 overlaps with the data signal line L2 in the second group in a direction perpendicular to the plane of the display panel. Therefore, in this embodiment, by arranging the first data connection line L13 and the data signal line L2 in the second group in different film layers, a short circuit between the first data connection line L13 and the data signal line L2 in the second group is avoided.

[0203] Figure 13 A schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 12 and Figure 13As shown, optionally, in the first pixel circuit column group G1, the data signal line L1 in the first group and the data signal line L3 in the third group are electrically connected via a first data connection line L13, and the data signal line L2 in the second group and the data signal line L4 in the fourth group are electrically connected via a second data connection line L24. The first data connection line L13 and the second data connection line L24 are located in the same film layer, or the first data connection line L13 and the second data connection line L24 are located in different film layers.

[0204] Among them, the connection relationship between the first group of data signal lines L1, the second group of data signal lines L2, the third group of data signal lines L3, the fourth group of data signal lines L4, the first data connection lines L13 and the second data connection lines L24 can refer to the above embodiments and will not be repeated here.

[0205] In this embodiment, if Figure 12 and Figure 13 As shown, the first data link line L13 and the second data link line L24 may be located in different film layers.

[0206] For example, Figure 12 and Figure 13 As shown, the data signal output line 40 can be located in the same film layer as the first electrode C1, the data signal line 30 can be located in the same film layer as the source and drain electrode 3, the second data connection line L24 can be located in the same film layer as the data signal line 30, and the first data connection line L13 can be located in the same film layer as the second electrode C2, but is not limited to this.

[0207] Figure 14 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 7 and Figure 14 As shown, optionally, the first data connection line L13 and the second data connection line L24 may be located in the same film layer.

[0208] For example, Figure 7 and Figure 14 As shown, the data signal output line 40 can be located in the same film layer as the first electrode C1, the data signal line 30 can be located in the same film layer as the source and drain electrode 3, and the second data connection line L24 and the first data connection line L13 can both be located in the same film layer as the second electrode C2, but this is not limited to this.

[0209] It should be noted that, under the condition of ensuring that the first data connection line L13 and the second data connection line L24 do not have a short circuit problem, the first data connection line L13 and the second data connection line L24 can be selected to be set in the same layer as the existing metal film layer structure in the pixel circuit 10, thereby reducing the number of metal layers set, which is beneficial to reducing the thickness of the display panel; at the same time, the first data connection line L13 and the second data connection line L24 can also be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, thereby shortening the process time and reducing manufacturing costs.

[0210] Exemplarily, the first data connection line L13 may be located in the same film layer as the data signal output line 40 and / or located in the same film layer as the data signal line 30 , but the present invention is not limited thereto.

[0211] Likewise, the second data connection line L24 can be located in the same film layer as the data signal output line 40 and / or the same film layer as the data signal line 30 , but is not limited thereto.

[0212] The data signal output line 40 may be located in the same film layer as the first electrode plate C1 and / or the second electrode plate C2 , and the data signal line 30 may be located in the same film layer as the source / drain electrode 3 . This embodiment of the present invention does not specifically limit this.

[0213] Continue to refer Figure 7-12 Optionally, the third data signal line 303 includes a first sub-data signal line L5 and a second sub-data signal line L6. In the row direction, the first sub-data signal line L5 and the second sub-data signal line L6 are located on different sides of the second pixel circuit column Z2.

[0214] Specifically, one second pixel circuit column Z2 is correspondingly provided with two third data signal lines 303 , and the two third data signal lines 303 are respectively a first sub-data signal line L5 and a second sub-data signal line L6 .

[0215] Among them, such as Figure 7-12As shown, in the row direction, the first sub-data signal line L5 and the second sub-data signal line L6 are located on different sides of the second pixel circuit column Z2. On the one hand, in the row direction, the first sub-data signal line L5 and the second sub-data signal line L6 are each spaced a certain distance from the second pixel circuit column Z2, thereby preventing parasitic capacitance from forming between the first sub-data signal line L5 and the second sub-data signal line L6 and the metal film layers of the pixel circuits 10 in the second pixel circuit column Z2, thereby reducing the impact of the first sub-data signal line L5 and the second sub-data signal line L6 on the performance of the pixel circuits 10. On the other hand, in the row direction, the first sub-data signal line L5 and the second sub-data signal line L6 can be spaced a large distance apart, thereby reducing mutual interference of data signals between the first sub-data signal line L5 and the second sub-data signal line L6.

[0216] In addition, if Figure 7-12 As shown, in an embodiment of the present invention, the same number of data signal lines 30 are provided between adjacent first pixel circuit columns Z1 and second pixel circuit columns Z2. For example, two data signal lines 30 are provided between adjacent first pixel circuit columns Z1 and second pixel circuit columns Z2, so that the data signal lines 30 are more evenly distributed in the row direction, thereby reducing visual interference caused by uneven reflection of light by the data signal lines 30 and improving the overall visual effect of the display panel.

[0217] Continue to refer Figure 7-12 Optionally, the third data signal line 303 includes a first sub-data signal line L5 and a second sub-data signal line L6. The first sub-data signal line L5 is electrically connected to the third pixel circuits 103 in odd rows in the second pixel circuit column Z2, and the second sub-data signal line L6 is electrically connected to the third pixel circuits 103 in even rows in the second pixel circuit column Z2.

[0218] The structures of the first sub-data signal line L5 and the second sub-data signal line L6 may refer to the above embodiment and will not be described in detail here.

[0219] In this embodiment, if Figure 7-12As shown, by setting the first sub-data signal line L5 to be electrically connected to the third pixel circuit 103 in the odd rows of the second pixel circuit column Z2, and the second sub-data signal line L6 to be electrically connected to the third pixel circuit 103 in the even rows of the second pixel circuit column Z2, the number of pixel circuits 10 connected to each data signal line 30 (for example, the data signal line L1 in the first group, the data signal line L2 in the second group, the data signal line L3 in the third group, the data signal line L4 in the fourth group, the first sub-data signal line L5 and the second sub-data signal line L6) can be the same, so that the capacitive load on each data signal line 30 is relatively consistent, which is beneficial to ensure that all pixel circuits 10 receive the data signal at the same time and strength, thereby helping to improve the display uniformity of the display panel.

[0220] At the same time, the number of nodes connected to the pixel circuit 10 on each data signal line 30 is the same, which can make the pattern distribution of the data signal line 30 more uniform, thereby reducing the visual interference caused by uneven reflection of light by the data signal line 30 and improving the overall visual effect of the display panel.

[0221] Figure 15 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 15 As shown, optionally, the third data signal line 303 includes a first sub-data signal line L5 and a second sub-data signal line L6. The first sub-data signal line L5 is electrically connected to all third pixel circuits 103 in the second pixel circuit column Z2, and the second sub-data signal line L6 is electrically connected to all third pixel circuits 103 in the second pixel circuit column Z2.

[0222] The structures of the first sub-data signal line L5 and the second sub-data signal line L6 may refer to the above embodiment and will not be described in detail here.

[0223] In this embodiment, if Figure 15 As shown, the first sub-data signal line L5 is electrically connected to all the third pixel circuits 103 in the second pixel circuit column Z2, and the second sub-data signal line L6 is electrically connected to all the third pixel circuits 103 in the second pixel circuit column Z2, so that data signals can be written to the third pixel circuits 103 simultaneously through the two data signal lines 30, which is beneficial to reducing the line resistance and further reducing the voltage drop on the data signal line 30, ensuring that the third pixel circuit 103 can receive a more stable data signal. At the same time, it can also increase the writing speed of the data signal, thereby improving the writing efficiency of the data signal.

[0224] Continue to refer Figure 7-Figure 9 、 Figure 11 、 Figure 12 and Figure 15Optionally, the first sub-data signal line L5 and the second sub-data signal line L6 connected to the same second pixel circuit column Z2 are electrically connected.

[0225] Among them, by setting an electrical connection between the first sub-data signal line L5 and the second sub-data signal line L6 connected to the second pixel circuit column Z2, the data signals on the first sub-data signal line L5 and the second sub-data signal line L6 can be provided by the same pin of the IC, thereby reducing the number of pins providing data signals in the IC, which is beneficial to reducing the size and cost of the IC.

[0226] Continue to refer Figure 7 、 Figure 9 、 Figure 11 、 Figure 12 and Figure 15 Optionally, the display panel provided by the embodiment of the present invention further includes a non-display area NAA located on at least one side of the display area AA. The first sub-data signal line L5 and the second sub-data signal line L6 connected to the same second pixel circuit column Z2 are electrically connected via a third data connection line L56, which is located in the non-display area NAA.

[0227] Specifically, such as Figure 7 、 Figure 9 、 Figure 11 、 Figure 12 and Figure 15 As shown, the non-display area NAA may be a lower frame area located on one side of the display area AA along the column direction, but is not limited thereto. The embodiment of the present invention does not specifically limit the positional relationship between the display area AA and the non-display area NAA.

[0228] In this embodiment, if Figure 7 、 Figure 9 、 Figure 11 、 Figure 12 and Figure 15 As shown, by providing a third data connection line L56 extending along the row direction, electrical connection between the first sub-data signal line L5 and the second sub-data signal line L6 corresponding to the same second pixel circuit column Z2 is achieved through the third data connection line L56.

[0229] The third data connection line L56 is located in the non-display area NAA, which can prevent the third data connection line L56 from blocking the display area AA, thereby reducing the impact of the third data connection line L56 on the display effect.

[0230] Continue to refer Figure 8 Optionally, the first sub-data signal line L5 and the second sub-data signal line L6 connected to the same second pixel circuit column Z2 are electrically connected via a third data connection line L56, and the third data connection line L56 is located in the display area AA.

[0231] Specifically, such as Figure 8 As shown, by providing a third data connection line L56 extending along the row direction, electrical connection between the first sub-data signal line L5 and the second sub-data signal line L6 corresponding to the same second pixel circuit column Z2 is achieved through the third data connection line L56.

[0232] Among them, the third data connection line L56 is located in the display area AA, which is different from the solution of setting the third data connection line L56 in the non-display area NAA. It can reduce the number of wiring in the non-display area NAA, thereby helping to reduce the area used for wiring in the non-display area NAA and realize a narrow frame design.

[0233] Continue to refer Figure 8 Optionally, the third data connection line L56 is located between adjacent rows of pixel circuits 10 in the display area AA, which can avoid the formation of parasitic capacitance between the third data connection line L56 and each metal film layer in the pixel circuit 10, thereby reducing the impact of the third data connection line L56 on the performance of the pixel circuit 10, but is not limited to this.

[0234] In other embodiments, the third data connection line L56 may also at least partially overlap with the pixel circuit 10 along a direction perpendicular to the plane of the display panel, so that the third data connection line L56 does not need to occupy additional space, which is beneficial to improving the pixel density of the display panel. The embodiments of the present invention do not specifically limit this.

[0235] Continue to refer Figure 7 and Figure 9Optionally, the plurality of first pixel circuit columns Z1 are divided into a plurality of first pixel circuit column groups G1, wherein the first pixel circuit column group G1 includes two adjacent first pixel circuit columns Z1, namely a first pixel circuit column Z11 and a second pixel circuit column Z12. The first data signal line 301 connected to the first pixel circuit 101 in the first pixel circuit column Z11 is the first data signal line L1 within the group, the second data signal line 302 connected to the second pixel circuit 102 in the first pixel circuit column Z11 is the second data signal line L2 within the group, the first data signal line 301 connected to the first pixel circuit 101 in the second pixel circuit column Z12 is the third data signal line L3 within the group, and the second data signal line 302 connected to the second pixel circuit 102 in the second pixel circuit column Z12 is the fourth data signal line L4 within the group. In the first pixel circuit column group G1, the data signal line L1 within the first group is electrically connected to the data signal line L3 within the third group, and the data signal line L2 within the second group is electrically connected to the data signal line L4 within the fourth group. The first data link line L13 and the second data link line L24 are both located in the non-display area NAA. The third data link line L56 is located on the side of the first data link line L13 closer to the display area AA, and the second data link line L24 is located between the third data link line L56 and the first data link line L13.

[0236] Among them, the structure of the first-group pixel circuit column Z11 and the second-group pixel circuit column Z12 in the first pixel circuit column group G1, as well as the connection relationship between the first-group data signal line L1, the second-group data signal line L2, the third-group data signal line L3, the fourth-group data signal line L4, the first data connection line L13 and the second data connection line L24 can be referred to the above embodiments and will not be repeated here.

[0237] In this embodiment, if Figure 7 and Figure 9 As shown, the first data connection line L13, the second data connection line L24 and the third data connection line L56 are all located in the non-display area NAA, which can prevent the first data connection line L13, the second data connection line L24 and the third data connection line L56 from blocking the display area AA, thereby reducing the influence of the first data connection line L13, the second data connection line L24 and the third data connection line L56 on the display effect.

[0238] Further, if Figure 7 and Figure 9As shown, in the row direction, the third data link line L56, the second data link line L24 and the first data link line L13 are sequentially arranged on one side of the display area AA. Then, in the direction perpendicular to the plane where the display panel is located, the first data link line L13 and the data signal line L2 in the second group and the data signal line L4 in the fourth group can be prevented from overlapping, and the second data link line L24 and the third data signal line 303 can be prevented from overlapping, thereby reducing the coupling capacitance between different data link lines and data signal lines and reducing the mutual interference between different data signals.

[0239] Continue to refer Figure 7 、 Figure 9 、 Figure 11 、 Figure 12 and Figure 15 Optionally, the display panel provided by the embodiment of the present invention further includes a plurality of data signal output lines 40. The data signal output lines 40 include a first data signal output line 401, a second data signal output line 402, and a third data signal output line 403. In the first pixel circuit column group G1, the first data connection line L13 is electrically connected to the first data signal output line 401, and the second data connection line L24 is electrically connected to the second data signal output line 402. The third data connection line L56 is electrically connected to the third data signal output line 403. The third data signal output line 403 and the first data connection line L13 are located in different film layers, and the third data signal output line 403 and the second data connection line L24 are located in different film layers.

[0240] Among them, such as Figure 7 、 Figure 9 、 Figure 11 、 Figure 12 and Figure 15 As shown, a plurality of data signal output lines 40 are provided on the display panel. The data signal output lines 40 are electrically connected to the pins of the integrated circuit IC and the data signal lines 30 respectively. The integrated circuit IC provides data signals to the data signal lines 30 through the data signal output lines 40 .

[0241] Specifically, such as Figure 7 、 Figure 9 、 Figure 11 、 Figure 12 and Figure 15As shown, the data signal output lines 40 include a first data signal output line 401, a second data signal output line 402, and a third data signal output line 403. In the first pixel circuit column group G1, the first group data signal line L1 and the third group data signal line L3 are both electrically connected to the same first data signal output line 401. In this case, the first data signal output line 401 can simultaneously provide data signals to the first group data signal line L1 and the third group data signal line L3. Similarly, in the first pixel circuit column group G1, the second group data signal line L2 and the fourth group data signal line L4 are both electrically connected to the same second data signal output line 402. In this case, the second data signal output line 402 can simultaneously provide data signals to the second group data signal line L2 and the fourth group data signal line L4. In the third data signal line 303 connected to the same second pixel circuit column Z2, the first sub-data signal line L5 and the second sub-data signal line L6 are both electrically connected to the same third data signal output line 403. At this time, the third data signal output line 403 can simultaneously provide data signals to the first sub-data signal line L5 and the second sub-data signal line L6.

[0242] In this embodiment, if Figure 7 、 Figure 9 、 Figure 11 、 Figure 12 and Figure 15 As shown, in a direction perpendicular to the plane where the display panel is located, there is an overlap between the third data signal output line 403 and the first data connection line L13, and there is an overlap between the third data signal output line 403 and the second data connection line L24. Therefore, the third data signal output line 403 and the first data connection line L13 are located in different film layers, and the third data signal output line 403 and the second data connection line L24 are located in different film layers to avoid short circuits between the third data signal output line 403 and the first data connection line L13, and between the third data signal output line 403 and the second data connection line L24.

[0243] It should be noted that, under the condition of ensuring that the third data signal output line 403 and the first data connection line L13 are located in different film layers, the first data connection line L13 can be selected to be set in the same layer as the existing metal film layer structure in the pixel circuit 10, thereby reducing the number of metal layers set, which is beneficial to reducing the thickness of the display panel; at the same time, the first data connection line L13 can also be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, thereby shortening the process time and reducing manufacturing costs.

[0244] Similarly, under the condition of ensuring that the third data signal output line 403 and the second data connection line L24 are located in different film layers, the second data connection line L24 can be selected to be set in the same layer as the existing metal film layer structure in the pixel circuit 10, thereby reducing the number of metal layers set, which is beneficial to reducing the thickness of the display panel; at the same time, the second data connection line L24 can also be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, thereby shortening the process time and reducing manufacturing costs.

[0245] Optionally, the first data link line L13, the second data link line L24 and the third data link line L56 may be located in the same film layer, or at least two of the first data link line L13, the second data link line L24 and the third data link line L56 may be located in different film layers.

[0246] Among them, under the condition of ensuring that the first data connection line L13, the second data connection line L24 and the third data connection line L56 do not have a short circuit problem, the first data connection line L13, the second data connection line L24 and the third data connection line L56 can be selected to be set in the same layer as the existing metal film layer structure in the pixel circuit 10, thereby reducing the number of metal layers set, which is beneficial to reducing the thickness of the display panel; at the same time, the first data connection line L13, the second data connection line L24 and the third data connection line L56 can also be prepared in the same process as the existing metal film layer structure in the pixel circuit 10, thereby shortening the process time and reducing manufacturing costs.

[0247] Continue to refer Figure 9 Optionally, the display panel provided by the embodiment of the present invention further includes a plurality of data signal output lines 40 and a plurality of gating circuits 50. The data signal output lines 40 include a third data signal output line 403, and the gating circuit 50 includes a third gating circuit 503. In the first sub-data signal line L5 and the second sub-data signal line L6 connected to the same second pixel circuit column Z2, the first sub-data signal line L5 and the second sub-data signal line L6 are electrically connected to the same third data signal output line 403 via the third gating circuit 503. The third gating circuit 503 is configured to transmit the data signal output by the third data signal output line 403 to the first sub-data signal line L5 and the second sub-data signal line L6 in a time-sharing manner.

[0248] Among them, such as Figure 9 As shown, a plurality of data signal output lines 40 are provided on the display panel. The data signal output lines 40 are electrically connected to the pins of the integrated circuit IC and the data signal lines 30 respectively. The integrated circuit IC provides data signals to the data signal lines 30 through the data signal output lines 40 .

[0249] The data signal output line 40 includes a third data signal output line 403. In the third data signal line 303 connected to the same second pixel circuit column Z2, the first sub-data signal line L5 and the second sub-data signal line L6 are both electrically connected to the same third data signal output line 403. At this time, the third data signal output line 403 can simultaneously provide data signals to the first sub-data signal line L5 and the second sub-data signal line L6.

[0250] Continue to refer Figure 9 , a third data signal output line 403 needs to provide data signals to the first sub-data signal line L5 and the second sub-data signal line L6 at the same time, then the capacitive load (loading) on ​​the integrated circuit IC pin includes the parasitic capacitance of the pixel circuit 10 connected to the first sub-data signal line L5 and the second sub-data signal line L6, which will cause a problem of large capacitive load. The larger the capacitive load, the more energy required for charging and discharging, and the higher the power consumption.

[0251] Based on the above technical problems, in this embodiment, if Figure 9 As shown, a plurality of gating circuits 50 are further provided on the display panel. The gating circuits 50 are used to transmit the data signal from the data signal output line 40 to different data signal lines 30 in a time-sharing manner, so that at the same time point, the gating circuit 50 will selectively transmit the data signal to one data signal line 30, ensuring that the pin of each integrated circuit IC only provides a data signal to one data signal line 30 at any time, thereby effectively reducing the capacitive load on the pin of the integrated circuit IC and thereby reducing power consumption.

[0252] Specifically, such as Figure 9 As shown, the gating circuit 50 includes a third gating circuit 503. In the first sub-data signal line L5 and the second sub-data signal line L6 connected to the same second pixel circuit column Z2, the first sub-data signal line L5 and the second sub-data signal line L6 are both electrically connected to the same third data signal output line 403 through the third gating circuit 503, so that the data signal output by the third data signal output line 403 is transmitted to the first sub-data signal line L5 and the second sub-data signal line L6 in a time-sharing manner through the third gating circuit 503, ensuring that the integrated circuit IC pin connected to the third data signal output line 403 only provides the data signal to the first sub-data signal line L5 or the second sub-data signal line L6 at any time, thereby reducing the capacitive load on the integrated circuit IC pin and further reducing power consumption.

[0253] Continue to refer Figure 9Optionally, the data signal output line 40, the gating circuit 50 and the integrated circuit IC are all located in the non-display area NAA, which can avoid the data signal output line 40, the gating circuit 50 and the integrated circuit IC from blocking the display area AA, thereby reducing the impact of the data signal output line 40, the gating circuit 50 and the integrated circuit IC on the display effect.

[0254] In other embodiments, the integrated circuit IC may also be disposed on a flexible circuit board bound and connected to the display panel, which is beneficial for reducing the area of ​​the non-display area NAA and achieving a narrow frame design. The embodiments of the present utility model do not specifically limit this.

[0255] Continue to refer Figure 9 Optionally, the data signal output line 40 extends in the column direction and is arranged in the row direction, which facilitates the electrical connection between the data signal output line 40 and the pin of the integrated circuit IC and the data signal line 30 while avoiding short circuits between different data signal output lines 40, but is not limited to this. The embodiments of the present utility model do not make specific limitations on this.

[0256] Continue to refer Figure 9 Optionally, the third gating circuit 503 includes a fifth switching transistor M5 and a sixth switching transistor M6. The fifth switching transistor M5 is connected between the first sub-data signal line L5 and the third data signal output line 403, and the sixth switching transistor M6 is connected between the second sub-data signal line L6 and the third data signal output line 403. The gate of the fifth switching transistor M5 receives the third switching signal, and the gate of the sixth switching transistor L6 receives the fourth switching signal.

[0257] Specifically, such as Figure 9 As shown, the third gating circuit 503 is composed of a fifth switch transistor M5 and a sixth switch transistor M6 , wherein one end of the fifth switch transistor M5 is connected to the first sub-data signal line L5 , and the other end is connected to the third data signal output line 403 .

[0258] Furthermore, the gate of the fifth switching transistor M5 receives a third switching signal, and the third switching signal is used to control the fifth switching transistor M5 to be turned on or off. When the fifth switching transistor M5 is turned on, the first sub-data signal line L5 and the third data signal output line 403 are connected. At this time, the third data signal output line 403 provides a data signal to the first sub-data signal line L5; when the fifth switching transistor M5 is turned off, the first sub-data signal line L5 and the third data signal output line 403 are insulated.

[0259] The gate of the sixth switching transistor M6 receives a fourth switching signal, and the fourth switching signal is used to control the sixth switching transistor M6 to be turned on or off. When the sixth switching transistor M6 is turned on, the second sub-data signal line L6 and the third data signal output line 403 are connected. At this time, the third data signal output line 403 provides a data signal to the second sub-data signal line L6; when the sixth switching transistor M6 is turned off, the second sub-data signal line L6 and the third data signal output line 403 are insulated.

[0260] Among them, the gate of the fifth switching transistor M5 and the gate of the sixth switching transistor M6 receive different third switching signals and fourth switching signals, so that the fifth switching transistor M5 and the sixth switching transistor M6 are turned on in a time-sharing manner, thereby realizing the time-sharing transmission of the data signal output by the third data signal output line 403 to the first sub-data signal line L5 and the second sub-data signal line L6, ensuring that the integrated circuit IC pin connected to the third data signal output line 403 only provides the data signal to the first sub-data signal line L5 or the second sub-data signal line L6 at any time, thereby reducing the capacitive load on the integrated circuit IC pin and reducing power consumption.

[0261] Further, if Figure 9 As shown, the first pixel circuit 101 connected to the data signal line L1 in the first group, the second pixel circuit 102 connected to the data signal line L4 in the fourth group, and the third data signal line 303 connected to the first sub-data signal line L5 are located in the same pixel circuit row. Therefore, the third switching signal received by the gate of the fifth switching transistor M5 can be set to be the same switching signal as the first switching signal SW1 received by the gate of the first switching transistor M1 and the gate of the fourth switching transistor M4, so that the fifth switching transistor M5, the first switching transistor M1 and the fourth switching transistor M4 are turned on at the same time, ensuring that the first pixel circuit 101, the second pixel circuit 102 and the third pixel circuit 103 located in the same row receive the data signal at the same time. Such a setting can reduce the number of switching signals, simplify the control logic, and help reduce the number of switching signal lines that transmit switching signals, thereby reducing costs.

[0262] Similarly, the second pixel circuit 102 connected to the data signal line L2 in the second group, the first pixel circuit 101 connected to the data signal line L3 in the third group, and the third data signal line 303 connected to the second sub-data signal line L6 are located in the same pixel circuit row. Therefore, the fourth switching signal received by the gate of the sixth switching transistor M6 and the second switching signal SW2 received by the gates of the second switching transistor M2 and the gates of the third switching transistor M3 can be set to be the same switching signal, so that the sixth switching transistor M6, the second switching transistor M2, and the third switching transistor M3 are turned on at the same time, ensuring that the first pixel circuit 101, the second pixel circuit 102, and the third pixel circuit 103 located in the same row receive the data signal at the same time. Such a setting can reduce the number of switching signals, simplify the control logic, and help reduce the number of switching signal lines that transmit switching signals, thereby reducing costs.

[0263] Figure 16 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 16 As shown, optionally, the third pixel circuits 103 in a second pixel circuit column Z2 are electrically connected to only one third data signal line 303 .

[0264] In this embodiment, if Figure 16 As shown, each second pixel circuit column Z2 is provided with only one third data signal line 303. This reduces the number of third data signal lines 303, thereby increasing the light transmission area of ​​the display panel. Furthermore, the reduced coverage area of ​​the third data signal lines 303 increases the spacing between the third data signal lines 303 and other signal lines, thereby reducing the coupling effect between the third data signal lines 303 and other signal lines and reducing mutual interference between the signal lines.

[0265] Figure 17 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 18 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 17 and Figure 18 As shown, optionally, the plurality of second pixel circuit columns Z2 are divided into a plurality of second pixel circuit column groups G2. The second pixel circuit column group G2 includes two adjacent second pixel circuit columns Z2, which are respectively a third-group pixel circuit column Z21 and a fourth-group pixel circuit column Z22. The third data signal line 303 connected to the third-group pixel circuit column Z21 is the fifth-group data signal line L7, and the third data signal line 303 connected to the fourth-group pixel circuit column Z22 is the sixth-group data signal line L8.

[0266] In the second pixel circuit column group G2, the fifth group data signal line L7 is located on the side of the third group pixel circuit column Z21 away from the fourth group pixel circuit column Z22, and the sixth group data signal line L8 is located on the side of the fourth group pixel circuit column Z22 away from the third group pixel circuit column Z21.

[0267] or,

[0268] In the second pixel circuit column group G2, the fifth group data signal line L7 is located on the side of the third group pixel circuit column Z21 close to the fourth group pixel circuit column Z22, and the sixth group data signal line L8 is located on the side of the fourth group pixel circuit column Z22 close to the third group pixel circuit column Z21.

[0269] Specifically, such as Figure 17 and Figure 18 As shown, in the display area AA, multiple second pixel circuit column groups G2 are arranged along the row direction, wherein the second pixel circuit column group G2 includes adjacently arranged third-group pixel circuit columns Z21 and fourth-group pixel circuit columns Z22, the third-group pixel circuit columns Z21 include third pixel circuits 103 arranged in sequence along the column direction, and the fourth-group pixel circuit columns Z22 include third pixel circuits 103 arranged in sequence along the column direction.

[0270] In this embodiment, the third pixel circuits 103 in the third pixel circuit column Z21 are all connected to the fifth data signal line L7, and the third pixel circuits 103 in the fourth pixel circuit column Z22 are all connected to the sixth data signal line L8.

[0271] like Figure 17 As shown, along the row direction, in the second pixel circuit column group G2, the fifth data signal line L7 is located on the side of the third pixel circuit column Z21 away from the fourth pixel circuit column Z22, and the sixth data signal line L8 is located on the side of the fourth pixel circuit column Z22 away from the third pixel circuit column Z21. Thus, the fifth data signal line L7 and the sixth data signal line L8 are located on opposite sides of the two second pixel circuit columns Z2 in the second pixel circuit column group G2. With this arrangement, the fifth data signal line L7 and the sixth data signal line L8 are symmetrically distributed relative to the central axis of the second pixel circuit column group G2, which helps achieve greater symmetry in the color shift of the displayed image and improves four-way color shift. That is, regardless of the direction from which the displayed image is viewed, the color consistency and accuracy are improved. Furthermore, the displayed image can be viewed from a wider range of angles without noticeable color changes, thereby enhancing the user experience.

[0272] like Figure 18As shown, along the row direction, in the second pixel circuit column group G2, the fifth data signal line L7 is located on the side of the third pixel circuit column Z21 close to the fourth pixel circuit column Z22, and the sixth data signal line L8 is located on the side of the fourth pixel circuit column Z22 close to the third pixel circuit column Z21. Therefore, the fifth data signal line L7 and the sixth data signal line L8 are both located between the third pixel circuit column Z21 and the fourth pixel circuit column Z22. With this arrangement, the fifth data signal line L7 and the sixth data signal line L8 are symmetrically distributed relative to the central axis of the second pixel circuit column group G2, which helps to achieve more symmetrical color shift in the displayed image, thereby improving four-way color shift. That is, regardless of the direction from which the displayed image is viewed, the color consistency and accuracy are improved. Furthermore, the displayed image can be viewed from a wider range of angles without noticeable color changes, thereby enhancing the user experience.

[0273] It should be noted that the central axis of the second pixel circuit column group G2 is a central axis extending along the column direction.

[0274] Figure 19 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 20 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 19 and Figure 20 As shown, optionally, the plurality of second pixel circuit columns Z2 are divided into a plurality of second pixel circuit column groups G2. The second pixel circuit column group G2 includes two adjacent second pixel circuit columns Z2, which are respectively a third-group pixel circuit column Z21 and a fourth-group pixel circuit column Z22. The third data signal line 303 connected to the third-group pixel circuit column Z21 is the fifth-group data signal line L7, and the third data signal line 303 connected to the fourth-group pixel circuit column Z22 is the sixth-group data signal line L8.

[0275] In the second pixel circuit column group G2, the fifth group data signal line L7 is located on the side of the third group pixel circuit column Z21 away from the fourth group pixel circuit column Z22, and the sixth group data signal line L8 is located on the side of the fourth group pixel circuit column Z22 close to the third group pixel circuit column Z21.

[0276] or,

[0277] In the second pixel circuit column group G2, the fifth group data signal line L7 is located on the side of the third group pixel circuit column Z21 close to the fourth group pixel circuit column Z22, and the sixth group data signal line L8 is located on the side of the fourth group pixel circuit column Z22 away from the third group pixel circuit column Z21.

[0278] The structures of the third and fourth pixel circuit columns Z21 and Z22 in the second pixel circuit column group G2, as well as the connection structures of the fifth and sixth data signal lines L7 and L8 can refer to the above embodiments and will not be described again.

[0279] In this embodiment, if Figure 19 As shown, in the second pixel circuit column group G2, the data signal line L7 in the fifth group is located on the side of the pixel circuit column Z21 in the third group away from the pixel circuit column Z22 in the fourth group, and the data signal line L8 in the sixth group is located on the side of the pixel circuit column Z22 in the fourth group close to the pixel circuit column Z21 in the third group. Then, along the row direction, the data signal line L7 in the fifth group is located on the left side of the pixel circuit column Z21 in the third group, and the data signal line L8 in the sixth group is located on the left side of the pixel circuit column Z22 in the fourth group, that is, the third data signal lines 303 are all located on the same side of the second pixel circuit column Z2 to which they are connected.

[0280] Such a setting can make the positional relationship between the third data signal line 303 and the second pixel circuit column Z2 correspondingly connected to it more consistent. At this time, the parasitic capacitance between the third data signal line 303 and each metal film layer or signal node in the second pixel circuit column Z2 correspondingly connected to it is at a similar level. Therefore, in the process of preparing the display panel, even if there are process fluctuations, the overlapping deviation between the third data signal line 303 and each metal film layer or signal node in the second pixel circuit column Z2 correspondingly connected to it also has the same trend change, thereby improving the display uniformity of the display panel and avoiding the vertical stripe phenomenon caused by brightness difference.

[0281] Continue to refer Figure 20 In the second pixel circuit column group G2, the data signal line L7 in the fifth group is located on the side of the pixel circuit column Z21 in the third group close to the pixel circuit column Z22 in the fourth group, and the data signal line L8 in the sixth group is located on the side of the pixel circuit column Z22 in the fourth group away from the pixel circuit column Z21 in the third group. Then, along the row direction, the data signal line L7 in the fifth group is located on the right side of the pixel circuit column Z21 in the third group, and the data signal line L8 in the sixth group is located on the right side of the pixel circuit column Z22 in the fourth group, that is, the third data signal lines 303 are all located on the same side of the second pixel circuit column Z2 to which they are connected.

[0282] Such a setting can make the positional relationship between the third data signal line 303 and the second pixel circuit column Z2 correspondingly connected to it more consistent. At this time, the parasitic capacitance between the third data signal line 303 and each metal film layer or signal node in the second pixel circuit column Z2 correspondingly connected to it is at a similar level. Therefore, in the process of preparing the display panel, even if there are process fluctuations, the overlapping deviation between the third data signal line 303 and each metal film layer or signal node in the second pixel circuit column Z2 correspondingly connected to it also has the same trend change, thereby improving the display uniformity of the display panel and avoiding the vertical stripe phenomenon caused by brightness difference.

[0283] Figure 21 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 21 As shown, optionally, in a direction perpendicular to the plane of the display panel, the first data signal line 301 and the second data signal line 302 both overlap with the first pixel circuit column Z1 , and the third data signal line 303 overlaps with the second pixel circuit column Z2 .

[0284] Specifically, such as Figure 21 As shown, in a direction perpendicular to the plane where the display panel is located, the first data signal line 301 and the second data signal line 302 are arranged to overlap with the first pixel circuit column Z1, and the third data signal line 303 is arranged to overlap with the second pixel circuit column Z2. This can make it possible for the first data signal line 301, the second data signal line 302 and the third data signal line 303 to not occupy additional space, which is beneficial to improving the pixel density of the display panel.

[0285] Figure 22 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 22 As shown, optionally, multiple columns of first pixel circuit columns Z1 and multiple columns of second pixel circuit columns Z2 are divided into multiple third pixel circuit column groups G3, and the third pixel circuit column group G3 includes first pixel circuit columns Z1 and second pixel circuit columns Z2 adjacent along the row direction, and the adjacent first pixel circuit columns Z1 and second pixel circuit columns Z2 are arranged in a mirror image.

[0286] Specifically, such as Figure 22 As shown, in the display area AA, multiple third pixel circuit column groups G3 are arranged along the row direction, wherein the third pixel circuit column group G3 includes adjacent first pixel circuit columns Z1 and second pixel circuit columns Z2, the first pixel circuit column Z1 includes first pixel circuits 101 and second pixel circuits 102 alternately arranged along the column direction, and the second pixel circuit column Z2 includes third pixel circuits 103 arranged sequentially along the column direction.

[0287] Among them, in the third pixel circuit column group G3, the adjacent first pixel circuit column Z1 and second pixel circuit column Z2 are arranged in a mirror image. At this time, in the same row of pixel circuits 10, the pixel circuit 10 located in the first pixel circuit column Z1 and the pixel circuit 10 located in the second pixel circuit column Z2 are adjacent and arranged in a mirror image. Then, when these two pixel circuits 10 are connected to some signal lines, these two pixel circuits 10 can share a connecting through-hole, thereby reducing the number of punch holes, helping to improve the transmittance of the display panel, and when the display panel is provided with an optical sensing device such as an under-screen fingerprint recognition module, it helps to improve the performance of the optical sensing device.

[0288] For example, Figure 4 The pixel circuit 10 shown in the figure is used as an example for explanation. The pixel circuit 10 may include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, a bias transistor T8 and a storage capacitor Cst.

[0289] Among them, one end of the initialization reset transistor T5 is used to receive the first reference signal VREF1, the other end of the initialization reset transistor T5 and the gate of the driving transistor T3 are connected to the first node N1, the gate of the initialization reset transistor T5 receives the first scanning signal S1N, and the first scanning signal S1N is used to control the conduction and turn-off of the initialization reset transistor T5. When the initialization reset transistor T5 is turned on, the first reference signal VREF1 is written to the gate of the driving transistor T3 to reset the first node N1.

[0290] One plate of the storage capacitor Cst is used to receive the first power signal, and the other plate of the storage capacitor Cst is connected to the first node N1. The storage capacitor Cst can ensure that the potential of the first node N1 is stable.

[0291] The threshold compensation transistor T4 is connected between the gate of the driving transistor T3 (i.e., the first node N1) and the second end of the driving transistor T3 (i.e., the third node N3). The gate of the threshold compensation transistor T4 receives the second scanning signal S2N. The second scanning signal S2N is used to control the conduction and cutoff of the threshold compensation transistor T4. When the threshold compensation transistor T4 is turned on, it can compensate for the threshold voltage of the driving transistor T3.

[0292] One end of the data write transistor T2 is used to receive the data signal DATA, and the other end of the data write transistor T2 is connected to the first end of the driving transistor T3 (i.e., the second node N2). The gate of the data write transistor T2 is used to receive the third scan signal SP, and the third scan signal SP is used to control the conduction and turn-off of the data write transistor T2. When the data write transistor T2 is turned on, the data signal DATA can be written to the gate of the driving transistor T3.

[0293] One end of the anode reset transistor T7 is used to receive the second reference signal VREF2, the other end of the anode reset transistor T7 is connected to the anode of the light-emitting element 20, and the gate of the anode reset transistor T7 is used to receive the fourth scan signal SPX. The fourth scan signal SPX is used to control the on and off of the anode reset transistor T7. When the anode reset transistor T7 is turned on, the second reference signal VREF2 can be written to the anode of the light-emitting element 20.

[0294] One end of the first emission control transistor T1 is configured to receive a positive power supply voltage PVDD, and the other end of the first emission control transistor T1 is connected to the first end of the driving transistor T3 (i.e., the second node N2). One end of the second emission control transistor T6 is configured to receive a negative power supply voltage PVEE, and the other end of the second emission control transistor T6 is connected to the second end of the driving transistor T3 (i.e., the third node N3). The gates of the first emission control transistor T1 and the second emission control transistor T6 are configured to receive a light control signal EM, which is used to control the on and off of the first emission control transistor T1 and the second emission control transistor T6. When the first emission control transistor T1 and the second emission control transistor T6 are on, both the positive power supply voltage PVDD and the negative power supply voltage PVEE can be connected to the light-emitting element 20, thereby enabling the light-emitting element 20 to emit light and display.

[0295] One end of the bias transistor T8 is used to receive the bias signal DVH, and the other end of the bias transistor T8 is connected to the first end of the driving transistor T3 (i.e., the second node N2) or the second end of the driving transistor T3 (i.e., the third node N3). The gate of the bias transistor T8 is used to receive the fourth scanning signal SPX, and the fourth scanning signal SPX is used to control the conduction and cutoff of the bias transistor T8. When the bias transistor T8 is turned on, the bias transistor T8 writes the bias signal DVH to the first end of the driving transistor T3 (i.e., the second node N2) and / or the second end of the driving transistor T3 (i.e., the third node N3).

[0296] Figure 23 The embodiment of the present invention provides a Figure 4 The signal timing diagram of the pixel circuit shown in Figure 4 and Figure 23As shown, the operation process of the pixel circuit 10 may include a pre-stage t10 and a light-emitting stage t20. The pre-stage t10 is a stage in which the light-emitting element 20 does not emit light, and the light-emitting stage t20 is a stage in which the light-emitting element 20 emits light. In some cases, the pre-stage t10 and the light-emitting stage t20 may be performed sequentially.

[0297] Specifically, such as Figure 4 and Figure 23 As shown, in the pre-stage t10, the light-emitting control signal EM is an inactive pulse, and the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned off under the action of the light-emitting control signal EM. At this time, the light-emitting element 20 does not emit light. In the light-emitting stage t20, the light-emitting control signal EM is an active pulse, and the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on under the action of the light-emitting control signal EM. At this time, the driving current generated by the driving transistor T3 can be transmitted to the light-emitting element 20, thereby controlling the light-emitting element O2 to enter the light-emitting stage and emit light.

[0298] It should be noted that the effective pulse of the light emitting control signal EM can be set according to the channel types of the first light emitting control transistor T1 and the second light emitting control transistor T6.

[0299] For example, Figure 4 and Figure 23 As shown, when the first light emitting control transistor T1 and the second light emitting control transistor T6 are both PMOS transistors, the invalid pulse of the light emitting control signal EM is at a high level, and the valid pulse of the light emitting control signal EM is at a low level.

[0300] In other embodiments, if the first light emitting control transistor T1 and the second light emitting control transistor T6 are NMOS transistors, the invalid pulse of the light emitting control signal EM is a low level, and the valid pulse of the light emitting control signal EM is a high level. This embodiment of the utility model does not specifically limit this.

[0301] Continue to refer Figure 4 and Figure 23 Optionally, the pre-phase t10 of the pixel circuit 10 may include an initialization phase t11.

[0302] Among them, in the initialization stage t11, the fourth scanning signal SPX is a valid pulse of a low level, so that the anode reset transistor T7 is turned on, and the second reference signal VREF2 is transmitted to the anode of the light-emitting element 20 through the anode reset transistor T7 to initialize the anode of the light-emitting element 20, thereby preventing the driving current provided to the anode of the light-emitting element 20 in the previous frame from affecting the display luminous brightness of the light-emitting element 20 in the next frame.

[0303] Continue to refer Figure 4 and Figure 23 Optionally, the pre-phase t10 of the pixel circuit 10 may include a reset phase t12.

[0304] Among them, in the reset stage t12, the first scanning signal S1N is a valid signal of a high level, so that the initialization reset transistor T5 is turned on, and the first reference signal VREF1 is transmitted to the gate of the driving transistor T3 (that is, the first node N1) through the turned-on initialization reset transistor T5, thereby resetting the gate of the driving transistor T3. At this time, the gate potential of the driving transistor T3 is consistent with the potential of the first reference signal VREF1, so as to prevent the data signal of the previous frame carried on the gate of the driving transistor T3 from affecting the writing of the data signal of the next frame.

[0305] Continue to refer Figure 4 and Figure 23 Optionally, the pre-stage t10 of the pixel circuit 10 may further include a data writing stage t13.

[0306] In the data writing phase t13, the third scan signal SP is a low-level active pulse, and the second scan signal S2N is a high-level active pulse, causing the data writing transistor T2 and the threshold compensation transistor T4 to be turned on. Simultaneously, the gate potential of the driving transistor T3 is consistent with the first reference signal VREF1, and the driving transistor T3 is also turned on. The data signal passes through the data writing transistor T2, the driving transistor T3, and the threshold compensation transistor T4, and is applied to the gate of the driving transistor T3 (i.e., the first node N1). The potential of the first node N1 is gradually increased until the driving transistor T3 is turned off. When the driving transistor T3 is turned off, the gate potential of the driving transistor T3 is Vdata-|Vth|, where Vdata is the voltage of the data signal DATA and |Vth| is the threshold voltage of the driving transistor T3.

[0307] Continue to refer Figure 4 and Figure 23 Optionally, after the data writing phase t13 ends, the display panel may enter the light emitting phase t20.

[0308] In the light-emitting stage t20, the light-emitting control signal EM is a low-level active pulse, and the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on. Due to the conduction of the first light-emitting control transistor T1, the positive power supply voltage PVDD is transmitted to the first end of the driving transistor T3 (i.e., the second node N2). Then, the voltage difference between the first end of the driving transistor T3 (i.e., the second node N2) and its gate (i.e., the first node N1) is PVDD-(Vdata-|Vth|), so that the driving current generated by the driving transistor T3 is K*(Vdata-PVDD). 2, K is a coefficient related to the size and material of the driving transistor T3. In this way, the driving current generated by the driving transistor T3 is independent of its own threshold voltage |Vth|. The driving current is transmitted to the anode of the light-emitting element 20 through the turned-on second light-emitting control transistor T6, causing the light-emitting element 20 to emit light.

[0309] Continue to refer Figure 4 and Figure 23 Optionally, the pre-stage t10 of the pixel circuit 10 may further include a bias adjustment stage t14.

[0310] In the bias adjustment phase t14, the fourth scanning signal SPX is a low-level valid pulse, which turns on the bias transistor T8. The bias signal DVH is input to the first end (i.e., the second node N2) or the second end (i.e., the third node N3) of the driving transistor T3 via the bias transistor T8 to adjust the voltage difference between the gate (i.e., the first node N1) and the first end (i.e., the second node N2) or the second end (i.e., the third node N3) of the driving transistor T3. This eliminates the reverse electric field generated inside the driving transistor T3, solves the bias problem, and avoids the threshold voltage of the driving transistor T3 from shifting, thereby facilitating the reduction of flicker.

[0311] Continue to refer Figure 4 and Figure 23 In the bias adjustment stage t14, the second scanning signal S2N can be a valid pulse of a high level, so that the threshold compensation transistor T4 is turned on. At this time, the bias signal DVH can be transmitted to the gate of the driving transistor T3 (i.e., the first node N1) through the threshold compensation transistor T4, so that the potential of the gate of the driving transistor T3 (i.e., the first node N1) is consistent with the first end (i.e., the second node N2) or the second end (i.e., the third node N3), which can further improve the threshold voltage offset of the driving transistor T3 and thus reduce the flicker phenomenon.

[0312] The bias adjustment phase t14 may be located before the data writing phase t13 or after the data writing phase t13, and the embodiment of the present invention does not make any specific limitation to this.

[0313] It can be understood that the above is only an illustrative description of the types of transistors in the pixel circuit 10 and the corresponding driving process. In the embodiment of the present invention, when the types of transistors in the pixel circuit 10 change, a driving process similar to the above can be achieved by changing the signal received by the gate of each transistor, which will not be repeated here.

[0314] Furthermore, the types of transistors in the pixel circuit 10 can be diverse. For example, all transistors can be low-temperature polysilicon (LTPS) transistors, or all transistors can be oxide (IGZO) transistors, or some can be LTPS transistors and others can be oxide transistors. LTPS transistors have advantages such as high switching speed, high carrier mobility, and low power consumption, while oxide transistors have advantages such as low leakage current.

[0315] Among them, the low-temperature polycrystalline oxide (LTPO) display panel that combines LTPO with oxide not only has the advantages of high resolution, high response speed, high brightness, and high aperture ratio of low-temperature polysilicon display panels, but also has the advantage of low leakage current of oxide.

[0316] For example, Figure 24 A schematic diagram of a film structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 24 As shown, taking the LTPO display panel as an example, a first semiconductor layer POLY, a first metal layer GAT, a second metal layer MC, a second semiconductor layer IGZO, a third metal layer MG, a fourth metal layer SD1, a fifth metal layer SD2, a sixth metal layer SD3 and an anode layer RE are stacked on one side of the base substrate 60, and an insulating layer 70 can be set between any two adjacent conductive film layers to avoid short circuit between the two adjacent conductive film layers.

[0317] Specifically, Figure 25 for Figure 24 A schematic structural diagram of a first semiconductor layer in a display panel shown; Figure 26 for Figure 24 A schematic structural diagram of a first metal layer in a display panel shown;

[0318] Figure 27 for Figure 24 A schematic structural diagram of a second metal layer in a display panel shown; Figure 28 for Figure 24 A schematic structural diagram of a second semiconductor layer in a display panel shown; Figure 29 for Figure 24 A schematic structural diagram of a third metal layer in a display panel shown; Figure 30 for Figure 24 A schematic structural diagram of a fourth metal layer in a display panel shown; Figure 31 for Figure 24 A schematic structural diagram of a fifth metal layer in a display panel shown; Figure 32 for Figure 24 A schematic structural diagram of a sixth metal layer in a display panel shown; Figure 33 for Figure 24 A schematic structural diagram of an anode layer in a display panel shown; Figure 34 for Figure 24 A schematic diagram of a stacked structure of a portion of film layers in a display panel is shown, specifically a schematic diagram of the stacked structure from the first semiconductor layer to the sixth metal layer;

[0319] Figure 35 for Figure 24 A schematic diagram of a stacked structure of all film layers in a display panel shown, specifically a schematic diagram of the stacked structure from the first semiconductor layer to the anode layer; Figure 36 for Figure 24 Schematic diagram of the entire film structure of a pixel circuit in the display panel shown; To clearly illustrate the structure of the pixel circuit, Figure 37 for Figure 24 The diagram shown is a partial film layer structure diagram of a pixel circuit in a display panel, specifically a schematic diagram of the stacked structure from the first semiconductor layer to the fifth metal layer.

[0320] in, Figures 24-37 The film structure shown can correspond to Figure 4 In the pixel circuit 10 shown in the figure, the threshold compensation transistor T4 and the initialization reset transistor T5 in the pixel circuit 10 are oxide (Indium Gallium Zinc Oxide, IGZO) transistors, and the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the second light-emitting control transistor T6, the anode reset transistor T7 and the bias transistor T8 are low-temperature polysilicon (Low Temperature Poly-Silicon, LTPS) transistors.

[0321] For example, Figure 4 、 Figures 24-37 As shown, active layers of the first light emission control transistor T1 , the data writing transistor T2 , the driving transistor T3 , the second light emission control transistor T6 , the anode reset transistor T7 , and the bias transistor T8 may be located in the first semiconductor layer POLY.

[0322] The first emission control transistor T1 , the data writing transistor T2 , the driving transistor T3 , the second emission control transistor T6 , the anode reset transistor T7 , the gate 2G of the bias transistor T8 , and the first plate C1 of the storage capacitor Cst may be located in the first metal layer GAT.

[0323] The first metal layer GAT also includes a third scan signal line sp, a fourth scan signal line spx, and a light-emission control signal line em extending in the row direction. The third scan signal line sp is electrically connected to the gate of the data write transistor T2 for transmitting a third scan signal SP. The fourth scan signal line spx is electrically connected to the gate of the anode reset transistor T7 and the gate of the bias transistor T8 for transmitting a fourth scan signal SPX. The light-emission control signal line em is electrically connected to the gate of the first light-emission control transistor T1 and the gate of the second light-emission control transistor T6 for transmitting a light-emission control signal EM.

[0324] The second metal layer MC may include a second plate C2 of the storage capacitor Cst, a second reference signal line vref2 extending along the row direction, a second scan signal line s2n, a first scan signal line s1n, and a first reference signal line vref1. The second reference signal line vref2 is electrically connected to the anode reset transistor T7 for transmitting a second reference signal VREF2; the second scan signal line s2n is electrically connected to the gate of the threshold compensation transistor T4 for transmitting a second scan signal S2N; the first scan signal line s1n is electrically connected to the gate of the initialization reset transistor T5 for transmitting a first scan signal S1N; and the first reference signal line vref1 is electrically connected to the initialization reset transistor T5 for transmitting a first reference signal VREF1.

[0325] The second semiconductor layer IGZO may include an active layer of the threshold compensation transistor T4 and an active layer of the initialization reset transistor T5 .

[0326] The third metal layer MG may include gates 2M of the threshold compensation transistor T4 and the initialization reset transistor T5, a bias signal line dvh extending in the row direction, a second scan signal line s2n, and a first scan signal line s1n. The bias signal line dvh is electrically connected to the bias transistor T8 for transmitting a bias signal DVH; the second scan signal line s2n is electrically connected to the gate of the threshold compensation transistor T4 for transmitting a second scan signal S2N; and the first scan signal line s1n is electrically connected to the gate of the initialization reset transistor T5 for transmitting a first scan signal S1N.

[0327] It should be noted that the first scan signal line s1n of the second metal layer MC is electrically connected to the first scan signal line s1n of the third metal layer MG, forming a double-layer wiring structure, which is beneficial to reducing line resistance and further reducing the voltage drop of the first scan signal S1N, thereby ensuring the stability of the first scan signal S1N.

[0328] Similarly, the second scan signal line s2n of the second metal layer MC and the second scan signal line s2n of the third metal layer MG form a double-layer wiring structure, which is beneficial to reducing line resistance and further reducing the voltage drop of the second scan signal S2N, ensuring the stability of the second scan signal S2N.

[0329] The fourth metal layer SD1 may include a bias signal line dvh extending along the column direction, wherein the bias signal line dvh extending along the column direction is electrically connected to the bias signal line dvh extending along the row direction in the second metal layer MC, which can form a grid routing structure, which is beneficial to reducing the line resistance, and thereby reducing the voltage drop of the bias signal DVH, thereby ensuring the stability of the bias signal DVH.

[0330] The fifth metal layer SD2 may include a data signal line 30 and a third power signal line P3 extending along a column direction. The data signal line 30 is used to transmit a data signal DATA, and the third power signal line P3 is used to transmit a positive power voltage PVDD.

[0331] The sixth metal layer SD3 may include a first power signal line P1 extending along the row direction, wherein the first power signal line P1 extending along the row direction is electrically connected to the first power signal line P1 extending along the column direction in the fifth metal layer SD2, and can form a grid routing structure, which is beneficial to reducing line resistance, thereby reducing the voltage drop of the positive power supply voltage PVDD, and ensuring the stability of the positive power supply voltage PVDD.

[0332] The anode layer RE may include an anode 111 of the light emitting element.

[0333] It should be noted that the specific film layer settings of the display panel can be adaptively adjusted according to actual needs, such as adding or removing some film layers, and the embodiments of the present invention do not specifically limit this.

[0334] Further, if Figures 34-37 As shown, in the third pixel circuit column group G3, the adjacent first pixel circuit column Z1 and second pixel circuit column Z2 are arranged in a mirror image. At this time, in the same row of pixel circuits 10, the pixel circuit 10 located in the first pixel circuit column Z1 and the pixel circuit 10 located in the second pixel circuit column Z2 are adjacent and arranged in a mirror image. Then, when these two pixel circuits 10 are connected to some signal lines, the two pixel circuits 10 can share a connecting through-hole, thereby reducing the number of punch holes, helping to improve the transmittance of the display panel, and when an optical sensor device such as an under-screen fingerprint recognition module is provided in the display panel, it helps to improve the performance of the optical sensor device.

[0335] Continue to refer Figure 22 、 Figures 34-37Optionally, in the third pixel circuit column group G3, the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1, and the third data signal line 303 connected to the second pixel circuit column Z2 are both located between the first pixel circuit column Z1 and the second pixel circuit column Z2.

[0336] Specifically, such as Figure 22 、 Figures 34-37 As shown, in the third pixel circuit column group G3, the first data signal line 301, the second data signal line 302, and the third data signal line 303 are all located between the first pixel circuit column Z1 and the second pixel circuit column Z2, so that the first data signal line 301, the second data signal line 302, and the third data signal line 303 in the third pixel circuit column group G3 are concentrated. At this time, the first data signal line 301, the second data signal line 302, and the third data signal line 303 in the third pixel circuit column group G3 are relatively close to each other, so that the parasitic capacitance between the first data signal line 301, the second data signal line 302, and the third data signal line 303 in the third pixel circuit column group G3 and other metal film layers or signal nodes in the pixel circuit 10 in the third pixel circuit column group G3 is at a similar level, which helps to reduce the loss difference between the data signals transmitted on the first data signal line 301, the second data signal line 302, and the third data signal line 303, thereby facilitating improved display uniformity.

[0337] It should be noted that the boundary of the pixel circuit column Z can be set as the gate boundary of the driving transistor T3 of the pixel circuit 10 in the pixel circuit column, then the data signal line 30 in the third pixel circuit column group G3 is located between the first pixel circuit column Z1 and the second pixel circuit column Z2. It can be understood that in the row direction, the data signal line 30 is located between the gates of the driving transistor T3 of the pixel circuit 10 in the first pixel circuit column Z1 and the second pixel circuit column Z2.

[0338] Continue to refer Figure 22 、 Figure 34 and Figure 35 As shown, optionally, in two adjacent third pixel circuit column groups G3 , the arrangement directions of the first data signal lines 301 and the second data signal lines 302 in different third pixel circuit column groups G3 are the same or opposite.

[0339] Specifically, such as Figure 22As shown, in two adjacent third pixel circuit column groups G3, the first data signal lines 301 and the second data signal lines 302 in different third pixel circuit column groups G3 are arranged in opposite directions. Thus, in two adjacent third pixel circuit column groups G3, the first data signal line 301, the second data signal line 302, the third data signal line 303, the third data signal line 303, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged sequentially in the row direction.

[0340] or, Figure 38 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 34 、 Figure 35 and Figure 38 As shown, in two adjacent third pixel circuit column groups G3, the second data signal line 302, the first data signal line 301, the third data signal line 303, the third data signal line 303, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction.

[0341] In another embodiment, in two adjacent third pixel circuit column groups G3, the first data signal line 301, the third data signal line 303, the second data signal line 302, the third data signal line 303, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 may be arranged in sequence in the row direction; or, the second data signal line 302, the third data signal line 303, the first data signal line 301, the third data signal line 303, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 may be arranged in sequence in the row direction.

[0342] In another embodiment, in two adjacent third pixel circuit column groups G3, the first data signal line 301, the third data signal line 303, the third data signal line 303, the second data signal line 302, the second data signal line 302, the third data signal line 303, the third data signal line 303, and the first data signal line 301 may be arranged in sequence in the row direction; or, the second data signal line 302, the third data signal line 303, the third data signal line 303, the first data signal line 301, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 may be arranged in sequence in the row direction.

[0343] With this arrangement, the first data signal lines 301 and the second data signal lines 302 in the two adjacent third pixel circuit column groups G3 are symmetrically distributed, which is conducive to making the color offset of the display image more symmetrical, thereby improving the four-directional color deviation. That is, no matter from which direction the display image is viewed, the consistency and accuracy of the color will be improved, and the display image can be viewed from a wider angle range without perceiving obvious color changes, thereby enhancing the user experience.

[0344] Figure 39 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 40 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 39 and Figure 40 As shown, optionally, in two adjacent third pixel circuit column groups G3 , the first data signal lines 301 and the second data signal lines 302 in different third pixel circuit column groups G3 are arranged in the same direction.

[0345] Specifically, such as Figure 39 As shown, in two adjacent third pixel circuit column groups G3, the first data signal line 301, the second data signal line 302, the third data signal line 303, the third data signal line 303, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction.

[0346] like Figure 40 As shown, optionally, in two adjacent third pixel circuit column groups G3, the second data signal line 302, the first data signal line 301, the third data signal line 303, the third data signal line 303, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction.

[0347] In another embodiment, in two adjacent third pixel circuit column groups G3, the first data signal line 301, the third data signal line 303, the second data signal line 302, the third data signal line 303, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 may be arranged in sequence in the row direction; or, the second data signal line 302, the third data signal line 303, the first data signal line 301, the third data signal line 303, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 may be arranged in sequence in the row direction.

[0348] In another embodiment, in two adjacent third pixel circuit column groups G3, the first data signal line 301, the third data signal line 303, the third data signal line 303, the second data signal line 302, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 may be arranged in sequence in the row direction; or, the second data signal line 302, the third data signal line 303, the third data signal line 303, the first data signal line 301, the second data signal line 302, the third data signal line 303, the third data signal line 303, and the first data signal line 301 may be arranged in sequence in the row direction.

[0349] Such a setting can make the positional relationship between the data signal line 30 connecting the sub-pixels of the same color and the pixel circuit 10 connected thereto more consistent. At this time, the parasitic capacitance between the data signal line 30 connecting the sub-pixels of the same color and the metal film layers or signal nodes in the pixel circuit 10 connected thereto are at a similar level. Therefore, in the process of preparing the display panel, even if there are process fluctuations, the overlapping deviation between the data signal line 30 connecting the sub-pixels of the same color and the metal film layers or signal nodes in the pixel circuit 10 connected thereto also has the same trend change, thereby improving the display uniformity of the display panel and avoiding the vertical stripe phenomenon caused by brightness difference.

[0350] Figure 41 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 42 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 43 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 44 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figures 41-44 As shown, the embodiment of the present invention optionally further includes a plurality of third power signal lines P3, which extend in the column direction and are arranged in the row direction. The plurality of third power signal lines P3 include a first sub-power signal line P3A, a second sub-power signal line P3B, and a third sub-power signal line P3C, which are arranged adjacent to each other in the row direction. The arrangement direction of the first data signal line 301 and the second data signal line 302 between the first sub-power signal line P3A and the second sub-power signal line P3B is the same as or opposite to the arrangement direction of the first data signal line 301 and the second data signal line 302 between the second sub-power signal line P3B and the third sub-power signal line P3C.

[0351] Specifically, such as Figure 34 、 Figure 35 、 Figures 41-44As shown, a third power signal line P3 extending along the column direction may be correspondingly provided for every two columns of pixel circuits 10 . The third power signal line P3 is used to transmit a positive power voltage PVDD.

[0352] Among them, such as Figure 34 、 Figure 35 、 Figure 41 and Figure 42 As shown, in the row direction, three adjacent third power signal lines P3 are respectively set to be the first sub-power signal line P3A, the second sub-power signal line P3B, and the third sub-power signal line P3C. The arrangement direction of the first data signal line 301 and the second data signal line 302 between the first sub-power signal line P3A and the second sub-power signal line P3B can be opposite to the arrangement direction of the first data signal line 301 and the second data signal line 302 between the second sub-power signal line P3B and the third sub-power signal line P3C.

[0353] For example, Figure 41 As shown, between the first sub-power signal line P3A and the second sub-power signal line P3B, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction; between the second sub-power signal line P3B and the third sub-power signal line P3C, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction.

[0354] Or, as Figure 34 、 Figure 35 and Figure 42 As shown, between the first sub-power signal line P3A and the second sub-power signal line P3B, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction; between the second sub-power signal line P3B and the third sub-power signal line P3C, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction.

[0355] In another embodiment, between the first sub-power signal line P3A and the second sub-power signal line P3B, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 may be arranged in sequence in the row direction; between the second sub-power signal line P3B and the third sub-power signal line P3C, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 may be arranged in sequence in the row direction. Alternatively, between the first sub-power signal line P3A and the second sub-power signal line P3B, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 may be arranged in sequence in the row direction; and between the second sub-power signal line P3B and the third sub-power signal line P3C, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 may be arranged in sequence in the row direction.

[0356] In another embodiment, between the first sub-power signal line P3A and the second sub-power signal line P3B, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 may be arranged in sequence in the row direction; between the second sub-power signal line P3B and the third sub-power signal line P3C, the second data signal line 302, the third data signal line 303, the third data signal line 303, and the first data signal line 301 may be arranged in sequence in the row direction. Alternatively, between the first sub-power signal line P3A and the second sub-power signal line P3B, the second data signal line 302, the third data signal line 303, the third data signal line 303, and the first data signal line 301 may be arranged in sequence in the row direction; and between the second sub-power signal line P3B and the third sub-power signal line P3C, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 may be arranged in sequence in the row direction.

[0357] With such an arrangement, the first data signal line 301 and the second data signal line 302 are symmetrically distributed between the first sub-power signal line P3A and the second sub-power signal line P3B, and between the second sub-power signal line P3B and the third sub-power signal line P3C, which is conducive to making the color offset of the display image more symmetrical, thereby improving the four-directional color deviation, that is, no matter from which direction the display image is viewed, the consistency and accuracy of the color will be improved, and the display image can be viewed from a wider angle range without perceiving obvious color changes, thereby enhancing the user experience.

[0358] Continue to refer Figure 43 and Figure 44As shown, optionally, the arrangement direction of the first data signal line 301 and the second data signal line 302 between the first sub-power signal line P3A and the second sub-power signal line P3B is the same as the arrangement direction of the first data signal line 301 and the second data signal line 302 between the second sub-power signal line P3B and the third sub-power signal line P3C.

[0359] Among them, such as Figure 43 As shown, between the first sub-power signal line P3A and the second sub-power signal line P3B, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction; between the second sub-power signal line P3B and the third sub-power signal line P3C, the first data signal line 301, the second data signal line 302, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction.

[0360] like Figure 44 As shown, optionally, between the first sub-power signal line P3A and the second sub-power signal line P3B, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction; between the second sub-power signal line P3B and the third sub-power signal line P3C, the second data signal line 302, the first data signal line 301, the third data signal line 303, and the third data signal line 303 are arranged in sequence in the row direction.

[0361] In another embodiment, the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 may be arranged in sequence in the row direction between the first sub-power signal line P3A and the second sub-power signal line P3B; the first data signal line 301, the third data signal line 303, the second data signal line 302, and the third data signal line 303 may be arranged in sequence in the row direction between the second sub-power signal line P3B and the third sub-power signal line P3C; or, between the first sub-power signal line P3A and the second sub-power signal line P3B, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 may be arranged in sequence in the row direction; and between the second sub-power signal line P3B and the third sub-power signal line P3C, the second data signal line 302, the third data signal line 303, the first data signal line 301, and the third data signal line 303 may be arranged in sequence in the row direction.

[0362] In another embodiment, the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 may be arranged in sequence in the row direction between the first sub-power signal line P3A and the second sub-power signal line P3B; the first data signal line 301, the third data signal line 303, the third data signal line 303, and the second data signal line 302 may be arranged in sequence in the row direction between the second sub-power signal line P3B and the third sub-power signal line P3C; or, between the first sub-power signal line P3A and the second sub-power signal line P3B, the second data signal line 302, the third data signal line 303, the third data signal line 303, the first data signal line 301, and the second data signal line 302 may be arranged in sequence in the row direction; and between the second sub-power signal line P3B and the third sub-power signal line P3C, the third data signal line 303, the third data signal line 303, and the first data signal line 301 may be arranged in sequence in the row direction.

[0363] Such a setting can make the positional relationship between the data signal line 30 connecting the sub-pixels of the same color and the pixel circuit 10 connected thereto more consistent. At this time, the parasitic capacitance between the data signal line 30 connecting the sub-pixels of the same color and the metal film layers or signal nodes in the pixel circuit 10 connected thereto are at a similar level. Therefore, in the process of preparing the display panel, even if there are process fluctuations, the overlapping deviation between the data signal line 30 connecting the sub-pixels of the same color and the metal film layers or signal nodes in the pixel circuit 10 connected thereto also has the same trend change, thereby improving the display uniformity of the display panel and avoiding the vertical stripe phenomenon caused by brightness difference.

[0364] Figure 45 for Figure 24 The schematic diagram of the stacked structure of another part of the film layers in the display panel shown is a schematic diagram of the stacked structure of the first semiconductor layer, the first metal layer, the fourth metal layer and the fifth metal layer, as shown in FIG. Figure 25 、 Figure 26 、 Figure 30 、 Figure 31 and Figure 45As shown, optionally, the pixel circuit 10 includes a data write transistor T2, and the active layer of the data write transistor T2 includes a first connection end E1. In the third pixel circuit column group G3, along the row direction, the first connection end E1 of the first pixel circuit 101 is located on the side of the second data signal line 302 close to the first data signal line 301, and the first data signal line 301 and the first connection end E1 of the first pixel circuit 101 are electrically connected. In the third pixel circuit column group G3, along the row direction, the first connection end E1 of the second pixel circuit 102 is located on the side of the first data signal line 301 close to the second data signal line 302, and the second data signal line 302 and the first connection end E1 of the second pixel circuit 102 are electrically connected.

[0365] Specifically, such as Figure 25 、 Figure 26 、 Figure 30 、 Figure 31 and Figure 45 As shown, the data writing transistor T2 is used to write the data signal DATA from the data signal line 30 into the pixel circuit 10 .

[0366] The active layer of the data writing transistor T2 is located in the first semiconductor layer POLY. A first connecting end E1 is provided at one end of the active layer of the data writing transistor T2 . The first connecting end E1 is used to form an electrical connection with the data signal line 30 .

[0367] Specifically, such as Figure 25 、 Figure 26 、 Figure 30 、 Figure 31 and Figure 45 As shown, in the third pixel circuit column group G3, along the row direction, the first connection end E1 of the first pixel circuit 101 is located on the side of the second data signal line 302 close to the first data signal line 301, so that in the row direction, the first connection end E1 of the first pixel circuit 101 is close to the first data signal line 301, thereby easily achieving electrical connection between the first connection end E1 of the first pixel circuit 101 and the first data signal line 301, and reducing the additional resistance and capacitance that may be introduced during the connection process, which is beneficial to improving the transmission efficiency of the data signal.

[0368] Furthermore, in the third pixel circuit column group G3, along the row direction, the first connection end E1 of the second pixel circuit 102 is located on the side of the first data signal line 301 close to the second data signal line 302, so that in the row direction, the first connection end E1 of the second pixel circuit 102 and the second data signal line 302 are at a closer distance, thereby easily achieving electrical connection between the first connection end E1 of the second pixel circuit 102 and the second data signal line 302, and reducing the additional resistance and capacitance that may be introduced during the connection process, which is beneficial to improving the transmission efficiency of the data signal.

[0369] Optionally, the active layer of the data writing transistor T2 is located in the first semiconductor layer POLY, and the first data signal line 301 and the second data signal line 302 are located in the fifth metal layer SD2. The electrical connection between the first connection end E1 of the first pixel circuit 101 and the first data signal line 301, and the electrical connection between the first connection end E1 of the second pixel circuit 102 and the second data signal line 302 can be achieved by drilling a hole in the insulating layer 70 between the first semiconductor layer POLY and the fifth metal layer SD2.

[0370] Further, continue to refer to Figure 25 、 Figure 26 、 Figure 30 、 Figure 31 and Figure 45 Optionally, the fourth metal layer SD1 includes a first connection portion 71 and a second connection portion 72. The first connection end E1 of the first pixel circuit 101 and the first data signal line 301 can be electrically connected through the first connection portion 71. For example, the first connection portion 71 is connected to the first connection end E1 of the first pixel circuit 101 through a punching connection, and the first data signal line 301 is connected to the first connection portion 71 through a punching connection. This can reduce the depth of each punching, thereby avoiding a circuit break caused by excessive punching depth. Similarly, the first connection end E1 of the second pixel circuit 102 and the second data signal line 302 can be electrically connected through the second connection portion 72. For example, the second connection portion 72 is connected to the first connection end E1 of the second pixel circuit 102 through a punching connection, and the second data signal line 302 is connected to the second connection portion 72 through a punching connection. This can reduce the depth of each punching, thereby avoiding a circuit break caused by excessive punching depth.

[0371] Continue to refer Figure 25 、 Figure 26 、 Figure 30 、 Figure 31 and Figure 45Optionally, two third data signal lines 303 may be correspondingly set in a column of second pixel circuits Z2, wherein one third data signal line 303 is electrically connected to the third pixel circuits 103 in odd rows in the second pixel circuit column Z2, and the other third data signal line 303 is electrically connected to the third pixel circuits 103 in even rows in the second pixel circuit column Z2.

[0372] Among them, the connection structure between the first connection end E1 of the third pixel circuit 103 and the corresponding third data signal line 303 can refer to the connection structure between the first connection end E1 of the first pixel circuit 101 and the first data signal line 301, and the connection structure between the first connection end E1 and the second data signal line 302 of the second pixel circuit 102. In this way, the connection structure between the first connection end E1 of the third pixel circuit 103 and the corresponding third data signal line 303 and the connection structure between the first connection end E1 of the first pixel circuit 101 and the first data signal line 301, and the connection structure between the first connection end E1 of the second pixel circuit 102 and the second data signal line 302 form a symmetrical distribution, which is conducive to making the color deviation of the display image more symmetrical, thereby improving the four-directional color deviation, which will not be repeated here.

[0373] Figure 46 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 47 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 46 and Figure 47 As shown, the display area AA optionally includes a first display area AA1 and a second display area AA2. Along the row direction, the first display area AA1 is located on at least one side of the second display area AA2. The display panel also includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2 and are electrically connected to the data signal lines 30 in the first display area AA1. In the third pixel circuit column group G3, the auxiliary signal lines FIAA are located between the data signal lines 30 connected to the first pixel circuit column Z1 and the data signal lines 30 connected to the second pixel circuit column Z2.

[0374] Specifically, such as Figure 46 and Figure 47As shown, the display area AA may include a first display area AA1 and a second display area AA2. The figure exemplarily shows that in the row direction, the first display area AA1 is located on both sides of the second display area AA2, wherein the first display area AA1 is located between the second display area AA2 and the non-display areas NAA on the left and right sides. Along the row direction, the second display area AA2 is closer to the center of the display panel, and the first display area AA1 is closer to the edge of the display panel. Under this setting, the non-display area NAA includes a fan-out area NAA1, and the fan-out area NAA1 is located on one side of the display area AA along the column direction. Taking the lower side as an example in the figure, the fan-out area NAA1 can be equipped with multiple data signal output lines 40, and the data signal output lines 40 are respectively electrically connected to the data signal lines 30 and the integrated circuit IC, thereby realizing the electrical connection between the integrated circuit IC and the data signal line 30, ensuring the stable transmission of the data signal, but it is not limited to this.

[0375] Further, if Figure 46 and Figure 47 As shown, multiple data signal lines 30 are provided in both the first display area AA1 and the second display area AA2. The data signal lines 30 located in the second display area AA2 can be directly connected to the data signal output lines 40. The data signal lines 30 located in the first display area AA1 are connected to the data signal output lines 40 via auxiliary signal lines FIAA located at least partially in the second display area AA2. In this way, the data signal output lines 40 can be centrally arranged in the fan-out area NAA1 below the second display area AA2, thereby reducing the space occupied by the data signal output lines 40. This can further reduce the installation area of ​​the fan-out area NAA1, effectively reducing the area occupied by the non-display area NAA, and achieving a narrow bezel effect.

[0376] Continue to refer Figure 47 In the third pixel circuit column group G3, the auxiliary signal line FIAA is located between the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1, and the third data signal line 303 connected to the second pixel circuit column Z2. Since the auxiliary signal line FIAA is also used to transmit data signals, the auxiliary signal line FIAA is placed together with the first data signal line 301, the second data signal line 302 and the third data signal line 303. At this time, the auxiliary signal line FIAA, the first data signal line 301, the second data signal line 302 and the third data signal line 303 are at a relatively close distance, so that the parasitic capacitance between the auxiliary signal line FIAA, the first data signal line 301, the second data signal line 302 and the third data signal line 303 and the metal film layer or signal node in the pixel circuit 10 is at a similar level, which helps to reduce the loss difference between the data signals transmitted on the auxiliary signal line FIAA, the first data signal line 301, the second data signal line 302 and the third data signal line 303, thereby facilitating improvement of display uniformity.

[0377] At the same time, the auxiliary signal line FIAA is located between the data signal line 30 connected to the first pixel circuit column Z1 and the data signal line 30 connected to the second pixel circuit column Z2, which can reduce the influence of the auxiliary signal line FIAA on the connection between the pixel circuit 10 and the data signal line 30 in the first pixel circuit column Z1 and the second pixel circuit column Z2.

[0378] Continue to refer Figure 47 Optionally, the number of the corresponding auxiliary signal lines FIAA in a third pixel circuit column group G3 is less than or equal to one.

[0379] Specifically, such as Figure 47 As shown, since two data signal lines 30 are correspondingly provided for a first pixel circuit column Z1 and one data signal line 30 is correspondingly provided for a second pixel circuit column Z2, at least three data signal lines 30 are provided in the third pixel circuit column group G3. In this embodiment, by setting the number of the corresponding auxiliary signal line FIAA in the third pixel circuit column group G3 to be less than or equal to 1, it is avoided that too many signal lines for transmitting data signals in the third pixel circuit column group G3 result in the signal lines for transmitting data signals being too dense, thereby ensuring that there can be sufficient spacing between the signal lines for transmitting data signals, thereby reducing the coupling capacitance between each data signal line 30 and the auxiliary signal line FIAA, and reducing the mutual interference of data signals between each data signal line 30 and the auxiliary signal line FIAA.

[0380] It should be noted that Figure 47 The description is made by taking an example where one auxiliary signal line FIAA is provided in one third pixel circuit column group G3 , but the invention is not limited thereto.

[0381] Figure 48 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 47-48 As shown, the display area AA optionally includes a first display area AA1 and a second display area AA2. Along the row direction, the first display area AA1 is located on at least one side of the second display area AA2. The display panel also includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2 and are electrically connected to the data signal lines 30 in the first display area AA1.

[0382] The auxiliary signal lines FIAA and the data signal lines 30 are located in different film layers.

[0383] In a direction perpendicular to the plane of the display panel, the auxiliary signal line FIAA at least partially overlaps with the data signal line 30 .

[0384] or,

[0385] In a direction perpendicular to the plane of the display panel, the auxiliary signal line FIAA does not overlap with the data signal line 30 .

[0386] The positional relationship between the first display area AA1 and the second display area AA2, and the distribution and connection structure of the auxiliary signal lines FIAA may refer to the above embodiments and will not be described in detail here.

[0387] In this embodiment, if Figure 47 and Figure 48 As shown, the auxiliary signal line FIAA and the data signal line 30 are located in different film layers, which can increase the distance between the auxiliary signal line FIAA and the data signal line 30, thereby reducing the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and further reducing the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0388] Further, if Figure 47 and Figure 48 As shown, in the direction perpendicular to the plane of the display panel, the auxiliary signal line FIAA and the data signal line 30 do not overlap, which can further reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, thereby reducing the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0389] Figure 49 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 49 As shown, optionally, in a direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA at least partially overlaps with the data signal line 30.

[0390] This configuration can reduce the total shielding area of ​​the auxiliary signal lines FIAA and the data signal lines 30 in the thickness direction of the display panel, help reduce the impact of the auxiliary signal lines FIAA and the data signal lines 30 on the display effect of the display area AA, and increase the light transmission area of ​​the display panel.

[0391] Figure 50 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 51 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 52 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown below. Figure 53 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 50-53As shown, optionally, a first pixel circuit column Z1 corresponds to an auxiliary signal line FIAA, and a second pixel circuit column Z2 corresponds to an auxiliary signal line FIAA.

[0392] In the third pixel circuit column group G3, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located between the first data signal line 301 and the second data signal line 302 corresponding to the first pixel circuit column Z1, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located between the two third data signal lines 303 corresponding to the second pixel circuit column Z2.

[0393] or,

[0394] In the third pixel circuit column group G3, along the row direction, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located on the same side of the first data signal line 301 and the second data signal line 302 corresponding to the first pixel circuit column Z1, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located on the same side of the two third data signal lines 303 corresponding to the second pixel circuit column Z2.

[0395] or,

[0396] In a direction perpendicular to the plane of the display panel, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30 corresponding to the first pixel circuit column Z1 at least partially overlap, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the data signal line 30 corresponding to the second pixel circuit column Z2 at least partially overlap.

[0397] Specifically, such as Figure 50-53 As shown, one auxiliary signal line FIAA is correspondingly set for a first pixel circuit column Z1, one auxiliary signal line FIAA is correspondingly set for a second pixel circuit column Z2, and two auxiliary signal lines FIAA are correspondingly set for a third pixel circuit column group G3 to increase the number of auxiliary signal lines FIAA. In this way, the setting area of ​​the first display area AA1 can be increased, which is conducive to achieving a narrow frame effect.

[0398] Among them, such as Figure 50As shown, in the third pixel circuit column group G3, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located between the first data signal line 301 and the second data signal line 302 corresponding to the first pixel circuit column Z1, so as to concentrate the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302, so that the parasitic capacitance between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1, the first data signal line 301 and the second data signal line 302 and each metal film layer or signal node in the pixel circuit 10 is at a similar level, which helps to reduce the loss difference between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signals transmitted on the first data signal line 301 and the second data signal line 302, thereby helping to improve display uniformity.

[0399] Further, if Figure 50 As shown, in the direction perpendicular to the plane where the display panel is located, there is no overlapping area between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302, which can reduce the coupling capacitance between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302, thereby reducing the mutual interference of data signals between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the first data signal line 301 and the second data signal line 302.

[0400] Similarly, if Figure 50 As shown, the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located between the two third data signal lines 303 corresponding to the second pixel circuit column Z2, so that the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303 are placed together, so that the parasitic capacitance between the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303 and each metal film layer or signal node in the pixel circuit 10 is at a similar level, which helps to reduce the loss difference between the data signals transmitted on the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303, thereby helping to improve display uniformity.

[0401] Further, if Figure 50 As shown, in the direction perpendicular to the plane where the display panel is located, there is no overlapping area between the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303, which can reduce the coupling capacitance between the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303, thereby reducing the mutual interference of data signals between the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the third data signal line 303.

[0402] Continue to refer Figure 51 and Figure 52 Optionally, in the third pixel circuit column group G3, along the row direction, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is located on the same side as the first data signal line 301 and the second data signal line 302 corresponding to the first pixel circuit column Z1, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located on the same side as the two third data signal lines 303 corresponding to the second pixel circuit column Z2. In a direction perpendicular to the plane of the display panel, there is no overlapping area between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30, which can reduce the coupling capacitance between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30, thereby reducing mutual interference of data signals between the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30.

[0403] in, Figure 51 The auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is exemplarily illustrated as being located on a side of the two data signal lines 30 corresponding to the first pixel circuit column Z1 close to the second pixel circuit column Z2, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located on a side of the two third data signal lines 303 corresponding to the second pixel circuit column Z2 close to the first pixel circuit column Z1. Figure 52 The auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 is exemplarily illustrated as being located on a side of the two data signal lines 30 corresponding to the first pixel circuit column Z1 away from the second pixel circuit column Z2, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 is located on a side of the two third data signal lines 303 corresponding to the second pixel circuit column Z2 away from the first pixel circuit column Z1, but is not limited to this.

[0404] Continue to refer Figure 53 Optionally, in a direction perpendicular to the plane of the display panel, the auxiliary signal line FIAA corresponding to the first pixel circuit column Z1 and the data signal line 30 corresponding to the first pixel circuit column Z1 at least partially overlap, and the auxiliary signal line FIAA corresponding to the second pixel circuit column Z2 and the data signal line 30 corresponding to the second pixel circuit column Z2 at least partially overlap. This configuration can reduce the total shielding area of ​​the auxiliary signal line FIAA and the data signal line 30 in the thickness direction of the display panel, thereby increasing the light transmission area of ​​the display panel and reducing the impact of the auxiliary signal line FIAA and the data signal line 30 on the display effect of the display area AA.

[0405] Figure 54 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 54As shown, optionally, the third pixel circuit column group G3 corresponds to three auxiliary signal lines FIAA. In the third pixel circuit column group G3, along the row direction, the three auxiliary signal lines FIAA are located between the first pixel circuit column Z1 and the second pixel circuit column Z2, and the auxiliary signal line FIAA is located between two adjacent data signal lines 30.

[0406] Specifically, such as Figure 54 As shown, two columns of pixel circuits 10 can correspond to three auxiliary signal lines FIAA. At this time, three auxiliary signal lines FIAA are correspondingly set for a third pixel circuit column group G3 to increase the number of auxiliary signal lines FIAA. In this way, the setting area of ​​the first display area AA1 can be increased, which is conducive to achieving a narrow frame effect.

[0407] like Figure 54 As shown, in the third pixel circuit column group G3, along the row direction, three auxiliary signal lines FIAA are located between the first pixel circuit column Z1 and the second pixel circuit column Z2, so as to concentrate the auxiliary signal lines FIAA and the data signal lines 30, so that the parasitic capacitance between the auxiliary signal lines FIAA and the data signal lines 30 and the metal film layer or signal node in the pixel circuit 10 is at a similar level, which helps to reduce the loss difference between the data signals transmitted on the auxiliary signal lines FIAA and the data signal lines 30, and improve display uniformity.

[0408] Further, if Figure 54 As shown, the three auxiliary signal lines FIAA can be respectively located between two adjacent data signal lines 30. Then, in the direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA can not overlap with the data signal line 30, which can further reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, thereby reducing the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0409] Meanwhile, in the third pixel circuit column group G3, the three auxiliary signal lines FIAA can be evenly distributed in the gaps between the four data signal lines 30, thereby reducing visual interference caused by uneven light reflection from the auxiliary signal lines FIAA and improving the overall visual effect of the display panel.

[0410] Figure 55 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 55 As shown, optionally, a first pixel circuit column Z1 corresponds to two auxiliary signal lines FIAA, and a second pixel circuit column Z2 corresponds to two auxiliary signal lines FIAA. In a direction perpendicular to the plane of the display panel, the auxiliary signal lines FIAA and the data signal lines 30 at least partially overlap.

[0411] Specifically, such as Figure 55 As shown, each column of pixel circuits 10 can be correspondingly provided with four auxiliary signal lines FIAA. At this time, a third pixel circuit column group G3 is correspondingly provided with four auxiliary signal lines FIAA to increase the number of auxiliary signal lines FIAA. This can increase the setting area of ​​the first display area AA1, which is conducive to achieving a narrow frame effect.

[0412] Further, if Figure 55 As shown, in the direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA and the data signal line 30 at least partially overlap. Such an arrangement can reduce the total blocking area of ​​the auxiliary signal line FIAA and the data signal line 30 in the thickness direction of the display panel, thereby increasing the light-transmitting area of ​​the display panel and reducing the influence of the auxiliary signal line FIAA and the data signal line 30 on the display effect of the display area AA.

[0413] Continue to refer Figure 47 Optionally, in the third pixel circuit column group G3, the first data signal line 301 connected to the first pixel circuit column Z1 is located on a side of the second data signal line 302 connected to the first pixel circuit column Z1 away from the first pixel circuit column Z1, and the spacing between the auxiliary signal line FIAA and the second data signal line 302 is greater than the spacing between the auxiliary signal line FIAA and the third data signal line 303.

[0414] or,

[0415] In the third pixel circuit column group G3, the second data signal line 302 connected to the first pixel circuit column Z1 is located on a side of the first data signal line 301 connected to the first pixel circuit column Z1 away from the first pixel circuit column Z1, and the distance between the auxiliary signal line FIAA and the first data signal line 301 is greater than the distance between the auxiliary signal line FIAA and the third data signal line 303.

[0416] Specifically, such as Figure 47 As shown, a first pixel circuit column Z1 is correspondingly provided with a first data signal line 301 and a second data signal line 302 , a second pixel circuit column Z2 is correspondingly provided with a third data signal line 303 , and a third pixel circuit column group G3 is provided with three data signal lines 30 .

[0417] like Figure 47As shown, in this embodiment, when the first data signal line 301 connected to the first pixel circuit column Z1 is located on a side of the second data signal line 302 connected to the first pixel circuit column Z1 away from the first pixel circuit column Z1, the spacing between the auxiliary signal line FIAA and the second data signal line 302 is set to be greater than the spacing between the auxiliary signal line FIAA and the third data signal line 303, so that the auxiliary signal line FIAA deviates from the center of the third pixel circuit column group G3. At this time, the auxiliary signal line FIAA is located between the first data signal line 301 and the third data signal line 303, and the spacing between the auxiliary signal line FIAA and the first data signal line 301, and the spacing between the auxiliary signal line FIAA and the third data signal line 303 are more consistent. Then, in the third pixel circuit column group G3, the distribution of the auxiliary signal line FIAA and the data signal line 30 is more uniform, thereby reducing the visual interference caused by the uneven reflection of light by the auxiliary signal line FIAA and the data signal line 30, thereby improving the overall visual effect of the display panel.

[0418] Continue to refer Figure 47 Optionally, when the second data signal line 302 connected to the first pixel circuit column Z1 is located on a side of the first data signal line 301 connected to the first pixel circuit column Z1 away from the first pixel circuit column Z1, the distance between the auxiliary signal line FIAA and the first data signal line 301 is set to be greater than the distance between the auxiliary signal line FIAA and the third data signal line 303, so that the auxiliary signal line FIAA deviates from the center of the third pixel circuit column group G3. At this time, the auxiliary signal line FIAA is located between the second data signal line 302 and the third data signal line 303, and the distance between the auxiliary signal line FIAA and the second data signal line 302, and the distance between the auxiliary signal line FIAA and the third data signal line 303 are more consistent. Then, in the third pixel circuit column group G3, the distribution of the auxiliary signal line FIAA and the data signal line 30 is more uniform, thereby reducing the visual interference caused by the uneven reflection of light by the auxiliary signal line FIAA and the data signal line 30, thereby improving the overall visual effect of the display panel.

[0419] Continue to refer Figure 47 Optionally, in the third pixel circuit column group G3 , the number of data signal lines 30 connected to the first pixel circuit column Z1 is greater than the number of data signal lines 30 connected to the second pixel circuit column Z2 .

[0420] Specifically, such as Figure 27As shown, in the third pixel circuit column group G3, by setting the number of data signal lines 30 connected to the second pixel circuit column Z2 to be smaller than the number of data signal lines 30 connected to the first pixel circuit column Z1, the number of data signal lines 30 can be reduced while ensuring the display effect, so that sufficient setting space can be provided for the auxiliary signal line FIAA while ensuring the transmittance, which is beneficial to increase the spacing between the auxiliary signal line FIAA and the data signal line 30, reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and thereby reduce the mutual interference of data signals between the auxiliary signal line FIAA and the data signal line 30.

[0421] Continue to refer Figure 46 and Figure 47 Optionally, the display area AA includes a first display area AA1 and a second display area AA2. Along the row direction, the first display area AA1 is located on at least one side of the second display area AA2. The display panel also includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected to the data signal lines 30 in the first display area AA1. In the third pixel circuit column group G3, along the row direction, the number of data signal lines 30 on either side of the auxiliary signal lines FIAA is different.

[0422] The positional relationship between the first display area AA1 and the second display area AA2, and the distribution and connection structure of the auxiliary signal lines FIAA may refer to the above embodiments and will not be described in detail here.

[0423] In this embodiment, if Figure 46 and Figure 47 As shown, in the third pixel circuit column group G3, along the row direction, the number of data signal lines 30 on both sides of the auxiliary signal line FIAA is different. When the number of data signal lines 30 in the third pixel circuit column group G3 is an odd number, the distribution of the auxiliary signal line FIAA and the data signal line 30 can be made more uniform, thereby reducing the visual interference caused by the uneven reflection of light from the auxiliary signal line FIAA and the data signal line 30, and improving the overall visual effect of the display panel.

[0424] Optionally, multiple data signal lines 30 are located in the same film layer.

[0425] By arranging all the data signal lines 30 to be located in the same film layer, the number of film layers can be reduced, thereby facilitating a reduction in the thickness of the display panel and achieving a lightweight and thin design.

[0426] For example, Figures 24-37 As shown, the data signal lines 30 may all be disposed on the fifth metal layer SD2 , but the present invention is not limited thereto.

[0427] Optionally, along a direction parallel to the plane where the display panel is located, the spacing between adjacent data signal lines 30 is greater than or equal to 2.5 μm. This can avoid signal interference between adjacent data signal lines 30 caused by adjacent data signal lines 30 being too close, making the data signal transmitted on the data signal line 30 more accurate and stable, but is not limited to this.

[0428] It should be noted that the spacing between adjacent data signal lines 30 can be set according to actual needs, and the embodiments of the present invention do not limit this. It can be understood that the larger the spacing between adjacent data signal lines 30, the smaller the signal interference between adjacent data signal lines 30; but the smaller the spacing between adjacent data signal lines 30, the more conducive it is to compressing the size of the pixel circuit 10, thereby helping to improve the pixel density of the display panel.

[0429] Figure 56 A partial cross-sectional structural diagram of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 56 As shown, optionally, at least two data signal lines 30 are located in different film layers, and in a direction perpendicular to the plane where the display panel is located, the data signal lines 30 located in different film layers at least partially overlap.

[0430] Specifically, such as Figure 56 As shown, by arranging at least two data signal lines 30 in different film layers, it helps to increase the spacing between different data signal lines 30, reduce the coupling capacitance between different data signal lines 30, and thus reduce the mutual interference of data signals between different data signal lines 30.

[0431] Further, if Figure 56 As shown, in a direction perpendicular to the plane where the display panel is located, the data signal lines 30 located in different film layers are arranged to at least partially overlap, which can reduce the overall blocking area of ​​the data signal lines 30 in the thickness direction of the display panel, thereby increasing the light-transmitting area of ​​the display panel and reducing the impact of the data signal lines 30 on the display effect of the display area AA.

[0432] Continue to refer Figure 35 and Figure 36 Optionally, the light-emitting element 20 includes a red light-emitting element 20R, a blue light-emitting element 20B and a green light-emitting element 20G, the first pixel circuit 101 is connected to the red light-emitting element 20R, the second pixel circuit 102 is connected to the blue light-emitting element 20B, and the third pixel circuit 103 is connected to the green light-emitting element 20G.

[0433] Specifically, such as Figure 35 and Figure 36As shown, the light-emitting element 20 may include a red light-emitting element 20R that emits red light, a blue light-emitting element 20B that emits blue light, and a green light-emitting element 20G that emits green light to achieve color image display, but is not limited to this. In some embodiments, the light-emitting element 20 may also include a white light-emitting element that emits white light, and the embodiments of the present utility model do not make specific limitations on this.

[0434] Continue to refer Figure 35 and Figure 36 In the first pixel circuit column Z1, the red light-emitting element 20R connected to the first pixel circuit 101 and the blue light-emitting element 20B connected to the second pixel circuit 102 are arranged alternately in the column direction; in the second pixel circuit column Z2, the green light-emitting element 20G connected to the third pixel circuit 103 is arranged in sequence in the column direction.

[0435] Such a setting can make the number of green light-emitting elements 20G greater. Since the human eye is most sensitive to green, by setting the number of green light-emitting elements 20G to be greater than the number of green light-emitting elements 20G or the number of blue light-emitting elements 20B, the high sensitivity of the human eye to green can be better met, which is beneficial to improving the display quality.

[0436] Figure 57 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 46 and Figure 57 As shown, optionally, the display area AA includes a first display area AA1 and a second display area AA2, and along the row direction, the first display area AA1 is located on at least one side of the second display area AA2. The display panel also includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected to the data signal lines 30 in the first display area AA1. The multiple columns of first pixel circuit columns Z1 and the multiple columns of second pixel circuit columns Z2 are divided into a plurality of third pixel circuit column groups G3, and the third pixel circuit column group G3 includes the first pixel circuit columns Z1 and the second pixel circuit columns Z2 adjacent to each other along the row direction.

[0437] The third pixel circuit column group G3 corresponds to an auxiliary signal line FIAA, and the second pixel circuit column Z2 corresponds to a third data signal line 303. In the third pixel circuit column group G3, the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1 are located on different sides of the first pixel circuit column Z1. In at least one third pixel circuit column group G3 in the second display area AA2, the auxiliary signal line FIAA and the third data signal line 303 connected to the second pixel circuit column Z2 are located on different sides of the second pixel circuit column Z2.

[0438] Among them, the positional relationship between the first display area AA1 and the second display area AA2, the connection structure of the auxiliary signal line FIAA, and the structure of the first pixel circuit column Z1 and the second pixel circuit column Z2 in the third pixel circuit column group G3 can be referred to the above embodiments and will not be repeated here.

[0439] In this embodiment, if Figure 46 and Figure 57 As shown, a third pixel circuit column group G3 is correspondingly provided with an auxiliary signal line FIAA, and a second pixel circuit column Z2 is correspondingly connected with a third data signal line 303, thereby providing sufficient setting space for the auxiliary signal line FIAA while ensuring the transmittance, which is beneficial to increase the distance between the auxiliary signal line FIAA and the data signal line 30, reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and further reduce the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0440] Further, if Figure 46 and Figure 57 As shown, in the third pixel circuit column group G3, the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1 are located on different sides of the first pixel circuit column Z1. On the one hand, in the row direction, the first data signal line 301 and the second data signal line 302 are spaced a certain distance from the first pixel circuit column Z1. This prevents parasitic capacitance from forming between the first data signal line 301 and the second data signal line 302 and the metal film layers of the pixel circuits 10 in the first pixel circuit column Z1, thereby reducing the impact of the first data signal line 301 and the second data signal line 302 on the performance of the pixel circuits 10. On the other hand, in the row direction, the first data signal line 301 and the second data signal line 302 can be spaced a large distance apart, thereby reducing mutual interference of data signals between the first data signal line 301 and the second data signal line 302.

[0441] Similarly, in at least one third pixel circuit column group G3, the auxiliary signal line FIAA and the third data signal line 303 connected to the second pixel circuit column Z2 are located on different sides of the second pixel circuit column Z2. On the one hand, in the row direction, the auxiliary signal line FIAA and the third data signal line 303 are spaced a certain distance from the second pixel circuit column Z2. This prevents parasitic capacitance from forming between the auxiliary signal line FIAA and the third data signal line 303 and the various metal film layers of the pixel circuits 10 in the second pixel circuit column Z2, thereby reducing the impact of the auxiliary signal line FIAA and the third data signal line 303 on the performance of the pixel circuits 10. On the other hand, in the row direction, a larger distance can be provided between the auxiliary signal line FIAA and the third data signal line 303, thereby reducing mutual interference of data signals between the auxiliary signal line FIAA and the third data signal line 303.

[0442] Figure 58 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 58 As shown, optionally, in the row direction, the first data signal line 301 connected to the first pixel circuit column Z1 and the second data signal line 302 connected to the second pixel circuit column Z2 are respectively located on opposite sides of the first pixel circuit column Z1. In the row direction, the two third data signal lines 303 connected to the second pixel circuit column Z2 are respectively located on opposite sides of the second pixel circuit column Z2.

[0443] Specifically, such as Figure 58 As shown, the first pixel circuit column Z1 is connected to a first data signal line 301 and a second data signal line 302. In the row direction, the first data signal line 301 and the second data signal line 302 are located on opposite sides of the first pixel circuit column Z1. On the one hand, in the row direction, the first data signal line 301 and the second data signal line 302 are spaced a certain distance from the first pixel circuit column Z1. This prevents parasitic capacitance from forming between the first data signal line 301 and the second data signal line 302 and the metal film layers of the pixel circuits 10 in the first pixel circuit column Z1, thereby reducing the impact of the first data signal line 301 and the second data signal line 302 on the performance of the pixel circuits 10. On the other hand, in the row direction, the first data signal line 301 and the second data signal line 302 can be spaced a large distance apart, thereby reducing mutual interference of data signals between the first data signal line 301 and the second data signal line 302.

[0444] Similarly, the first pixel circuit column Z1 is connected to two corresponding third data signal lines 303. In the row direction, the two third data signal lines 303 are located on opposite sides of the second pixel circuit column Z2. On the one hand, in the row direction, the two third data signal lines 303 are spaced a certain distance from the second pixel circuit column Z2. This prevents the formation of parasitic capacitance between the two third data signal lines 303 and the various metal film layers of the pixel circuits 10 in the second pixel circuit column Z2, thereby reducing the impact of the auxiliary signal line FIAA and the third data signal line 303 on the performance of the pixel circuits 10. On the other hand, in the row direction, the two third data signal lines 303 can be spaced a large distance apart, thereby reducing mutual interference of data signals between the two third data signal lines 303.

[0445] For example, Figure 59 A schematic diagram of another pixel circuit structure provided by an embodiment of the present invention is shown in FIG. Figure 59 As shown, the pixel circuit 10 may include a first light emission control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initialization reset transistor T5, a second light emission control transistor T6, an anode reset transistor T7 and a storage capacitor Cst.

[0446] Among them, the connection relationship and function of the first light-emitting control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initialization reset transistor T5, the second light-emitting control transistor T6, the anode reset transistor T7 and the storage capacitor Cst can be referred to the above embodiment and will not be repeated here.

[0447] Figure 60 The embodiment of the present invention provides a drive cycle to Figure 59 The signal timing diagram of the pixel circuit shown in Figure 59 and Figure 60 As shown, the operation process of the pixel circuit 10 may include a pre-stage t10 and a light-emitting stage t20. The pre-stage t10 is a stage in which the light-emitting element 20 does not emit light, and the light-emitting stage t20 is a stage in which the light-emitting element 20 emits light. In some cases, the pre-stage t10 and the light-emitting stage t20 may be performed sequentially.

[0448] The specific meanings of the pre-stage t10 and the light-emitting stage t20 may be referred to the above embodiments and will not be described again here.

[0449] Continue to refer Figure 59 and Figure 60 Optionally, the pre-phase t10 of the pixel circuit 10 may include a reset phase t12.

[0450] In the reset phase t12, the first scanning signal S1N is a valid low-level signal, so that the initialization reset transistor T5 is turned on, and the first reference signal VREF1 is transmitted to the gate of the driving transistor T3 (i.e., the first node N1) through the turned-on initialization reset transistor T5, thereby resetting the gate of the driving transistor T3. At this time, the gate potential of the driving transistor T3 is consistent with the potential of the first reference signal VREF1, so as to prevent the data signal of the previous frame carried on the gate of the driving transistor T3 from affecting the writing of the data signal of the next frame.

[0451] Continue to refer Figure 59 and Figure 60 Optionally, the pre-stage t10 of the pixel circuit 10 may further include a data writing stage t13.

[0452] In the data writing phase t13, the third scanning signal SP and the second scanning signal S2N are both active low-level pulses, turning on the data writing transistor T2 and the threshold compensation transistor T4. Simultaneously, the gate potential of the driving transistor T3 is kept consistent with the first reference signal VREF1, and the driving transistor T3 is also turned on. The data signal passes through the data writing transistor T2, the driving transistor T3, and the threshold compensation transistor T4, and is applied to the gate of the driving transistor T3 (i.e., the first node N1). The potential of the first node N1 is gradually increased until the driving transistor T3 is turned off. When the driving transistor T3 is turned off, the gate potential of the driving transistor T3 is Vdata-|Vth|, where Vdata is the voltage of the data signal DATA and |Vth| is the threshold voltage of the driving transistor T3.

[0453] Continue to refer Figure 59 and Figure 60 Optionally, after the data writing phase t13 ends, the display panel may enter the light emitting phase t20.

[0454] In the light-emitting stage t20, the light-emitting control signal EM is a low-level active pulse, and the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are turned on. Due to the conduction of the first light-emitting control transistor T1, the positive power supply voltage PVDD is transmitted to the first end of the driving transistor T3 (i.e., the second node N2). Then, the voltage difference between the first end of the driving transistor T3 (i.e., the second node N2) and its gate (i.e., the first node N1) is PVDD-(Vdata-|Vth|), so that the driving current generated by the driving transistor T3 is K*(Vdata-PVDD). 2, K is a coefficient related to the size and material of the driving transistor T3. In this way, the driving current generated by the driving transistor T3 is independent of its own threshold voltage |Vth|. The driving current is transmitted to the anode of the light-emitting element 20 through the turned-on second light-emitting control transistor T6, causing the light-emitting element 20 to emit light.

[0455] Continue to refer Figure 59 and Figure 60 Optionally, the pre-phase t10 of the pixel circuit 10 may include an initialization phase t11.

[0456] In the initialization phase t11, the fourth scan signal SPX is a valid pulse of a low level, so that the anode reset transistor T7 is turned on, and the second reference signal VREF2 is transmitted to the anode of the light-emitting element 20 through the anode reset transistor T7 to initialize the anode of the light-emitting element 20, thereby preventing the driving current provided to the anode of the light-emitting element 20 in the previous frame from affecting the display brightness of the light-emitting element 20 in the next frame.

[0457] Among them, the transistors in the pixel circuit 10 can all be low-temperature polysilicon (LTPS) transistors. Low-temperature polysilicon transistors have the advantages of high switching speed, high carrier mobility and low power. Oxide transistors have the advantages of low leakage current, but are not limited to this.

[0458] Furthermore, the fourth scan signal SPX, the second scan signal S2N, and the third scan signal SP may be the same scan signal, thereby reducing the number of scan signal lines and lowering costs.

[0459] It can be understood that the above is only an illustrative description of the types of transistors in the pixel circuit 10 and the corresponding driving process. In the embodiment of the present invention, when the types of transistors in the pixel circuit 10 change, a driving process similar to the above can be achieved by changing the signal received by the gate of each transistor, which will not be repeated here.

[0460] For example, Figure 61 A schematic diagram of a film structure of another display panel provided by an embodiment of the present invention is shown in FIG. Figure 61 As shown, taking the LTPS display panel as an example, a first semiconductor layer POLY, a first metal layer GAT, a second metal layer MC, a fourth metal layer SD1, a fifth metal layer SD2, a sixth metal layer SD3 and an anode layer RE are stacked on one side of the base substrate 60, and an insulating layer 70 can be set between any two adjacent conductive film layers to avoid short circuit between the two adjacent conductive film layers.

[0461] Figure 62 for Figure 61A schematic structural diagram of a first semiconductor layer in a display panel shown; Figure 63 for Figure 61 A schematic structural diagram of a first metal layer in a display panel shown; Figure 64 for Figure 61 A schematic structural diagram of a second metal layer in a display panel shown; Figure 65 for Figure 61 A schematic structural diagram of a fourth metal layer in a display panel shown; Figure 66 for Figure 61 A schematic structural diagram of a fifth metal layer in a display panel shown; Figure 67 for Figure 61 A schematic structural diagram of a sixth metal layer in a display panel shown; Figure 68 for Figure 61 A schematic structural diagram of an anode layer in a display panel shown; Figure 69 for Figure 61 A schematic diagram of a stacked structure of all film layers in a display panel shown, specifically a schematic diagram of the stacked structure from the first semiconductor layer to the anode layer;

[0462] Figure 70 for Figure 61 Schematic diagram of the film structure of a pixel circuit in the display panel shown in FIG. To clearly illustrate the structure of the pixel circuit, Figure 71 for Figure 61 The diagram shown is a partial film layer structure diagram of a pixel circuit in a display panel, specifically a schematic diagram of the stacked structure from the first semiconductor layer to the fifth metal layer.

[0463] in, Figures 61-71 The film structure shown can correspond to Figure 59 In the pixel circuit 10 shown in the figure, the first light emission control transistor T1, the data writing transistor T2, the driving transistor T3, the threshold compensation transistor T4, the initialization reset transistor T5, the second light emission control transistor T6 and the anode reset transistor T7 in the pixel circuit 10 are all low temperature polysilicon (LTPS) transistors.

[0464] For example, Figures 59-71 As shown, active layers of the first emission control transistor T1 , the data writing transistor T2 , the driving transistor T3 , the threshold compensation transistor T4 , the initialization reset transistor T5 , the second emission control transistor T6 and the anode reset transistor T7 may be located in the first semiconductor layer POLY.

[0465] The driving transistor T3 , the threshold compensation transistor T4 , the initialization reset transistor T5 , the second light emission control transistor T6 , the gate 2 g of the anode reset transistor T7 , and the first plate C1 of the storage capacitor Cst may be located in the first metal layer GAT.

[0466] The first metal layer GAT may further include a first scan signal line s1n, a third scan signal line sp, a fourth scan signal line spx, a second scan signal line s2n, and a light-emission control signal line em extending in the row direction. The first scan signal line s1n is electrically connected to the gate of the initialization reset transistor T5 for transmitting a first scan signal S1N; the third scan signal line sp is electrically connected to the gate of the data write transistor T2 for transmitting a third scan signal SP; the fourth scan signal line spx is electrically connected to the gate of the anode reset transistor T7 for transmitting a fourth scan signal SPX; the second scan signal line s2n is electrically connected to the gate of the threshold compensation transistor T4 for transmitting a second scan signal S2N; and the light-emission control signal line em is electrically connected to the gates of the first and second light-emission control transistors T1 and T6 for transmitting a light-emission control signal EM.

[0467] Furthermore, the third scanning signal line sp, the fourth scanning signal line spx and the second scanning signal line s2n may be the same scanning signal line, which can reduce the number of scanning signal lines and is beneficial to increasing the light transmission area of ​​the display panel.

[0468] The second metal layer MC may include a second plate C2 of the storage capacitor Cst, and a first reference signal line vref1 and a second reference signal line vref2 extending in the row direction. The first reference signal line vref1 is electrically connected to the initialization reset transistor T5 for transmitting a first reference signal VREF1. The second reference signal line vref2 is electrically connected to the anode reset transistor T7 for transmitting a second reference signal VREF2.

[0469] The fourth metal layer SD1 may include a third power signal line P3 extending along a column direction, wherein the third power signal line P3 is used to transmit a positive power voltage PVDD.

[0470] The fifth metal layer SD2 may include data signal lines 30 extending along a column direction, and the data signal lines 30 are used to transmit data signals DATA.

[0471] The sixth metal layer SD3 may include a first power signal line P1 extending along the row direction, wherein the first power signal line P1 extending along the row direction is electrically connected to the third power signal line P3 extending along the column direction in the fourth metal layer SD1, and can form a grid routing structure, which is beneficial to reducing line resistance, thereby reducing the voltage drop of the positive power supply voltage PVDD, and ensuring the stability of the positive power supply voltage PVDD.

[0472] The anode layer RE may include an anode 111 of the light emitting element.

[0473] It should be noted that the specific film layer settings of the display panel can be adaptively adjusted according to actual needs, such as adding or removing some film layers, and the embodiments of the present invention do not specifically limit this.

[0474] Further, if Figures 62-71 As shown, the first data signal line 301 connected to the first pixel circuit column Z1 and the second data signal line 302 connected to the second pixel circuit column Z2 are located on opposite sides of the first pixel circuit column Z1, respectively. The two third data signal lines 303 connected to the second pixel circuit column Z2 are located on opposite sides of the second pixel circuit column Z2, respectively. On the one hand, in the row direction, a certain distance is provided between the data signal lines 30 and the pixel circuits 10. This prevents parasitic capacitance from forming between the data signal lines 30 and the various metal film layers of the pixel circuits 10, thereby reducing the impact of the data signal lines 30 on the performance of the pixel circuits 10. On the other hand, in the row direction, a larger distance can be provided between adjacent data signal lines 30, thereby reducing mutual interference of data signals between adjacent data signal lines 30.

[0475] Figure 72 A schematic diagram of a film structure of a pixel circuit provided by an embodiment of the present utility model is shown in FIG. Figure 73 A schematic diagram of a film structure of another pixel circuit provided by an embodiment of the present invention is shown in FIG. Figure 46 、 Figure 72 and Figure 73 As shown, the display area AA optionally includes a first display area AA1 and a second display area AA2. Along the row direction, the first display area AA1 is located on at least one side of the second display area AA2. The display panel also includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2 and are electrically connected to the data signal lines 30 in the first display area AA1.

[0476] The auxiliary signal lines FIAA and the data signal lines 30 are located in different film layers.

[0477] or,

[0478] The auxiliary signal lines FIAA and the data signal lines 30 are located in the same film layer.

[0479] The positional relationship between the first display area AA1 and the second display area AA2, and the distribution and connection structure of the auxiliary signal lines FIAA may refer to the above embodiments and will not be described in detail here.

[0480] Further, if Figure 72 As shown, the auxiliary signal line FIAA and the data signal line 30 can be located in the same film layer, which can reduce the number of film layers, thereby facilitating a reduction in the thickness of the display panel and achieving a lightweight and thin design.

[0481] For example, Figure 72 As shown, the auxiliary signal line FIAA and the data signal line 30 may both be located in the sixth metal layer SD3, but the present invention is not limited thereto.

[0482] Continue to refer Figure 73 Optionally, the auxiliary signal line FIAA and the data signal line 30 can be located in different film layers, which helps to increase the distance between the auxiliary signal line FIAA and the data signal line 30, reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and thereby reduce the mutual interference of data signals between the auxiliary signal line FIAA and the data signal line 30.

[0483] For example, Figure 73 As shown, the data signal line 30 may be located in the sixth metal layer SD3, and the auxiliary signal line FIAA may be located in the fifth metal layer SD2, but the present invention is not limited thereto.

[0484] Continue to refer Figure 72 Optionally, the display panel provided by an embodiment of the present invention further includes a plurality of third power signal lines P3, extending in the column direction and arranged in the row direction. A first pixel circuit column Z1 corresponds to an auxiliary signal line FIAA and a third power signal line P3, and the auxiliary signal line FIAA and the third power signal line P3 are located between the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1. A second pixel circuit column Z2 corresponds to an auxiliary signal line FIAA and a third power signal line P3, and the auxiliary signal line FIAA and the third power signal line P3 are located between the two third data signal lines 303 connected to the second pixel circuit column Z2.

[0485] Specifically, such as Figure 72 As shown, the third power signal line P3 extends along the column direction and is arranged along the row direction, and is used to transmit a positive power voltage PVDD with a fixed voltage.

[0486] In this embodiment, if Figure 72 As shown, there is a large distance between the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1, thereby providing sufficient arrangement space for the auxiliary signal line FIAA.

[0487] Among them, one first pixel circuit column Z1 corresponds to one auxiliary signal line FIAA and one third power signal line P3, so as to increase the number of auxiliary signal lines FIAA, thereby increasing the setting area of ​​the first display area AA1 and achieving a narrow frame effect.

[0488] In this embodiment, by setting the auxiliary signal line FIAA between the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1, it is convenient to increase the distance between the auxiliary signal line FIAA and the data signal line 30, reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and thereby reduce the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0489] At the same time, the third power signal line P3 is also arranged between the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1. The third power signal line P3 can provide a fixed positive power supply voltage PVDD, thereby serving as a shielding layer to reduce mutual interference of data signals between the first data signal line 301 and the second data signal line 302 connected to the first pixel circuit column Z1.

[0490] Continue to refer Figure 72 Optionally, a column of second pixel circuits Z2 corresponds to an auxiliary signal line FIAA and a third power signal line P3 to increase the number of auxiliary signal lines FIAA, thereby increasing the setting area of ​​the first display area AA1 and facilitating a narrow frame effect.

[0491] In this embodiment, by setting the auxiliary signal line FIAA between the two third data signal lines 303 connected to the second pixel circuit column Z2, it is convenient to increase the distance between the auxiliary signal line FIAA and the third data signal line 303, reduce the coupling capacitance between the auxiliary signal line FIAA and the third data signal line 303, and thereby reduce the mutual interference of the data signals between the auxiliary signal line FIAA and the third data signal line 303.

[0492] At the same time, the third power signal line P3 is also set between the two third data signal lines 303 connected to the second pixel circuit column Z2. The third power signal line P3 can provide a fixed positive power supply voltage PVDD, thereby serving as a shielding layer to reduce mutual interference of data signals between the two third data signal lines 303 connected to the second pixel circuit column Z2.

[0493] Figure 74 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 74As shown, optionally, a first pixel circuit column Z1 corresponds to an auxiliary signal line FIAA, and a second pixel circuit column Z2 corresponds to an auxiliary signal line FIAA. The auxiliary signal line FIAA is located between two data signal lines 30 between the adjacent first pixel circuit column Z1 and second pixel circuit column Z2.

[0494] Specifically, such as Figure 74 As shown, a first pixel circuit column Z1 corresponds to an auxiliary signal line FIAA, and a second pixel circuit column Z2 corresponds to an auxiliary signal line FIAA, so as to increase the number of auxiliary signal lines FIAA. This can increase the setting area of ​​the first display area AA1, which is conducive to achieving a narrow frame effect.

[0495] Further, if Figure 74 As shown, the auxiliary signal line FIAA is located between the two data signal lines 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2. In this way, the auxiliary signal line FIAA and the data signal line 30 can be placed together, so that the parasitic capacitance between the auxiliary signal line FIAA and the data signal line 30 and each metal film layer or signal node in the pixel circuit 10 is at a similar level, which helps to reduce the loss difference between the data signals transmitted on the auxiliary signal line FIAA and the data signal line 30, and improve display uniformity.

[0496] Figure 75 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 75 As shown, optionally, multiple columns of first pixel circuit columns Z1 and multiple columns of second pixel circuit columns Z2 are divided into multiple third pixel circuit column groups G3, and the third pixel circuit column group G3 includes the first pixel circuit column Z1 and the second pixel circuit column Z2 adjacent to each other along the row direction. The third pixel circuit column group G3 corresponds to three auxiliary signal lines FIAA, and the auxiliary signal line FIAA is located between any two adjacent data signal lines 30.

[0497] The structures of the first pixel circuit column Z1 and the second pixel circuit column Z2 in the third pixel circuit column group G3 may refer to the above embodiment and will not be described in detail here.

[0498] Specifically, such as Figure 75 As shown, two columns of pixel circuits 10 can correspond to three auxiliary signal lines FIAA. At this time, three auxiliary signal lines FIAA are correspondingly set for a third pixel circuit column group G3 to increase the number of auxiliary signal lines FIAA. In this way, the setting area of ​​the first display area AA1 can be increased, which is conducive to achieving a narrow frame effect.

[0499] Further, if Figure 75As shown, four data signal lines 30 are correspondingly arranged in the third pixel circuit column group G3. Along the row direction, three auxiliary signal lines FIAA are respectively located between two adjacent data signal lines 30. Then, in the direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA can not overlap with the data signal line 30, which can further reduce the coupling capacitance between the auxiliary signal line FIAA and the data signal line 30, and thus reduce the mutual interference of the data signals between the auxiliary signal line FIAA and the data signal line 30.

[0500] Meanwhile, in the third pixel circuit column group G3, the three auxiliary signal lines FIAA can be evenly distributed in the gaps between the four data signal lines 30, thereby reducing visual interference caused by uneven light reflection from the auxiliary signal lines FIAA and improving the overall visual effect of the display panel.

[0501] Figure 76 A schematic diagram of a film structure of another pixel circuit provided by an embodiment of the present invention is shown in FIG. Figure 76 As shown, optionally, a column of first pixel circuit columns Z1 corresponds to one or two auxiliary signal lines FIAA, and a column of second pixel circuit columns Z2 corresponds to one or two auxiliary signal lines FIAA, and in a direction perpendicular to the plane where the display panel is located, the auxiliary signal lines FIAA and the data signal lines 30 at least partially overlap.

[0502] Specifically, such as Figure 76 As shown, a first pixel circuit column Z1 may correspond to one or two auxiliary signal lines FIAA, and a second pixel circuit column Z2 may correspond to one or two auxiliary signal lines FIAA, which is conducive to achieving a narrow frame effect.

[0503] Continue to refer Figure 76 The auxiliary signal line FIAA and the data signal line 30 are located in different film layers, and in the direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA and the data signal line 30 at least partially overlap. This arrangement can reduce the overall blocking area of ​​the auxiliary signal line FIAA and the data signal line 30 in the thickness direction of the display panel, thereby increasing the light transmittance area of ​​the display panel.

[0504] It should be noted that Figure 76 In the description, an example is given in which a first pixel circuit column Z1 corresponds to two auxiliary signal lines FIAA, and a second pixel circuit column Z2 corresponds to two auxiliary signal lines FIAA, but the invention is not limited thereto.

[0505] also, Figure 76 In the figure, the auxiliary signal lines FIAA and the data signal lines 30 are arranged in a one-to-one overlapping manner as an example, but the present invention is not limited thereto.

[0506] Continue to refer Figure 46 and Figure 76 Optionally, the display area AA includes a first display area AA1 and a second display area AA2. Along the row direction, the first display area AA1 is located on at least one side of the second display area AA2. The display panel also includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2, and the auxiliary signal lines FIAA are electrically connected to the data signal lines 30 in the first display area AA1.

[0507] A first pixel circuit column Z1 corresponds to at least two auxiliary signal lines FIAA, and a second pixel circuit column Z2 corresponds to at least two auxiliary signal lines FIAA.

[0508] The positional relationship between the first display area AA1 and the second display area AA2, and the connection structure of the auxiliary signal line FIAA may refer to the above embodiment and will not be described in detail here.

[0509] In this embodiment, if Figure 46 and Figure 76 As shown, a first pixel circuit column Z1 corresponds to at least two auxiliary signal lines FIAA, and a second pixel circuit column Z2 corresponds to at least two auxiliary signal lines FIAA, so as to increase the number of auxiliary signal lines FIAA. This can increase the setting area of ​​the first display area AA1, which is conducive to achieving a narrow frame effect.

[0510] It should be noted that Figure 76 In the description, an example is given in which a first pixel circuit column Z1 corresponds to two auxiliary signal lines FIAA, and a second pixel circuit column Z2 corresponds to two auxiliary signal lines FIAA, but the invention is not limited thereto.

[0511] In other embodiments, a first pixel circuit column Z1 may be provided with more auxiliary signal lines FIAA, and a second pixel circuit column Z2 may be provided with more auxiliary signal lines FIAA, which is not specifically limited in the embodiment of the present invention.

[0512] Optionally, the number of auxiliary signal lines FIAA corresponding to a first pixel circuit column Z1 is less than or equal to 4, and the number of auxiliary signal lines FIAA corresponding to a second pixel circuit column Z2 is less than or equal to 4.

[0513] Among them, as can be seen from the above embodiments, the number of auxiliary signal lines FIAA corresponding to a column of first pixel circuit column Z1 can be one, two, three or four, and the number of auxiliary signal lines FIAA corresponding to a column of second pixel circuit column Z2 can be one, two, three or four. In this way, while achieving a narrow bezel effect, an excessive number of auxiliary signal lines FIAA can be avoided, thereby effectively controlling the mutual interference between the auxiliary signal lines FIAA and the data signal lines 30, and at the same time, it also helps to ensure that the display panel has sufficient light-transmitting area.

[0514] Figure 77 A schematic diagram of the structure of another display panel provided by an embodiment of the present utility model is shown in FIG. Figure 77 As shown, the display panel provided in this embodiment of the present invention optionally further includes a plurality of third power signal lines P3, which extend along the column direction and are arranged along the row direction. A first pixel circuit column Z1 corresponds to a third power signal line P3, and a second pixel circuit column Z2 corresponds to a third power signal line P3. Along the row direction, the third power signal line P3 is located between two data signal lines 30 between adjacent first pixel circuit columns Z1 and second pixel circuit columns Z2.

[0515] Specifically, such as Figure 77 As shown, the third power signal line P3 extends along the column direction and is arranged along the row direction, and is used to transmit a positive power voltage PVDD with a fixed voltage.

[0516] In this embodiment, if Figure 77 As shown, the third power signal line P3 is arranged between the two data signal lines 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2. The third power signal line P3 can provide a fixed positive power supply voltage PVDD, thereby serving as a shielding layer to reduce signal interference between the data signal line 30 connected to the first pixel circuit column Z1 and the data signal line 30 connected to the second pixel circuit column Z2.

[0517] Continue to refer Figures 69-71 Optionally, in a direction perpendicular to the plane of the display panel, the third power signal line P3 and the data signal line 30 are located in different film layers, and the third power signal line P3 at least partially overlaps with the two data signal lines 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2.

[0518] Specifically, such as Figures 69-71As shown, by arranging the third power signal line P3 and the data signal line 30 in different film layers, it is beneficial to increase the setting space of the third power signal line P3, thereby increasing the setting area of ​​the third power signal line P3, which is beneficial to reducing the line resistance, and further reducing the signal voltage drop on the third power signal line P3, thereby ensuring the stability of the positive power supply voltage PVDD.

[0519] For example, Figures 69-71 As shown, the data signal line 30 may be located in the fifth metal layer SD2 , and the third power signal line P3 may be located in the fourth metal layer SD1 , but the present invention is not limited thereto.

[0520] Further, if Figures 69-71 As shown, in a direction perpendicular to the plane where the display panel is located, the third power signal line P3 at least partially overlaps with the two data signal lines 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2. The third power signal line P3 can provide a fixed positive power supply voltage PVDD, thereby serving as a shielding layer. While reducing signal interference between the data signal line 30 connected to the first pixel circuit column Z1 and the data signal line 30 connected to the second pixel circuit column Z2, it can also reduce signal interference between the data signal line 30 and other film layers.

[0521] Figure 78 A schematic diagram of a film structure of another pixel circuit provided by an embodiment of the present invention is shown in FIG. Figure 46 and Figure 78 As shown, the display area AA optionally includes a first display area AA1 and a second display area AA2. Along the row direction, the first display area AA1 is located on at least one side of the second display area AA2. The display panel also includes a plurality of auxiliary signal lines FIAA, which extend along the column direction and are arranged along the row direction. The auxiliary signal lines FIAA are at least partially located in the second display area AA2 and are electrically connected to the data signal lines 30 in the first display area AA1.

[0522] The auxiliary signal line FIAA and the third power signal line P3 are located in different film layers.

[0523] In a direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA at least partially overlaps with the third power signal line P3.

[0524] The positional relationship between the first display area AA1 and the second display area AA2, and the connection structure of the auxiliary signal line FIAA may refer to the above embodiment and will not be described in detail here.

[0525] In this embodiment, if Figure 46 and Figure 78As shown, by arranging the third power signal line P3 and the auxiliary signal line FIAA in different film layers, it is beneficial to increase the setting space of the third power signal line P3, thereby increasing the setting area of ​​the third power signal line P3, which is beneficial to reducing the line resistance, and further reducing the signal voltage drop on the third power signal line P3, thereby ensuring the stability of the positive power supply voltage PVDD.

[0526] Further, if Figure 46 and Figure 78 As shown, in a direction perpendicular to the plane where the display panel is located, the auxiliary signal line FIAA is set to at least partially overlap with the third power signal line P3. The third power signal line P3 can provide a fixed positive power voltage PVDD, thereby serving as a shielding layer to reduce signal interference between the auxiliary signal line FIAA and other film layers.

[0527] Continue to refer Figures 69-71 Optionally, the light-emitting element 20 includes a red light-emitting element 20R, a blue light-emitting element 20B and a green light-emitting element 20G. In a direction perpendicular to the plane of the display panel, the red light-emitting element 20R, the green light-emitting element 20G and the blue light-emitting element 20B at least partially overlap with the third power signal line P3 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2.

[0528] Specifically, the inventors discovered through research that, in a direction perpendicular to the plane of the display panel, there are traces with smaller line widths in the film layer below the light-emitting element 20, causing the anode 111 located above the traces to bulge upward, affecting the flatness of the anode 111, and further causing the light-emitting layer 112 above the anode 111 to be uneven. As a result, when the display panel is viewed at the same tilt angle in different directions, there are differences in the brightness of the light-emitting layer 112, resulting in inconsistent color deviations at the same tilt angle in different directions, that is, there is a problem of inconsistent color deviations in four directions, which affects the display effect of the display panel.

[0529] In this embodiment, since the third power signal line P3 usually has a larger line width, the red light-emitting element 20R, the green light-emitting element 20G and the blue light-emitting element 20B are all arranged to at least partially overlap with the third power signal line P3 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2, which is beneficial to improving the flatness of the anode 111, and thereby reducing the brightness difference of the organic light-emitting layer when the display panel is viewed at the same tilt angle in different directions, reducing the color deviation difference under the same tilt angle viewing angle in different directions, improving the problem of inconsistent color deviation in four directions, and improving the display effect of the display panel.

[0530] Continue to refer Figures 69-71Optionally, the light-emitting elements 20 include a red light-emitting element 20R, a blue light-emitting element 20B, and a green light-emitting element 20G. In a direction perpendicular to the plane of the display panel, the red light-emitting element 20R, the green light-emitting element 20G, and the blue light-emitting element 20B at least partially overlap with the data signal line 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2.

[0531] Specifically, such as Figures 69-71 As shown, in the direction perpendicular to the plane where the display panel is located, the red light-emitting element 20R, the green light-emitting element 20G and the blue light-emitting element 20B all at least partially overlap with the data signal line 30 between the adjacent first pixel circuit column Z1 and the second pixel circuit column Z2, which can reduce the overall blocking area of ​​the data signal line 30 and the light-emitting element 20 in the thickness direction of the display panel, thereby helping to increase the light-transmitting area of ​​the display panel.

[0532] Continue to refer Figures 59-71 Optionally, the pixel circuit 10 further includes a driving transistor T3, a threshold compensation transistor T4, and a shielding layer 80. The gate of the driving transistor T3 and the threshold compensation transistor T4 are connected to the first node N1. At least a portion of the shielding layer 80 is located between the first node N1 and the data signal line 30 in a direction parallel to the plane of the display panel.

[0533] The connection structure and function of the driving transistor T3 and the threshold compensation transistor T4 may refer to the above embodiments, and the embodiments of the present invention do not specifically limit this.

[0534] It can be understood that the potential of the gate of the driving transistor T3 (i.e., the first node N1) determines the size of the driving current formed when it is turned on, and the size of the driving current can determine the brightness of the light-emitting element 20. Therefore, the accuracy and stability of the potential of the first node N1 are crucial to the display effect of the display panel.

[0535] In this embodiment, a shielding layer 80 is arranged between the first node N1 and the data signal line 30 in a direction parallel to the plane where the display panel is located, so as to reduce the signal interference between the first node N1 and the data signal line 30 through the shielding layer 80, improve the accuracy and stability of the potential of the first node N1, and thus help improve the display effect of the display panel.

[0536] The shape of the shielding layer 80 can be set according to actual needs, and the embodiment of the present invention does not make any specific limitation on this.

[0537] Continue to refer Figures 59-71Optionally, in a direction perpendicular to the plane of the display panel, the shielding layer 80 is located between the active layer of the driving transistor T3 and the data signal line 30, and the shielding layer 80 and the data signal line 30 at least partially overlap.

[0538] Specifically, such as Figures 59-71 As shown, in a direction perpendicular to the plane where the display panel is located, by providing a shielding layer 80 between the active layer of the driving transistor T3 and the data signal line 30, and the shielding layer 80 and the data signal line 30 at least partially overlap, the shielding layer 80 can play a shielding role in the direction perpendicular to the plane where the display panel is located, thereby further reducing the signal interference between the first node N1 and the data signal line 30, improving the accuracy and stability of the potential of the first node N1, and further facilitating the improvement of the display effect of the display panel.

[0539] Among them, such as Figures 59-71 As shown, the shielding layer 80 may be disposed on the second metal layer MC, but is not limited thereto.

[0540] Optionally, a fixed voltage is applied to the shielding layer 80 .

[0541] By applying a fixed voltage to the shielding layer 80 so that the voltage on the shielding layer 80 is constant, the influence of the shielding layer 80 on the pixel circuit 10 can be reduced.

[0542] At the same time, the shielding layer 80 can also shield the signal lines and signal nodes that have overlapping areas with it, thereby helping to reduce mutual interference between the signal lines and signal nodes in the pixel circuit 10 and improve the driving performance of the pixel circuit 10.

[0543] Continue to refer Figures 59-71 、 Figure 78 Optionally, the display panel provided by the embodiment of the present invention further includes a plurality of third power signal lines P3, the plurality of third power signal lines P3 extend along the second direction Y and are arranged along the first direction X, the first direction X intersects with the second direction Y, and the shielding layer 80 is electrically connected to the third power signal lines P3.

[0544] The third power signal line P3 is used to provide a positive power voltage PVDD for the pixel circuit 10 . The positive power voltage PVDD is a direct current signal, not an alternating current (AC) signal.

[0545] Figures 59-71 、 Figure 78 As shown, in this embodiment, the shielding layer 80 is electrically connected to the third power signal line P3, and a constant voltage can be provided to the shielding layer 80 through the third power signal line P3, thereby reducing the number of signal lines and facilitating an increase in the light transmission area of ​​the display panel.

[0546] At the same time, after the third power signal line P3 is electrically connected to the shielding layer 80, the routing area of ​​the third power signal line P3 is increased, thereby reducing the resistance of the third power signal line P3 and further reducing the voltage drop (IR drop) on the third power signal line P3, which helps to improve display uniformity.

[0547] It should be noted that the third power signal line P3 and the shielding layer 80 can be connected in the display area AA or in the non-display area NAA, or can be electrically connected through other wiring. The embodiment of the present utility model does not specifically limit the method of electrical connection.

[0548] Figure 79 for Figure 24 A schematic diagram of a laminated structure of a portion of film layers in a display panel is shown, specifically a schematic diagram of the laminated structure from the fifth metal layer to the anode layer; Figure 80 for Figure 61 Schematic diagram of a laminated structure of a portion of film layers in a display panel shown, specifically a schematic diagram of the laminated structure from the fourth metal layer to the anode layer; Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 As shown, optionally, the display panel provided by the embodiment of the present invention further includes a plurality of first power signal lines P1, the plurality of first power signal lines P1 extending along a first direction X and arranged along a second direction Y, wherein the first direction X intersects the second direction Y. The plurality of first power signal lines P1 include a first power voltage signal line P11, a second power voltage signal line P12, and a third power voltage signal line P13. The first power voltage signal line P11 is connected to the first pixel circuit 101, the second power voltage signal line P12 is connected to the second pixel circuit 102, and the third power voltage signal line P13 is connected to the third pixel circuit 103. The first power voltage signal line P11 is used to transmit a first power voltage, the second power voltage signal line P12 is used to transmit a second power voltage, and the third power voltage signal line P13 is used to transmit a third power voltage. At least two of the first power voltage, the second power voltage, and the third power voltage are different.

[0549] Specifically, such as Figure 4 、 Figures 24-36 、 Figure 59 、 Figures 61-70 、 Figure 79 and Figure 80As shown, the first power signal line P1 is used to provide a positive power voltage PVDD to the pixel circuit 10, wherein the driving transistor T3 and the light-emitting element 20 in the pixel circuit 10 are connected in series between the first power signal line P1 and the second power signal line P2, the first power signal line P1 transmits the positive power voltage PVDD, and the second power signal line P2 is used to transmit the negative power voltage PVEE, and the positive power voltage PVDD can be greater than the negative power voltage PVEE, wherein the driving current is generated by the potential difference between the first power signal line P1 and the second power signal line P2, thereby driving the light-emitting element 20 to emit light.

[0550] The inventors have found through research that the different materials of the light-emitting layer 112 in the light-emitting elements 20 that emit light of different colors will cause the pixel capacitors of the light-emitting elements 20 that emit light of different colors to have different capacitance values. During the light-emitting stage, the anode 111 and the cathode 113 of the light-emitting element 20 are connected, and the pixel capacitor of the light-emitting element 20 will be charged first. At this time, the anode potential of the light-emitting element 20 gradually rises. When the pixel capacitor of the light-emitting element 20 is full, the voltage across the light-emitting element 20 reaches the turn-on voltage, and the light-emitting element 20 begins to emit light continuously. Among them, the smaller the pixel capacitance of the light-emitting element 20, the smaller the voltage difference between the anode and the cathode when the pixel capacitance is full, and the smaller the turn-on voltage; similarly, the larger the pixel capacitance of the light-emitting element 20, the greater the voltage difference between the anode and the cathode when the pixel capacitance is full, and the greater the turn-on voltage. It can be understood that the turn-on voltage is the voltage across the anode when the pixel capacitance is full, and the light-emitting element 20 begins to emit light when the voltage across the anode reaches the turn-on voltage.

[0551] To ensure that the driving transistors T3 in all color sub-pixels can operate in the saturation region, that is, to ensure that all sub-pixels can reach sufficient power supply voltage to drive the sub-pixels to their maximum brightness, the voltage difference between the positive power supply voltage PVDD and the negative power supply voltage PVEE needs to be able to meet the voltage requirement of the light-emitting element 20 with the highest turn-on voltage among all color sub-pixels. Therefore, for sub-pixels with lower turn-on voltages of the light-emitting element 20, the voltage value of the positive power supply voltage PVDD will be redundant.

[0552] The power consumption power2 of the sub-pixel can satisfy the following formula:

[0553] power2=(PVDD-PVEE)×I;

[0554] Where I is the magnitude of the driving current.

[0555] As can be seen from the above formula, the greater the voltage difference between the positive power supply voltage PVDD and the negative power supply voltage PVEE, the higher the power consumption of the sub-pixel. Therefore, when there is redundancy in the voltage value of the positive power supply voltage PVDD, there will be unnecessary power consumption loss, thereby increasing the power consumption of the display panel.

[0556] Based on the above technical problems, in this embodiment, if Figure 4 、 Figures 24-36 、 Figure 59 、 Figures 61-70 、 Figure 79 and Figure 80 As shown, multiple first power signal lines P1 are divided into a first power voltage signal line P11, a second power voltage signal line P12 and a third power voltage signal line P13, wherein the first power voltage signal line P11 is connected to the first pixel circuit 101, the second power voltage signal line P12 is connected to the second pixel circuit 102, and the third power voltage signal line P13 is connected to the third pixel circuit 103, so as to separately set the first power signal lines P1 connecting sub-pixels of different colors.

[0557] Among them, the first power supply voltage signal line P11 is used to transmit the first power supply voltage to the first pixel circuit 101, the second power supply voltage signal line P12 is used to transmit the second power supply voltage to the second pixel circuit 102, and the third power supply voltage signal line P13 is used to transmit the third power supply voltage to the third pixel circuit 103, and at least two of the first power supply voltage, the second power supply voltage and the third power supply voltage are different, so that the voltage amplitude of the positive power supply voltage PVDD received by the sub-pixels of different colors can be independently set according to the difference in the cross-voltage requirements of the light-emitting elements 20 in the sub-pixels of different colors, so that the positive power supply voltage PVDD received by the sub-pixels of different colors is closer to the cross-voltage requirements of their light-emitting elements 20, thereby reducing the voltage redundancy of the positive power supply voltage PVDD and reducing the power consumption of the display panel.

[0558] Continue to refer Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 Optionally, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B, and a green light emitting element 20G. The first pixel circuit 101 is connected to the red light emitting element 20R, the second pixel circuit 102 is connected to the blue light emitting element 20B, and the third pixel circuit 103 is connected to the green light emitting element 20G.

[0559] The second power voltage VB is greater than the third power voltage VG, and the third power voltage VG is greater than or equal to the first power voltage VR.

[0560] or,

[0561] The second power voltage VB is greater than the first power voltage VR, and the first power voltage VR is greater than or equal to the third power voltage VG.

[0562] Among them, such as Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80As shown, the light-emitting element 20 may include a red light-emitting element 20R that emits red light, a blue light-emitting element 20B that emits blue light, and a green light-emitting element 20G that emits green light to achieve color image display, but is not limited to this. In some embodiments, the light-emitting element 20 may also include a white light-emitting element that emits white light, and the embodiments of the present utility model do not make specific limitations on this.

[0563] In this embodiment, the first pixel circuit 101 is connected to the red light-emitting element 20R, and the first pixel circuit 101 and the red light-emitting element 20R constitute a red sub-pixel. The positive power supply voltage PVDD of the red sub-pixel is provided by the first power supply voltage signal line P11, and the positive power supply voltage PVDD is the first power supply voltage VR.

[0564] The second pixel circuit 102 is connected to the blue light emitting element 20B, and the second pixel circuit 102 and the blue light emitting element 20B constitute a blue sub-pixel. The positive power supply voltage PVDD of the blue sub-pixel is provided by the second power supply voltage signal line P12, and the positive power supply voltage PVDD is the second power supply voltage VB.

[0565] The third pixel circuit 103 is connected to the green light emitting element 20G. The third pixel circuit 103 and the green light emitting element 20G constitute a green sub-pixel. The positive power supply voltage PVDD of the green sub-pixel is provided by the third power supply voltage signal line P13. The positive power supply voltage PVDD is the third power supply voltage VG.

[0566] The inventors further discovered that due to the different materials of the light-emitting layer 112 in the red sub-pixel 20R, the blue light-emitting element 20B, and the green light-emitting element 20G, there will be differences in the turn-on voltages of the red sub-pixel 20R, the blue light-emitting element 20B, and the green light-emitting element 20G, and therefore the cross-voltage requirements of the red sub-pixel 20R, the blue light-emitting element 20B, and the green light-emitting element 20G are different.

[0567] In some embodiments, the cross-voltage requirement value of the blue light-emitting element 20B is the largest, the cross-voltage requirement value of the red sub-pixel 20R is the smallest, and the cross-voltage requirement value of the green light-emitting element 20G is between the cross-voltage requirement value of the blue light-emitting element 20B and the cross-voltage requirement value of the red sub-pixel 20R. At this time, the second power supply voltage VB can be set to be greater than the third power supply voltage VG, and the third power supply voltage VG can be greater than or equal to the first power supply voltage VR, that is, VB>VG≥VR. While ensuring that the cross-voltage requirements for the normal operation of the red sub-pixel 20R, the blue light-emitting element 20B and the green light-emitting element 20G are met, the voltage redundancy of the positive power supply voltage PVDD can be reduced, thereby reducing the power consumption of the display panel.

[0568] In other embodiments, the cross-voltage requirement value of the blue light-emitting element 20B is the largest, the cross-voltage requirement value of the green light-emitting element 20G is the smallest, and the cross-voltage requirement value of the red sub-pixel 20R is between the cross-voltage requirement value of the blue light-emitting element 20B and the cross-voltage requirement value of the green light-emitting element 20G. In this case, the second power supply voltage VB can be set to be greater than the first power supply voltage VR, and the first power supply voltage VR can be greater than or equal to the third power supply voltage VG, that is, VB>VR≥VG. While ensuring that the cross-voltage requirements for the normal operation of the red sub-pixel 20R, the blue light-emitting element 20B and the green light-emitting element 20G are met, the voltage redundancy of the positive power supply voltage PVDD can be reduced, thereby reducing the power consumption of the display panel.

[0569] It should be noted that the magnitude relationship among the second power voltage VB, the third power voltage VG and the first power voltage VR can be adjusted according to the actual display panel structure and requirements, and is not limited to the above embodiment. The embodiment of the present utility model does not make specific limitations on this.

[0570] Continue to refer Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 Optionally, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B, and a green light emitting element 20G. The first pixel circuit 101 is connected to the red light emitting element 20R, the second pixel circuit 102 is connected to the blue light emitting element 20B, and the third pixel circuit 103 is connected to the green light emitting element 20G.

[0571] The first power supply voltage signal line P11 and the third power supply voltage signal line P13 are the same signal line.

[0572] The configuration of the light emitting element 20 and the corresponding pixel circuit 10 may refer to the above embodiment and will not be described in detail here.

[0573] In some display panels, the cross-voltage requirements of the red light emitting element 20R and the green light emitting element 20G may not differ much, so the red light emitting element 20R and the green light emitting element 20G may use the same positive power supply voltage PVDD.

[0574] Specifically, such as Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80As shown, the positive power supply voltage PVDD for the red sub-pixel is provided by the first power supply voltage signal line P11, which is the first power supply voltage VR. The positive power supply voltage PVDD for the green sub-pixel is provided by the third power supply voltage signal line P13, which is the third power supply voltage VG. The first power supply voltage VR and the third power supply voltage VG can be the same. In this case, the first power supply voltage signal line P11 and the third power supply voltage signal line P13 can be set as the same signal line, so that the red and green sub-pixels share the same first power supply signal line P1. This reduces power consumption while also reducing the number of first power supply signal lines P1, thereby improving the light transmittance of the display panel.

[0575] Optionally, the second power supply voltage VB is greater than the first power supply voltage VR, and the first power supply voltage VR is equal to the third power supply voltage VG.

[0576] In which, VB>VG=VR is set. While ensuring that the cross-voltage requirements for normal operation of the red sub-pixel 20R, the blue light-emitting element 20B and the green light-emitting element 20G are met and the power consumption of the display panel is reduced, the first power supply voltage VR and the third power supply voltage VG use the same positive power supply voltage PVDD, which can reduce the number of positive power supply voltages PVDD with different voltage values, thereby simplifying the design of the driving circuit and reducing costs.

[0577] Continue to refer Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 Optionally, the first power supply voltage signal line P11 and the second power supply voltage signal line P12 are alternately arranged along the second direction Y.

[0578] Specifically, such as Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 As shown, by arranging the first power supply voltage signal line P11 and the second power supply voltage signal line P12 alternately along the second direction Y, the first power supply voltage signal line P11 and the second power supply voltage signal line P12 can be evenly distributed in the second direction, thereby facilitating electrical connection between the first power supply voltage signal line P11 and the second power supply voltage signal line P12 and the corresponding pixel circuit 10, ensuring that the pixel circuit 10 corresponding to each color sub-pixel can receive the required positive power supply voltage PVDD.

[0579] Continue to refer Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80Optionally, the display panel provided in an embodiment of the present invention further includes a plurality of third power signal lines P3. The plurality of third power signal lines P3 extend along the second direction Y and are arranged along the first direction X. The third power signal lines P3 and the first power signal lines P1 are located in different film layers. The plurality of third power signal lines P3 include a first power connection signal line P31 and a second power connection signal line P32. The first power connection signal line P31 is electrically connected to at least two first power voltage signal lines P11, and the second power connection signal line P32 is electrically connected to at least two second power voltage signal lines P12.

[0580] Specifically, such as Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 As shown, the plurality of third power signal lines P3 and the plurality of first power signal lines P1 are located in different film layers and are arranged crosswise.

[0581] Furthermore, the plurality of third power signal lines P3 are divided into first power connection signal lines P31 and second power connection signal lines P32 .

[0582] Among them, the first power connection signal line P31 and at least two first power voltage signal lines P11 are electrically connected, so that the first power connection signal line P31 and the first power voltage signal line P11 form a grid routing structure, which is beneficial to reducing line resistance, and thus reducing the voltage drop of the first power voltage, thereby ensuring the stability of the first power voltage.

[0583] Similarly, the second power connection signal line P32 is electrically connected to at least two second power supply voltage signal lines P12, so that the second power connection signal line P32 and the second power supply voltage signal line P12 form a grid routing structure, which is beneficial to reducing line resistance, thereby reducing the voltage drop of the second power supply voltage and ensuring the stability of the first power supply voltage.

[0584] Continue to refer Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 Optionally, the first power connection signal lines P31 and the second power connection signal lines P32 are alternately arranged along the first direction X.

[0585] Specifically, such as Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80As shown, by arranging the first power connection signal line P31 and the second power connection signal line P32 alternately along the first direction X, the first power connection signal line P31 and the second power connection signal line P32 can be evenly distributed in the first direction X, thereby facilitating the electrical connection between the first power connection signal line P31 and the second power connection signal line P32 and the corresponding first power voltage signal line P11 and the second power voltage signal line P12. At the same time, when the first power voltage signal line P11 and the second power voltage signal line P12 are alternately arranged along the second direction Y, the first power connection signal line P31 and the second power connection signal line P32 are alternately arranged along the first direction X, so that the punched connection positions between the first power signal line P1 and the third power signal line P3 can be evenly distributed, thereby improving the morphological uniformity of the display panel, and further improving the overall visual effect of the display panel.

[0586] Continue to refer Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 Optionally, in a direction perpendicular to the plane of the display panel, the third power signal line P3 and the green light emitting element 20G at least partially overlap.

[0587] Among them, since the human eye is most sensitive to green, by setting the third power signal line P3 and the green light-emitting element 20G to at least partially overlap in the direction perpendicular to the plane where the display panel is located, the larger line width of the third power signal line P3 can be used to improve the flatness of the anode 111 of the green light-emitting element 20G, and then when the display panel is viewed at the same tilt angle in different directions, the brightness difference of the green light-emitting element 20G can be reduced, and the color deviation difference under the same tilt angle viewing angle in different directions can be reduced, thereby improving the four-directional color deviation and improving the display effect of the display panel.

[0588] Figure 81 A schematic diagram of the overlapping relationship between a third power signal line and a green light emitting element provided in an embodiment of the present utility model is shown in FIG. Figure 81 As shown, optionally, in the first direction X, the third power signal line P3 includes a first boundary B1 and a second boundary B2 that are opposite to each other, and in the first direction X, the green light-emitting element 20G includes a third boundary B3 and a fourth boundary B4 that are opposite to each other. Along the first direction X, the first boundary B1 and the second boundary B2 are both located between the third boundary B3 and the fourth boundary B4, and the first boundary B1 is located between the second boundary B2 and the third boundary B3. Along the first direction X, the distance between the first boundary B1 and the third boundary B3 is d1, and the distance between the second boundary B2 and the fourth boundary B4 is d2, where d1 = d2.

[0589] Specifically, such as Figure 81As shown, when the line width of the third power signal line P3 is smaller than the length of the green light-emitting element 20G in the first direction X, the first boundary B1 and the second boundary B2 of the third power signal line P3 can be set between the third boundary B3 and the fourth boundary B4 of the green light-emitting element 20G, and in the first direction X, the distance d1 between the first boundary B1 and the third boundary B3 is equal to the distance d2 between the second boundary B2 and the fourth boundary B4. With this arrangement, the central axis of the third power signal line P3 extending in the first direction X can be aligned with the central axis of the green light-emitting element 20G extending in the first direction X along a direction perpendicular to the plane where the display panel is located, thereby improving the positional symmetry between the third power signal line P3 and the green light-emitting element 20G, further reducing the color deviation difference under the same tilt angle viewing angle in different directions, improving the four-directional color deviation, and making the color performance of the display panel at different angles more consistent.

[0590] It should be noted that Figure 81 In the figure, the boundary of the anode 111 of the green light-emitting element 20G is used as the boundary of the green light-emitting element 20G, but it is not limited to this. In other embodiments, the boundary of the light-emitting area of ​​the green light-emitting element 20G can also be used as the boundary of the green light-emitting element 20G. The embodiment of the present invention does not make specific limitations on this.

[0591] Continue to refer Figure 79 Optionally, in a direction perpendicular to the plane where the display panel is located, the third power signal line P3 covers the green light emitting element 20G.

[0592] Among them, by setting a third power signal line P3 to cover the green light-emitting element 20G in a direction perpendicular to the plane where the display panel is located, the flatness of the anode 111 of the green light-emitting element 20G can be further improved, thereby further improving the problem of inconsistent color deviation in four directions and improving the display effect of the display panel.

[0593] Continue to refer Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 Optionally, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B, and a green light emitting element 20G. In a direction perpendicular to the plane of the display panel, the first power signal line P1 and the green light emitting element 20G at least partially overlap.

[0594] Among them, since the human eye is most sensitive to green, by setting the first power signal line P1 and the green light-emitting element 20G to at least partially overlap in a direction perpendicular to the plane where the display panel is located, the larger line width of the first power signal line P1 can be used to improve the flatness of the anode 111 of the green light-emitting element 20G, and then when the display panel is viewed at the same tilt angle in different directions, the brightness difference of the green light-emitting element 20G can be reduced, and the color deviation difference under the same tilt angle viewing angle in different directions can be reduced, the four-directional color deviation can be improved, and the display effect of the display panel can be improved.

[0595] Figure 82 A schematic diagram of the overlapping relationship between a first power signal line and a green light emitting element provided in an embodiment of the present utility model is shown as follows: Figure 82 As shown, optionally, in the second direction Y, the first power signal line P1 includes a fifth boundary B5 and a sixth boundary B6 that are opposite to each other. In the second direction Y, the green light-emitting element 20G includes a seventh boundary B7 and an eighth boundary B8 that are opposite to each other. Along the second direction Y, the fifth boundary B5 and the sixth boundary B6 are both located between the seventh boundary B7 and the eighth boundary B8, and the fifth boundary B5 is located between the sixth boundary B6 and the seventh boundary B7. Along the second direction Y, the distance between the fifth boundary B5 and the seventh boundary B7 is d3, and the distance between the sixth boundary B6 and the eighth boundary B8 is d4, where d3 = d4.

[0596] Specifically, such as Figure 82 As shown, when the line width of the first power signal line P1 is smaller than the length of the green light-emitting element 20G in the second direction Y, the fifth boundary B5 and the sixth boundary B6 of the first power signal line P1 can be set between the seventh boundary B7 and the eighth boundary B8 of the green light-emitting element 20G, and in the second direction Y, the distance d3 between the fifth boundary B5 and the seventh boundary B7 is equal to the distance d4 between the sixth boundary B6 and the eighth boundary B8. With this arrangement, the central axis of the first power signal line P1 extending in the second direction Y can be aligned with the central axis of the green light-emitting element 20G extending in the second direction Y along the direction perpendicular to the plane where the display panel is located, thereby improving the positional symmetry of the first power signal line P1 and the green light-emitting element 20G, further reducing the color deviation difference under the same tilt angle viewing angle in different directions, improving the four-directional color deviation, and making the color performance of the display panel at different angles more consistent.

[0597] It should be noted that Figure 82 In the figure, the boundary of the anode 111 of the green light-emitting element 20G is used as the boundary of the green light-emitting element 20G, but it is not limited to this. In other embodiments, the boundary of the light-emitting area of ​​the green light-emitting element 20G can also be used as the boundary of the green light-emitting element 20G. The embodiment of the present invention does not make specific limitations on this.

[0598] Figure 83 Another schematic diagram of the overlapping relationship between the first power signal line and the green light emitting element provided by the embodiment of the present utility model is as follows: Figure 83 As shown, optionally, the light emitting element 20 includes a red light emitting element 20R, a blue light emitting element 20B and a green light emitting element 20G. In a direction perpendicular to the plane where the display panel is located, the first power signal line P1 covers the green light emitting element 20G.

[0599] Among them, by setting the first power signal line P1 to cover the green light-emitting element 20G in the direction perpendicular to the plane of the display panel, the flatness of the anode 111 of the green light-emitting element 20G can be further improved, thereby further improving the problem of inconsistent color deviation in four directions and improving the display effect of the display panel.

[0600] It should be noted that Figures 24-36 、 Figures 61-70 、 Figure 79 and Figure 80 In the description, the first direction X is taken as the row direction and the second direction Y is taken as the column direction, but the present invention is not limited thereto and the embodiments of the present invention do not make specific limitations on this.

[0601] Continue to refer Figure 33 and Figure 68 Optionally, a plurality of red light-emitting elements 20R and a blue light-emitting element 20B constitute a first virtual quadrilateral Z1, the red light-emitting element 20R is at the first vertex of the first virtual quadrilateral Z1, the blue light-emitting element 20B is at the second vertex of the first virtual quadrilateral Z1, the first vertex and the second vertex are alternated a...

Claims

1. A display panel, characterized in that: comprising a display area, the display area comprising a plurality of pixel circuits arranged in an array, the plurality of pixel circuits comprising a first pixel circuit, a second pixel circuit and a third pixel circuit; The first pixel circuit, the second pixel circuit, and the third pixel circuit are respectively connected to light-emitting elements of different colors; The display panel further comprises a plurality of data signal lines, wherein the plurality of data signal lines comprises a first data signal line, a second data signal line and a third data signal line; The first data signal line is electrically connected to the first pixel circuit, the second data signal line is electrically connected to the second pixel circuit, and the third data signal line is electrically connected to the third pixel circuit.

2. The display panel according to claim 1, wherein: The plurality of pixel circuits form a plurality of first pixel circuit columns, wherein the first pixel circuit columns include the first pixel circuits and the second pixel circuits alternately arranged along a column direction; The plurality of pixel circuits form a plurality of second pixel circuit columns, the second pixel circuit columns including the third pixel circuits arranged along the column direction; the first pixel circuit columns and the second pixel circuit columns are alternately arranged along the row direction; A plurality of data signal lines extend along the column direction and are arranged along the row direction; The first data signal line is electrically connected to the first pixel circuit in the same first pixel circuit column, the second data signal line is electrically connected to the second pixel circuit in the same first pixel circuit column, and the third data signal line is electrically connected to the third pixel circuit in the same second pixel circuit column.

3. The display panel according to claim 2, wherein: The plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, wherein the first pixel circuit column group includes two first pixel circuit columns, and the two first pixel circuit columns are respectively a first group pixel circuit column and a second group pixel circuit column; The first data signal line connected to the first pixel circuit in the first pixel circuit column is a first-group data signal line; the second data signal line connected to the second pixel circuit in the first pixel circuit column is a second-group data signal line; the first data signal line connected to the first pixel circuit in the second pixel circuit column is a third-group data signal line; and the second data signal line connected to the second pixel circuit in the second pixel circuit column is a fourth-group data signal line. In the first pixel circuit column group, the data signal line in the first group is electrically connected to the data signal line in the third group, and the data signal line in the second group is electrically connected to the data signal line in the fourth group; The first pixel circuit connected to the data signal line in the first group and the first pixel circuit connected to the data signal line in the third group are located in different pixel circuit rows, and the second pixel circuit connected to the data signal line in the second group and the second pixel circuit connected to the data signal line in the fourth group are located in different pixel circuit rows.

4. The display panel according to claim 3, wherein: The first pixel circuits and the second pixel circuits are alternately arranged along the row direction; The first pixel circuit column group includes two adjacent first pixel circuit columns.

5. The display panel according to claim 3, wherein: Also includes a non-display area located on at least one side of the display area; In the first pixel circuit column group, the data signal line in the first group and the data signal line in the third group are electrically connected via a first data connection line; the data signal line in the second group and the data signal line in the fourth group are electrically connected via a second data connection line; The first data connection line and the second data connection line are both located in the non-display area.

6. The display panel according to claim 3, wherein: In the first pixel circuit column group, the data signal line in the first group and the data signal line in the third group are electrically connected via a first data connection line; the data signal line in the second group and the data signal line in the fourth group are electrically connected via a second data connection line; The first data connection line and the second data connection line are both located in the display area.

7. The display panel according to claim 3, wherein: Also included are a plurality of data signal output lines and a plurality of gating circuits; The data signal output line includes a first data signal output line and a second data signal output line; The gating circuit includes a first gating circuit and a second gating circuit; In the first pixel circuit column group, the data signal line within the first group and the data signal line within the third group are electrically connected to the same first data signal output line via the first gating circuit, and the first gating circuit is used to transmit the data signal output by the first data signal output line to the data signal line within the first group and the data signal line within the third group in a time-sharing manner; In the first pixel circuit column group, the data signal line in the second group and the data signal line in the fourth group are electrically connected to the same second data signal output line through the second selection circuit, and the second selection circuit is used to transmit the data signal output by the second data signal output line to the data signal line in the second group and the data signal line in the fourth group in a time-sharing manner.

8. The display panel according to claim 7, wherein: The first gating circuit includes a first switching transistor and a second switching transistor, the first switching transistor being connected between the data signal line in the first group and the first data signal output line, and the second switching transistor being connected between the data signal line in the third group and the first data signal output line; The second gating circuit includes a third switching transistor and a fourth switching transistor, the third switching transistor being connected between the data signal line in the second group and the second data signal output line, and the fourth switching transistor being connected between the data signal line in the fourth group and the second data signal output line; The gate of the first switching transistor and the gate of the fourth switching transistor receive a first switching signal; The gate of the second switching transistor and the gate of the third switching transistor receive a second switching signal.

9. The display panel according to claim 2, wherein: The plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, wherein the first pixel circuit column group includes two adjacent first pixel circuit columns, and the two adjacent first pixel circuit columns are respectively a first group pixel circuit column and a second group pixel circuit column; The first data signal line connected to the first pixel circuit in the first pixel circuit column is a first-group data signal line; the second data signal line connected to the second pixel circuit in the first pixel circuit column is a second-group data signal line; the first data signal line connected to the first pixel circuit in the second pixel circuit column is a third-group data signal line; the first data signal line connected to the second pixel circuit in the second pixel circuit column is a fourth-group data signal line; In the row direction, the data signal line within the first group and the data signal line within the second group are located on different sides of the pixel circuit column within the first group, and the data signal line within the third group and the data signal line within the fourth group are located on different sides of the pixel circuit column within the second group.

10. The display panel according to claim 2, wherein: The plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, wherein the first pixel circuit column group includes two first pixel circuit columns, and the two first pixel circuit columns are respectively a first group pixel circuit column and a second group pixel circuit column; The first data signal line connected to the first pixel circuit in the first pixel circuit column is a first-group data signal line; the second data signal line connected to the second pixel circuit in the first pixel circuit column is a second-group data signal line; the first data signal line connected to the first pixel circuit in the second pixel circuit column is a third-group data signal line; and the second data signal line connected to the second pixel circuit in the second pixel circuit column is a fourth-group data signal line. In the first pixel circuit column group, the second intra-group data signal line and the fourth intra-group data signal line are located between the first intra-group data signal line and the third intra-group data signal line.

11. The display panel according to claim 10, wherein: Also includes a non-display area located on at least one side of the display area; In the first pixel circuit column group, the data signal line in the first group and the data signal line in the third group are electrically connected via a first data connection line; the data signal line in the second group and the data signal line in the fourth group are electrically connected via a second data connection line; The first data connection line and the second data connection line are both located in the non-display area; The second data connection line is located on a side of the first data connection line close to the display area.

12. The display panel according to claim 11, wherein: Also includes a plurality of data signal output lines; The data signal output line includes a first data signal output line and a second data signal output line; In the first pixel circuit column group, the first data connection line is electrically connected to the first data signal output line, and the second data connection line is electrically connected to the second data signal output line; The first data connection line and the second data signal output line are located in different film layers.

13. The display panel according to claim 2, wherein: The plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, wherein the first pixel circuit column group includes two first pixel circuit columns, and the two first pixel circuit columns are respectively a first group pixel circuit column and a second group pixel circuit column; The first data signal line connected to the first pixel circuit in the first pixel circuit column is a first-group data signal line; the second data signal line connected to the second pixel circuit in the first pixel circuit column is a second-group data signal line; the first data signal line connected to the first pixel circuit in the second pixel circuit column is a third-group data signal line; and the second data signal line connected to the second pixel circuit in the second pixel circuit column is a fourth-group data signal line. In the first pixel circuit column group, the data signal lines in the first group, the data signal lines in the second group, the data signal lines in the third group, and the data signal lines in the fourth group are sequentially arranged along a row direction.

14. The display panel according to claim 13, wherein: Also includes a non-display area located on at least one side of the display area; In the first pixel circuit column group, the data signal line in the first group and the data signal line in the third group are electrically connected via a first data connection line; the data signal line in the second group and the data signal line in the fourth group are electrically connected via a second data connection line; The first data connection line and the second data connection line are both located in the non-display area; The second data connection line is located on a side of the first data connection line close to the display area, and the second data connection line and the data signal line in the third group are located in a different film layer; or, The first data connection line is located on a side of the second data connection line close to the display area, and the first data connection line and the second group of data signal lines are located in different film layers.

15. The display panel according to claim 3, wherein: In the first pixel circuit column group, the data signal line in the first group and the data signal line in the third group are electrically connected via a first data connection line; the data signal line in the second group and the data signal line in the fourth group are electrically connected via a second data connection line; The first data connection line and the second data connection line are located in the same film layer, or the first data connection line and the second data connection line are located in different film layers.

16. The display panel according to claim 2, wherein: The third data signal line includes a first sub-data signal line and a second sub-data signal line; In the row direction, the first sub-data signal line and the second sub-data signal line are located on different sides of the second pixel circuit column.

17. The display panel according to claim 2, wherein: The third data signal line includes a first sub-data signal line and a second sub-data signal line; The first sub-data signal line is electrically connected to the third pixel circuits in odd-numbered rows in the second pixel circuit column; The second sub-data signal line is electrically connected to the third pixel circuits in even-numbered rows in the second pixel circuit column.

18. The display panel according to claim 2, wherein: The third data signal line includes a first sub-data signal line and a second sub-data signal line; The first sub-data signal line is electrically connected to all the third pixel circuits in the second pixel circuit column; The second sub-data signal line is electrically connected to all the third pixel circuits in the second pixel circuit column.

19. The display panel according to claim 17 or 18, wherein: The first sub-data signal line and the second sub-data signal line connected to the same second pixel circuit column are electrically connected.

20. The display panel according to claim 19, wherein Also includes a non-display area located on at least one side of the display area; The first sub-data signal line and the second sub-data signal line connected to the same second pixel circuit column are electrically connected via a third data connection line; The third data connection line is located in the non-display area.

21. The display panel according to claim 19, wherein The first sub-data signal line and the second sub-data signal line connected to the same second pixel circuit column are electrically connected via a third data connection line; The third data connection line is located in the display area.

22. The display panel according to claim 20, wherein: The plurality of first pixel circuit columns are divided into a plurality of first pixel circuit column groups, wherein the first pixel circuit column group includes two first pixel circuit columns, and the two first pixel circuit columns are respectively a first group pixel circuit column and a second group pixel circuit column; The first data signal line connected to the first pixel circuit in the first pixel circuit column is a first-group data signal line; the second data signal line connected to the second pixel circuit in the first pixel circuit column is a second-group data signal line; the first data signal line connected to the first pixel circuit in the second pixel circuit column is a third-group data signal line; and the second data signal line connected to the second pixel circuit in the second pixel circuit column is a fourth-group data signal line. In the first pixel circuit column group, the data signal line in the first group and the data signal line in the third group are electrically connected via a first data connection line; The data signal lines in the second group and the data signal lines in the fourth group are electrically connected via a second data connection line; The first data connection line and the second data connection line are both located in the non-display area; The third data connection line is located on a side of the first data connection line close to the display area, and the second data connection line is located between the third data connection line and the first data connection line.

23. The display panel according to claim 22, wherein: Also includes a plurality of data signal output lines; The data signal output lines include a first data signal output line, a second data signal output line and a third data signal output line; In the first pixel circuit column group, the first data connection line is electrically connected to the first data signal output line, and the second data connection line is electrically connected to the second data signal output line; The third data connection line is electrically connected to the third data signal output line; The third data signal output line and the first data connection line are located in different film layers, and the third data signal output line and the second data connection line are located in different film layers.

24. The display panel according to claim 16, wherein: Also included are a plurality of data signal output lines and a plurality of gating circuits; The data signal output line includes a third data signal output line; The gating circuit includes a third gating circuit; In the first sub-data signal line and the second sub-data signal line connected to the same second pixel circuit column, the first sub-data signal line and the second sub-data signal line are electrically connected to the same third data signal output line through the third selection circuit, and the third selection circuit is used to transmit the data signal output by the third data signal output line to the first sub-data signal line and the second sub-data signal line in a time-sharing manner.

25. The display panel according to claim 24, wherein: The third gating circuit includes a fifth switching transistor and a sixth switching transistor, the fifth switching transistor being connected between the first sub-data signal line and the third data signal output line, and the sixth switching transistor being connected between the second sub-data signal line and the third data signal output line; The gate of the fifth switch transistor receives a third switch signal; the gate of the sixth switch transistor receives a fourth switch signal.

26. The display panel according to claim 2, wherein: The third pixel circuits in one column of the second pixel circuits are electrically connected to only one third data signal line.

27. The display panel according to claim 26, wherein: The plurality of second pixel circuit columns are divided into a plurality of second pixel circuit column groups, each of the second pixel circuit column groups including two adjacent second pixel circuit columns, the two adjacent second pixel circuit columns being a third group pixel circuit column and a fourth group pixel circuit column respectively; The third data signal line connected to the pixel circuit column in the third group is the data signal line in the fifth group; the third data signal line connected to the pixel circuit column in the fourth group is the data signal line in the sixth group; In the second pixel circuit column group, the fifth group data signal line is located on a side of the third group pixel circuit columns away from the fourth group pixel circuit columns, and the sixth group data signal line is located on a side of the fourth group pixel circuit columns away from the third group pixel circuit columns; or, In the second pixel circuit column group, the fifth group internal data signal line is located on the side of the third group internal pixel circuit column close to the fourth group internal pixel circuit column, and the sixth group internal data signal line is located on the side of the fourth group internal pixel circuit column close to the third group internal pixel circuit column.

28. The display panel according to claim 26, wherein: The plurality of second pixel circuit columns are divided into a plurality of second pixel circuit column groups, each of the second pixel circuit column groups including two adjacent second pixel circuit columns, the two adjacent second pixel circuit columns being a third group pixel circuit column and a fourth group pixel circuit column respectively; The third data signal line connected to the pixel circuit column in the third group is the data signal line in the fifth group; the third data signal line connected to the pixel circuit column in the fourth group is the data signal line in the sixth group; In the second pixel circuit column group, the fifth group data signal line is located on a side of the third group pixel circuit column away from the fourth group pixel circuit column, and the sixth group data signal line is located on a side of the fourth group pixel circuit column close to the third group pixel circuit column; or, In the second pixel circuit column group, the fifth group data signal line is located on the side of the third group pixel circuit column close to the fourth group pixel circuit column, and the sixth group data signal line is located on the side of the fourth group pixel circuit column away from the third group pixel circuit column.

29. The display panel according to claim 2, wherein: In a direction perpendicular to the plane where the display panel is located, the first data signal line and the second data signal line both overlap with the first pixel circuit column, and the third data signal line overlaps with the second pixel circuit column.

30. The display panel according to claim 2, wherein: Multiple columns of the first pixel circuit columns and multiple columns of the second pixel circuit columns are divided into multiple third pixel circuit column groups, and the third pixel circuit column groups include the first pixel circuit columns and the second pixel circuit columns adjacent to each other along the row direction, and the adjacent first pixel circuit columns and the second pixel circuit columns are arranged in a mirror image.

31. The display panel according to claim 30, wherein: In the third pixel circuit column group, the first data signal line and the second data signal line connected to the first pixel circuit column, and the third data signal line connected to the second pixel circuit column are both located between the first pixel circuit column and the second pixel circuit column.

32. The display panel according to claim 31, wherein: In two adjacent third pixel circuit column groups, the first data signal lines and the second data signal lines in different third pixel circuit column groups are arranged in the same direction or in opposite directions.

33. The display panel according to claim 31, wherein Also included are a plurality of third power signal lines, the plurality of third power signal lines extending along the column direction and arranged along the row direction; The plurality of third power signal lines include a first sub-power signal line, a second sub-power signal line and a third sub-power signal line which are arranged adjacent to each other in sequence along the row direction; An arrangement direction of the first data signal line and the second data signal line between the first sub power signal line and the second sub power signal line is the same as or opposite to an arrangement direction of the first data signal line and the second data signal line between the second sub power signal line and the third sub power signal line.

34. The display panel according to claim 31, wherein: The pixel circuit includes a data writing transistor, and the active layer of the data writing transistor includes a first connection end portion; In the third pixel circuit column group, along the row direction, the first connection end of the first pixel circuit is located on a side of the second data signal line close to the first data signal line, and the first data signal line and the first connection end of the first pixel circuit are electrically connected; In the third pixel circuit column group, along the row direction, the first connection end of the second pixel circuit is located on a side of the first data signal line close to the second data signal line, and the second data signal line and the first connection end of the second pixel circuit are electrically connected.

35. The display panel according to claim 31, wherein The display area includes a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extending along the column direction and arranged along the row direction; The auxiliary signal line is at least partially located in the second display area, and the auxiliary signal line is electrically connected to the data signal line in the first display area; In the third pixel circuit column group, the auxiliary signal line is located between the data signal line connected to the first pixel circuit column and the data signal line connected to the second pixel circuit column.

36. The display panel according to claim 35, wherein: The number of the auxiliary signal lines correspondingly arranged in one of the third pixel circuit column groups is less than or equal to one.

37. The display panel according to claim 31, wherein: The display area includes a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further includes a plurality of auxiliary signal lines, the auxiliary signal lines extending along the column direction and arranged along the row direction; the auxiliary signal lines are at least partially located in the second display area, and the auxiliary signal lines are electrically connected to the data signal lines in the first display area; The auxiliary signal line and the data signal line are located in different film layers; In a direction perpendicular to the plane where the display panel is located, the auxiliary signal line and the data signal line at least partially overlap; or, In a direction perpendicular to the plane where the display panel is located, the auxiliary signal line and the data signal line do not overlap.

38. The display panel according to claim 37, wherein: One column of the first pixel circuits corresponds to one of the auxiliary signal lines, and one column of the second pixel circuits corresponds to one of the auxiliary signal lines; In the third pixel circuit column group, the auxiliary signal line corresponding to the first pixel circuit column is located between the first data signal line and the second data signal line corresponding to the first pixel circuit column, and the auxiliary signal line corresponding to the second pixel circuit column is located between the two third data signal lines corresponding to the second pixel circuit column; or, In the third pixel circuit column group, along the row direction, the auxiliary signal line corresponding to the first pixel circuit column is located on the same side of the first data signal line and the second data signal line corresponding to the first pixel circuit column, and the auxiliary signal line corresponding to the second pixel circuit column is located on the same side of the two third data signal lines corresponding to the second pixel circuit column; or, In a direction perpendicular to the plane of the display panel, the auxiliary signal line corresponding to the first pixel circuit column and the data signal line corresponding to the first pixel circuit column at least partially overlap, and the auxiliary signal line corresponding to the second pixel circuit column and the data signal line corresponding to the second pixel circuit column at least partially overlap.

39. The display panel according to claim 37, wherein: The third pixel circuit column group corresponds to three auxiliary signal lines; In the third pixel circuit column group, along the row direction, three auxiliary signal lines are located between the first pixel circuit column and the second pixel circuit column, and the auxiliary signal line is located between two adjacent data signal lines.

40. The display panel according to claim 37, wherein: One column of the first pixel circuits corresponds to two of the auxiliary signal lines, and one column of the second pixel circuits corresponds to two of the auxiliary signal lines; In a direction perpendicular to the plane where the display panel is located, the auxiliary signal line and the data signal line at least partially overlap.

41. The display panel according to claim 35, wherein: In the third pixel circuit column group, the first data signal line connected to the first pixel circuit column is located on a side of the second data signal line connected to the first pixel circuit column that is farther away from the first pixel circuit column, and a distance between the auxiliary signal line and the second data signal line is greater than a distance between the auxiliary signal line and the third data signal line; or, In the third pixel circuit column group, the second data signal line connected to the first pixel circuit column is located on a side of the first data signal line connected to the first pixel circuit column away from the first pixel circuit column, and a distance between the auxiliary signal line and the first data signal line is greater than a distance between the auxiliary signal line and the third data signal line.

42. The display panel according to claim 35, wherein: In the third pixel circuit column group, the number of the data signal lines connected to the first pixel circuit column is greater than the number of the data signal lines connected to the second pixel circuit column.

43. The display panel according to claim 30, wherein: The display area includes a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extending along the column direction and arranged along the row direction; The auxiliary signal line is at least partially located in the second display area, and the auxiliary signal line is electrically connected to the data signal line in the first display area; In the third pixel circuit column group, along the row direction, the numbers of the data signal lines on both sides of the auxiliary signal line are different.

44. The display panel according to claim 1, wherein The plurality of data signal lines are located in the same film layer.

45. The display panel according to claim 1, wherein At least two of the data signal lines are located in different film layers; In a direction perpendicular to the plane where the display panel is located, the data signal lines located in different film layers at least partially overlap.

46. ​​The display panel according to claim 1 or 2, characterized in that: The light emitting elements include a red light emitting element, a blue light emitting element and a green light emitting element; The first pixel circuit is connected to the red light emitting element; The second pixel circuit is connected to the blue light emitting element; The third pixel circuit is connected to the green light emitting element.

47. The display panel according to claim 1, wherein Also included are a plurality of first power signal lines, the plurality of first power signal lines extending along a first direction and arranged along a second direction, the first direction intersecting the second direction; The plurality of first power signal lines include a first power voltage signal line, a second power voltage signal line and a third power voltage signal line; The first power supply voltage signal line is connected to the first pixel circuit, the second power supply voltage signal line is connected to the second pixel circuit, and the third power supply voltage signal line is connected to the third pixel circuit; The first power supply voltage signal line is used to transmit a first power supply voltage, the second power supply voltage signal line is used to transmit a second power supply voltage, and the third power supply voltage signal line is used to transmit a third power supply voltage; At least two of the first power supply voltage, the second power supply voltage, and the third power supply voltage are different.

48. The display panel according to claim 47, wherein: The light emitting elements include a red light emitting element, a blue light emitting element and a green light emitting element; The first pixel circuit is connected to the red light emitting element, the second pixel circuit is connected to the blue light emitting element, and the third pixel circuit is connected to the green light emitting element; The second power supply voltage is greater than the third power supply voltage, and the third power supply voltage is greater than or equal to the first power supply voltage; or, The second power supply voltage is greater than the first power supply voltage, and the first power supply voltage is greater than or equal to the third power supply voltage.

49. The display panel according to claim 47, wherein: The light emitting elements include a red light emitting element, a blue light emitting element and a green light emitting element; The first pixel circuit is connected to the red light emitting element, the second pixel circuit is connected to the blue light emitting element, and the third pixel circuit is connected to the green light emitting element; The first power supply voltage signal line and the third power supply voltage signal line are the same signal line.

50. The display panel according to claim 49, wherein: The second power supply voltage is greater than the first power supply voltage, and the first power supply voltage is equal to the third power supply voltage.

51. The display panel according to claim 49, wherein: The first power supply voltage signal lines and the second power supply voltage signal lines are alternately arranged along the second direction.

52. The display panel according to claim 49, wherein: Also comprising a plurality of third power signal lines, wherein the plurality of third power signal lines extend along the second direction and are arranged along the first direction; The third power signal line and the first power signal line are located in different film layers; The plurality of third power signal lines include a first power connection signal line and a second power connection signal line; The first power connection signal line is electrically connected to at least two of the first power voltage signal lines, and the second power connection signal line is electrically connected to at least two of the second power voltage signal lines.

53. The display panel according to claim 52, wherein: The first power connection signal lines and the second power connection signal lines are alternately arranged along the first direction.

54. The display panel according to claim 52, wherein: In a direction perpendicular to the plane where the display panel is located, the third power signal line and the green light emitting element at least partially overlap.

55. The display panel according to claim 54, wherein: In the first direction, the third power signal line includes a first boundary and a second boundary opposite to each other; In the first direction, the green light emitting element includes a third boundary and a fourth boundary opposite to each other; Along the first direction, the first boundary and the second boundary are both located between the third boundary and the fourth boundary, and the first boundary is located between the second boundary and the third boundary; Along the first direction, the distance between the first boundary and the third boundary is d1, and the distance between the second boundary and the fourth boundary is d2, where d1=d2.

56. The display panel according to claim 54, wherein: In a direction perpendicular to the plane where the display panel is located, the third power signal line covers the green light emitting element.

57. The display panel according to claim 47, wherein: The light emitting elements include a red light emitting element, a blue light emitting element and a green light emitting element; In a direction perpendicular to the plane where the display panel is located, the first power signal line and the green light emitting element at least partially overlap.

58. The display panel according to claim 57, wherein: In the second direction, the first power signal line includes a fifth boundary and a sixth boundary opposite to each other; In the second direction, the green light emitting element includes a seventh boundary and an eighth boundary that are opposite to each other; Along the second direction, the fifth boundary and the sixth boundary are both located between the seventh boundary and the eighth boundary, and the fifth boundary is located between the sixth boundary and the seventh boundary; Along the second direction, the distance between the fifth boundary and the seventh boundary is d3, and the distance between the sixth boundary and the eighth boundary is d4, where d3=d4.

59. The display panel according to claim 47, wherein The light emitting elements include a red light emitting element, a blue light emitting element and a green light emitting element; In a direction perpendicular to the plane where the display panel is located, the first power signal line covers the green light emitting element.

60. The display panel according to claim 2, wherein: The display area includes a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further includes a plurality of auxiliary signal lines, the auxiliary signal lines extending along the column direction and arranged along the row direction; the auxiliary signal lines are at least partially located in the second display area, and the auxiliary signal lines are electrically connected to the data signal lines in the first display area; A plurality of the first pixel circuit columns and a plurality of the second pixel circuit columns are divided into a plurality of third pixel circuit column groups, wherein the third pixel circuit column groups include the first pixel circuit columns and the second pixel circuit columns adjacent to each other along the row direction; The third pixel circuit column group corresponds to one of the auxiliary signal lines, and the second pixel circuit column corresponds to one of the third data signal lines; In the third pixel circuit column group, the first data signal line and the second data signal line connected to the first pixel circuit column are respectively located on different sides of the first pixel circuit column; In at least one of the third pixel circuit column groups in the second display area, the auxiliary signal line and the third data signal line connected to the second pixel circuit column are located on different sides of the second pixel circuit column.

61. The display panel according to claim 2, wherein: In the row direction, the first data signal line connected to the first pixel circuit column and the second data signal line connected to the second pixel circuit column are respectively located on two opposite sides of the first pixel circuit column; In the row direction, the two third data signal lines connected to the second pixel circuit column are respectively located on two opposite sides of the second pixel circuit column.

62. The display panel according to claim 61, wherein: The display area includes a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further includes a plurality of auxiliary signal lines, the auxiliary signal lines extending along the column direction and arranged along the row direction; the auxiliary signal lines are at least partially located in the second display area, and the auxiliary signal lines are electrically connected to the data signal lines in the first display area; The auxiliary signal line and the data signal line are located in different film layers; or, The auxiliary signal line and the data signal line are located in the same film layer.

63. The display panel according to claim 62, wherein: Also included are a plurality of third power signal lines, the plurality of third power signal lines extending along the column direction and arranged along the row direction; One column of the first pixel circuits corresponds to one auxiliary signal line and one third power signal line, and the auxiliary signal line and the third power signal line are located between the first data signal line and the second data signal line connected to the first pixel circuit column; One column of the second pixel circuits corresponds to one auxiliary signal line and one third power signal line, and the auxiliary signal line and the third power signal line are located between the two third data signal lines connected to the second pixel circuit column.

64. The display panel according to claim 62, wherein: One column of the first pixel circuits corresponds to one of the auxiliary signal lines, and one column of the second pixel circuits corresponds to one of the auxiliary signal lines; The auxiliary signal line is located between the two data signal lines between the first pixel circuit column and the second pixel circuit column that are adjacent to each other.

65. The display panel according to claim 62, wherein: A plurality of the first pixel circuit columns and a plurality of the second pixel circuit columns are divided into a plurality of third pixel circuit column groups, wherein the third pixel circuit column groups include the first pixel circuit columns and the second pixel circuit columns adjacent to each other along the row direction; The third pixel circuit column group corresponds to three auxiliary signal lines; The auxiliary signal line is located between any two adjacent data signal lines.

66. The display panel according to claim 62, wherein: One column of the first pixel circuits corresponds to one or two of the auxiliary signal lines, and one column of the second pixel circuits corresponds to one or two of the auxiliary signal lines; In a direction perpendicular to the plane where the display panel is located, the auxiliary signal line and the data signal line at least partially overlap.

67. The display panel according to claim 2, wherein: The display area includes a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further comprises a plurality of auxiliary signal lines, the auxiliary signal lines extending along the column direction and arranged along the row direction; The auxiliary signal line is at least partially located in the second display area, and the auxiliary signal line is electrically connected to the data signal line in the first display area; One column of the first pixel circuits corresponds to at least two of the auxiliary signal lines, and one column of the second pixel circuits corresponds to at least two of the auxiliary signal lines.

68. The display panel according to claim 67, wherein: The number of the auxiliary signal lines corresponding to one column of the first pixel circuits is less than or equal to 4, and the number of the auxiliary signal lines corresponding to one column of the second pixel circuits is less than or equal to 4.

69. The display panel according to claim 61, wherein: Also included are a plurality of third power signal lines, the plurality of third power signal lines extending along the column direction and arranged along the row direction; One column of the first pixel circuits corresponds to one of the third power signal lines, and one column of the second pixel circuits corresponds to one of the third power signal lines; Along the row direction, the third power signal line is located between two data signal lines between the first pixel circuit column and the second pixel circuit column that are adjacent to each other.

70. The display panel according to claim 69, wherein: In a direction perpendicular to the plane of the display panel, the third power signal line and the data signal line are located in different film layers, and the third power signal line at least partially overlaps with the two data signal lines between the adjacent first pixel circuit column and the second pixel circuit column.

71. The display panel according to claim 69, wherein: The display area includes a first display area and a second display area; Along the row direction, the first display area is located on at least one side of the second display area; The display panel further includes a plurality of auxiliary signal lines, the auxiliary signal lines extending along the column direction and arranged along the row direction; the auxiliary signal lines are at least partially located in the second display area, and the auxiliary signal lines are electrically connected to the data signal lines in the first display area; The auxiliary signal line and the third power signal line are located in different film layers; In a direction perpendicular to the plane where the display panel is located, the auxiliary signal line at least partially overlaps with the third power signal line.

72. The display panel according to claim 69, wherein: The light emitting elements include a red light emitting element, a blue light emitting element and a green light emitting element; In a direction perpendicular to the plane of the display panel, the red light emitting element, the green light emitting element and the blue light emitting element at least partially overlap with the third power signal line between the adjacent first pixel circuit column and the second pixel circuit column.

73. The display panel according to claim 61, wherein The light emitting elements include a red light emitting element, a blue light emitting element and a green light emitting element; In a direction perpendicular to the plane of the display panel, the red light emitting element, the green light emitting element and the blue light emitting element at least partially overlap with the data signal line between the adjacent first pixel circuit column and the second pixel circuit column.

74. The display panel according to claim 1, wherein The pixel circuit further includes a driving transistor, a threshold compensation transistor and a shielding layer, wherein the gate of the driving transistor and the threshold compensation transistor are connected to a first node; Along a direction parallel to the plane where the display panel is located, at least a portion of the shielding layer is located between the first node and the data signal line.

75. The display panel according to claim 74, characterized in that In a direction perpendicular to the plane where the display panel is located, the shielding layer is located between the active layer of the driving transistor and the data signal line, and the shielding layer and the data signal line at least partially overlap.

76. The display panel according to claim 74, characterized in that A fixed voltage is applied to the shielding layer.

77. The display panel according to claim 76, characterized in that Also included are a plurality of third power signal lines, the plurality of third power signal lines extending along the second direction and arranged along the first direction, the first direction intersecting the second direction; The shielding layer is electrically connected to the third power signal line.

78. A display device, characterized in that A display panel comprising any one of claims 1-77.

Images