Bias circuit, bias chip and bias device
By adding a resistor and an inductor in series in the bias circuit and introducing a second capacitor in the DC branch, the problem of the bias chip being difficult to balance in terms of size, bandwidth, and insertion loss is solved, and the miniaturization and high-bandwidth effect of the bias chip are achieved.
Patent Information
- Application Number
- CN202422684804.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-09-12
- Estimated Expiration
- 2034-11-04
AI Technical Summary
Existing bias chips are difficult to meet the requirements of size, bandwidth and insertion loss. Traditional bias chips have the problems of large size and low bandwidth or high bandwidth and high insertion loss.
A bias circuit is used, including a combination of a first capacitor, a second capacitor, an inductor and a resistor. By adding a resistor in series with the inductor, the total impedance of the DC branch is increased, and a second capacitor is introduced in the DC branch to bypass the AC signal and reduce insertion loss.
The insertion loss is reduced in the case of small inductance, meeting the requirements of small bias chip size and high bandwidth, while effectively preventing AC signals from leaking to the DC bias power supply, improving system stability.
Smart Images
Figure CN223334665U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of integrated circuits, and in particular to a bias circuit, a bias chip and a bias device. Background Art
[0002] In optical communication systems, the bias tee plays a crucial role. Its primary function is to provide the necessary DC bias voltage for the optoelectronic chip, ensuring its proper operation. Furthermore, the bias tee effectively blocks AC signals from entering the power supply line without interfering with optical signal transmission, thereby protecting the power supply from interference and ensuring system stability and reliability.
[0003] In traditional bias chips, such as Figure 1 As shown in the figure, using an oversized inductor has the advantage of low insertion loss, but the disadvantages are low bandwidth and a large bias chip. Using a small inductor has the advantage of high bandwidth and a small bias chip, but the disadvantage is high insertion loss. Existing bias chips struggle to balance size, bandwidth, and insertion loss. Utility Model Content
[0004] The embodiments of the present invention provide a bias circuit, a bias chip, and a bias device to solve the technical problem in the related art that the bias circuit of the existing bias chip is difficult to balance size, bandwidth, and insertion loss.
[0005] In a first aspect, a bias circuit is provided, comprising: a first capacitor, a second capacitor, an inductor, and a resistor;
[0006] The first end of the first capacitor is connected to the first end of the inductor and serves as the input end of the bias circuit, and the second end of the first capacitor serves as the output end of the bias circuit;
[0007] The first end of the resistor is connected to the first end of the inductor, the second end of the resistor is connected to the first end of the second capacitor and serves as an input end of a DC bias power supply, and the second end of the second capacitor is grounded.
[0008] In some embodiments, the inductor has a spiral structure.
[0009] In some embodiments, the first capacitor is an electrolytic capacitor.
[0010] In some embodiments, the second capacitor is an electrolytic capacitor.
[0011] In some embodiments, the resistor is a precision resistor.
[0012] In a second aspect, a bias chip is provided, comprising:
[0013] a substrate on which the bias circuit is disposed;
[0014] A lead frame is provided on the substrate and connected to the bias circuit.
[0015] In some embodiments, the input and output pins of the lead frame adopt a GSG structure.
[0016] In some embodiments, the substrate is a silicon substrate.
[0017] In some embodiments, the bias chip is manufactured using a BICOMS process.
[0018] In a third aspect, a bias device is provided, comprising the aforementioned bias chip, and further comprising:
[0019] A DC bias power supply is configured to output a DC bias voltage to the second end of the resistor and the first end of the second capacitor.
[0020] The beneficial effects brought about by the technical solution provided by the utility model include:
[0021] The present invention provides a bias circuit, bias chip, and bias device. The bias circuit adds a resistor in series with an inductor. This increases the total impedance of the DC branch and reduces insertion loss when using a small inductor, thereby meeting the requirements for a small bias chip size, high bandwidth, and low insertion loss. A second capacitor is introduced into the DC branch to remove leaked AC signals, further preventing them from leaking into the DC bias power supply. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 A circuit diagram of a bias circuit of an existing bias chip;
[0024] Figure 2 A circuit diagram of a bias circuit provided in an embodiment of the present utility model;
[0025] Figure 3 A schematic diagram of an inductor provided in an embodiment of the present utility model;
[0026] Figure 4 A schematic diagram of a lead frame of a bias chip provided in an embodiment of the present utility model. DETAILED DESCRIPTION
[0027] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.
[0028] The embodiment of the utility model provides a bias circuit, which can solve the technical problem that the bias circuit of the existing bias chip is difficult to take into account the size, bandwidth and insertion loss.
[0029] See also Figure 1 As shown, an embodiment of the present invention provides a bias circuit, characterized in that it includes: a first capacitor C1, a second capacitor C2, an inductor L and a resistor R.
[0030] The first end of the first capacitor C1 is connected to the first end of the inductor L and serves as the input end of the bias circuit, and the second end of the first capacitor C1 serves as the output end of the bias circuit.
[0031] The first end of the resistor R is connected to the first end of the inductor L, the second end of the resistor R is connected to the first end of the second capacitor C2 and serves as the input end of the DC bias power supply, and the second end of the second capacitor C2 is grounded.
[0032] The bias circuit of the present embodiment adds a resistor in series with the inductor, and the total impedance becomes Z = R + ωL. That is, when using a small inductor (without increasing the inductor value), the total impedance of the DC branch is increased, the insertion loss is reduced, and the requirements of a small bias chip size, high bandwidth, and low insertion loss are met. A second capacitor is introduced in the DC branch to lead out the leaked AC signal, better preventing the AC signal from leaking into the DC bias power supply. The size of existing traditional bias chip products is generally about 3 to 5 cm in length. The bias chip using the bias circuit of the present embodiment can be reduced to about 0.7 mm in size, facilitating chip integration.
[0033] As an optional implementation, in one embodiment of the utility model, the inductor is a spiral structure. Figure 2 As shown, the inductor adopts a spiral structure. On-chip inductors with a spiral structure can reduce parasitic capacitance while maintaining the same inductance value, thereby increasing the resonant frequency. The inductor of this embodiment of the utility model is manufactured using a SiGe 180nm process, which typically uses six metal layers M1 to M6. This inductor is manufactured using two metal layers, M5 and M6.
[0034] As an optional implementation, in one embodiment of the utility model, the first capacitor C1 and the second capacitor C2 are both electrolytic capacitors. Electrolytic capacitors have large capacity, low price, good ripple current resistance and wide frequency and temperature characteristics.
[0035] As an optional implementation, in one embodiment of the utility model, the resistor is a precision resistor. Precision resistors have the characteristics of high precision, high stability, low temperature drift, and low noise. Optionally, the resistor is a precision resistor with an error within ±1%.
[0036] The present invention also provides a bias chip comprising a substrate and a lead frame. The bias circuit is disposed on the substrate, and the lead frame is disposed on the substrate and connected to the bias circuit. Optionally, the substrate is a silicon substrate.
[0037] The bias circuit includes: a first capacitor C1, a second capacitor C2, an inductor L, and a resistor R. The first end of the first capacitor C1 is connected to the first end of the inductor L and serves as the input end of the bias circuit, and the second end of the first capacitor C1 serves as the output end of the bias circuit. The first end of the resistor R is connected to the first end of the inductor L, and the second end of the resistor R is connected to the first end of the second capacitor C2 and serves as the input end of the DC bias power supply. The second end of the second capacitor C2 is grounded.
[0038] The bias chip of this embodiment adds a resistor in series with the inductor to its bias circuit, creating a total impedance of Z = R + ωL. This increases the total impedance of the DC branch while using a small inductor (without increasing the inductor value), reducing insertion loss and meeting the requirements for a small bias chip size, high bandwidth, and low insertion loss. To better prevent AC signal leakage into the DC bias power supply, a second capacitor is introduced into the DC branch, acting as a bypass to divert any leaked AC signal.
[0039] In addition, the lead frame is a key component for connecting the circuits inside the chip to external pins, including various input and output pins, power supply pins, ground pins, etc. The lead frame plays a vital role in chip layout design, ensuring the correct transmission of signals and the normal operation of the chip. Optionally, the input and output pins of the lead frame adopt a GSG structure. The GSG structure is a test structure used in integrated circuits, including a pair of signal pads and two pairs of ground pads, all of which are arranged linearly, so that the width of the structure is small enough to be set within the narrow zigzag channel of the chip. Figure 4 A schematic diagram of a lead frame of a bias chip provided in an embodiment of the present utility model.
[0040] In the lead frame, each pin is generally a metal pin made of the M6 layer, and an electrostatic discharge protection circuit can be set on the outside. The lead frame and the electrostatic discharge protection circuit work together. Specifically, the pins of the lead frame are responsible for the connection of the signal transmission port as well as power supply and grounding, while the electrostatic discharge protection circuit acts as a protection circuit to prevent electrostatic discharge from damaging sensitive electronic components. While maintaining efficient transmission performance, the lead frame effectively improves the reliability and durability of the system through the electrostatic discharge protection circuit. This protection mechanism can prevent transient impacts on the circuit caused by electrostatic discharge, thereby ensuring the stable operation of the overall bias circuit.
[0041] As an optional implementation, in one embodiment of the utility model, the bias chip is manufactured using a BICOMS process. The BICMOS process is a new generation of high-performance VLSI process following CMOS. It is based on the CMOS process with a small number of process steps added. CMOS has become a mainstream process with low power consumption and high density. As the size gradually shrinks, the circuit performance continues to improve. However, when the size drops below 1um, its potential is greatly limited due to reasons such as carrier velocity saturation. Integrating CMOS and Bipolar on the same chip, giving full play to their respective advantages and overcoming their shortcomings can make the circuit achieve high speed and low power consumption. The circuit of the BICOMS process has the advantages of high integration and low power consumption of CMOS circuits, and also obtains the advantages of high speed and strong current driving capability of bipolar circuits.
[0042] As an optional implementation, in one embodiment of the utility model, the inductor is a spiral structure. Figure 2 As shown, the inductor adopts a spiral structure. On-chip inductors with a spiral structure can reduce parasitic capacitance while maintaining the same inductance value, thereby increasing the resonant frequency. The inductor of this embodiment of the utility model is manufactured using a SiGe 180nm process, which typically uses six metal layers M1 to M6. This inductor is manufactured using two metal layers, M5 and M6.
[0043] As an optional implementation, in one embodiment of the utility model, the first capacitor C1 and the second capacitor C2 are both electrolytic capacitors. Electrolytic capacitors have large capacity, low price, good ripple current resistance and wide frequency and temperature characteristics.
[0044] As an optional implementation, in one embodiment of the utility model, the resistor is a precision resistor. Precision resistors have the characteristics of high precision, high stability, low temperature drift, and low noise. Optionally, the resistor is a precision resistor with an error within ±1%.
[0045] An embodiment of the present invention further provides a bias device, comprising the aforementioned bias chip, and further comprising: a DC bias power supply, wherein the DC bias power supply is configured to output a DC bias voltage to the second end of the resistor and the first end of the second capacitor.
[0046] In the description of the present invention, it should be noted that the terms "upper" and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be internal communication between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.
[0047] It should be noted that, in the present invention, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements that are inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.
[0048] The foregoing description is intended only to provide specific embodiments of the present invention, intended to enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but rather to be construed in the broadest manner consistent with the principles and novel features of the present invention.
Claims
1. A bias circuit, characterized in that: include: a first capacitor, a second capacitor, an inductor, and a resistor; The first end of the first capacitor is connected to the first end of the inductor and serves as the input end of the bias circuit, and the second end of the first capacitor serves as the output end of the bias circuit; The first end of the resistor is connected to the first end of the inductor, the second end of the resistor is connected to the first end of the second capacitor and serves as an input end of a DC bias power supply, and the second end of the second capacitor is grounded.
2. The bias circuit according to claim 1, wherein: The inductor has a spiral structure.
3. The bias circuit according to claim 1, wherein: The first capacitor is an electrolytic capacitor.
4. The bias circuit according to claim 1, wherein: The second capacitor is an electrolytic capacitor.
5. The bias circuit according to claim 1, wherein: The resistor is a precision resistor.
6. A bias chip, characterized in that: include: a substrate, the bias circuit according to claim 1 being provided on the substrate; A lead frame is provided on the substrate and connected to the bias circuit.
7. The bias chip according to claim 6, wherein: The input and output pins of the lead frame adopt a GSG structure.
8. The bias chip according to claim 6, wherein: The substrate is a silicon substrate.
9. The bias chip according to claim 6, wherein: The bias chip is manufactured using a BICOMS process.
10. A bias device, comprising the bias chip according to any one of claims 6 to 9, characterized in that: Also includes: A DC bias power supply is configured to output a DC bias voltage to the second end of the resistor and the first end of the second capacitor.