Metal insulating layer metal capacitor embedded in passivation layer

Abstract

The utility model provides a passivation layer formed above an interconnection line structure. The etch opening at least partially passes through the passivation layer. A first conductive layer is deposited over the passivation layer. The first conductive layer partially fills the opening. An insulating layer is deposited over the first conductive layer. The insulating layer partially fills the opening. A second conductive layer is deposited over the insulating layer. The second conductive layer completely fills the opening. A first conductive structure electrically coupled to the first conductive layer is formed. A second conductive structure electrically coupled to the second conductive layer is formed.

Description

Technical Field

[0001] The utility model relates to a metal capacitor with a metal insulating layer embedded in a passivation layer. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC design and materials have produced generations of ICs, each with smaller and more complex circuits than the previous one. During the course of IC evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or wire) that can be created using a process) has shrunk.

[0003] As semiconductor devices continue to shrink in size, manufacturing challenges may increase. For example, a metal-insulator-metal (MIM) structure can be used to implement microelectronic components, such as capacitors. However, in order to increase the capacitance of a MIM capacitor, the area (and size) of the MIM capacitor is typically increased. As semiconductor devices evolve to more advanced (e.g., smaller) technology nodes, it may be difficult to allocate the area required to achieve the capacitance of the MIM capacitor. As a result, the performance of the MIM capacitor may decline. So, although semiconductor manufacturing methods are generally sufficient for their intended purposes, they are not completely satisfactory in every aspect. Utility Model Content

[0004] The utility model provides a device. The device includes an interconnect structure. A first passivation layer is disposed above the interconnect structure. A recess is disposed within the first passivation layer. A first conductive layer is disposed above the interconnect structure and partially within the recess. An insulating layer is disposed above the first conductive layer and partially within the recess. A second conductive layer is disposed above the insulating layer. The second conductive layer completely fills the recess. A second passivation layer is disposed above the second conductive layer.

[0005] The present invention provides a device. The device includes a first passivation layer disposed above an interconnect structure. The device includes a second passivation layer disposed above the first passivation layer. The device further includes a metal-insulator-metal capacitor disposed between the first passivation layer and the second passivation layer. The metal-insulator-metal capacitor includes a downwardly protruding portion that at least partially protrudes through the first passivation layer.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 13 According to various aspects of the present invention, there are cross-sectional views of an IC device (or portions thereof) at various stages of fabrication.

[0008] Figure 14 Various aspects of the present invention are top views of an IC device (or portions thereof) at stages of fabrication.

[0009] Figure 15 According to various aspects of the present invention, a conductive through-hole and a plurality of adjacent components thereof are cross-sectional views during a manufacturing stage.

[0010] Figure 16 、 17A 17B and 17B are top views of various IC devices (or portions thereof) at various stages of fabrication according to various aspects of the present invention.

[0011] Figure 18 According to various aspects of the present invention, a block diagram of an IC manufacturing system is provided.

[0012] Figure 19 The flowchart is a method for manufacturing an IC device related to an embodiment of the present invention.

[0013] Description of Reference Numerals

[0014] 100: IC device

[0015] 110: IC substrate

[0016] 115: Circuit

[0017] 120: Interconnection structure

[0018] 130, 131: Metal wiring

[0019] 140: Dielectric Materials

[0020] 150, 350: passivation layer

[0021] 155, 370: Photolithography

[0022] 160, 380: Patterned photoresist layer

[0023] 180, 181, 390, 391: Opening / groove

[0024] 190, 230, 330, 400: Etching process

[0025] 200, 260, 300, 345: Deposition process

[0026] 210, 310: conductive layer

[0027] 210A, 210B, 210C, 310A, 310B, 310C: Conductive layer segments

[0028] 210D, 280D, 310D: dummy segments

[0029] 240, 340: opening

[0030] 280: Insulation layer

[0031] 280A, 280C: Insulation layer fragment

[0032] 410: Redistribution layer formation process

[0033] 420, 421, 560: Conductive perforation

[0034] 430, 431: Conductive pads

[0035] 480, 481, 660, 690: protruding

[0036] 490: Depth

[0037] 500: thickness

[0038] 510, 511: Part

[0039] 520, 630: size

[0040] 530, 570, 580, 590, 595: distance

[0041] 540: Minimum distance

[0042] 600A-600D, 650, 680: Capacitor units

[0043] 610: Boundary

[0044] 900: Integrated Circuit Manufacturing Systems

[0045] 902, 904, 906, 908, 910, 912, 914, 916…, N: Entity

[0046] 918: Network

[0047] 1000: Method

[0048] 1010, 1020, 1030, 1040, 1050, 1060: Steps DETAILED DESCRIPTION

[0049] The following disclosure provides many different embodiments or examples for realizing the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. As shown, for example, in the following description, forming a first feature or upper and second features may include embodiments in which the first and second features are directly formed in contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be directly in contact. In addition, in various examples, the present invention may be repeated reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or architectures discussed.

[0050] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature(s), as shown in the figures. Spatially relative terms are intended to encompass different orientations of a component in use or operation in orientations other than those depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0051] Furthermore, when "about," "approximate," or the like is used to describe a number or range of numbers, the term is intended to encompass numbers within a reasonable range including the number being described, such as + / - 10% of the number being described, or other values ​​understood by those skilled in the art. For example, the term "about 5 nanometers" encompasses a size range from 4.5 nanometers to 5.5 nanometers.

[0052] Multiple IC chips contain multiple different types of microelectronic components, such as transistors, resistors, inductors, capacitors, and the like. For each of these microelectronic component types, there can be multiple manufacturing methods, resulting in different structures. In some cases, capacitors can be implemented using a MIM structure, for example, as part of a copper (Cu) redistribution layer (RDL) frame or an aluminum-copper (AlCu) redistribution layer frame. The MIM structure can include multiple metal-containing layers and multiple insulating layers, where each insulating layer is located between two individual metal-containing layers.

[0053] For MIM capacitors on ICs, achieving high capacitance may be desirable. However, as the size of semiconductor features shrinks with each technology generation, the effective area of ​​the MIM capacitor also shrinks, which may negatively impact the capacitance. Additional metal layers and insulating layers can be used to effectively increase the capacitance of MIM capacitors on ICs. However, doing so may make the manufacturing process more complicated, extend production time, and increase production costs. To address these issues, the present invention is related to a manufacturing method and framework for implementing multiple trenches in a passivation layer, and the MIM capacitor can be at least partially formed in the multiple trenches in the passivation layer. The multiple trenches allow the MIM capacitor to increase additional surface area (for example, based on the depth of the multiple trenches) without the need for additional metal layers or insulating layers. Therefore, according to various aspects of the present invention, the formed MIM capacitor can still achieve relatively high capacitance without substantially complicating the process or increasing manufacturing costs.

[0054] The following references Figures 1 to 13 , which discusses a process flow for implementing the MIM capacitor of the present invention, is a plurality of schematic partial cross-sectional views of an IC device 100 (eg, a workpiece) constructed according to various aspects of the present invention in some embodiments.

[0055] Now please refer to Figure 1 , the IC device 100 includes an IC substrate 110. In some embodiments, the IC substrate 110 includes a semiconductor substrate, such as a silicon substrate. The IC substrate 110 may also include a plurality of devices, such as field-effect transistors (FETs), memory cells, image sensors, passive devices, other devices, or combinations thereof. In some embodiments, the IC substrate 110 includes a plurality of flat active areas with a plurality of IC devices, such as a plurality of plain field-effect transistors. In some other embodiments, the IC substrate 110 includes a plurality of fin (e.g., vertically protruding) active areas with a plurality of IC devices formed thereon. Please understand that in some embodiments, the plurality of fin active areas may also be used to form a plurality of gate-all-around (GAA) devices. In any case, as a simplified non-limiting example herein, the Figure 1 A circuit 115 is formed in the IC substrate 110. The circuit 115 may include a planar transistor or a FinFET (or GAA) transistor.

[0056] The IC device 100 may also include an interconnection structure 120 formed above the semiconductor substrate. The interconnection structure 120 includes multiple conductive components, such as multiple metal lines (e.g., metal line 130 or metal line 131), multiple contacts, and multiple vias, to provide horizontal and vertical electrical routing. The multiple metal lines, such as metal line 130, are distributed in multiple metal layers, such as a first metal layer (e.g., M1 layer), a second metal layer (e.g., M2 layer), etc., and a top metal layer. In the illustrated embodiments, the multiple metal lines 130 to 131 belong to the topmost metal layer of the interconnection structure 120, and for simplicity, the multiple metal lines and / or multiple vias of other metal layers of the interconnection structure 120 are not specifically illustrated here.

[0057] In addition, the plurality of conductive elements of interconnect structure 120 can provide electrical connections to circuit 115. Interconnect structure 120 also includes dielectric material 140 to provide electrical isolation between the conductive elements, thereby preventing electrical shorts. In some embodiments, dielectric material 140 can include an oxide material, such as silicon oxide. It can be said that the plurality of metal wires, such as metal wires 130-131, are embedded in dielectric material 140.

[0058] Now please refer to Figure 2 A planarization process, such as a chemical mechanical polishing (CMP) process, may be performed to planarize the upper surface of the interconnect structure 120. Thereafter, a passivation layer 150 may be formed over the planarized upper surface of the interconnect structure 120, including over the plurality of metal lines 130 and 131. In some embodiments, the passivation layer 150 may be formed using one or more deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. In some embodiments, the passivation layer 150 is formed to have a silicon carbonitride (SiCN) material composition. In some other embodiments, the passivation layer 150 may have a silicon nitride (SiN) material composition. In yet other embodiments, the passivation layer 150 may include another dielectric material type other than SiCN or SiN. As discussed in more detail below, the MIM capacitor of the present invention will be partially embedded in the passivation layer 150.

[0059] Now please refer to Figure 3 A lithography process 155 is performed on the IC device 100 to form a patterned photoresist layer 160 over the passivation layer 150. The lithography process 155 may include one or more photoresist coating, pre-exposure baking, exposing, post-exposure baking, developing, and rinsing processes (not necessarily in this order). As a result of the lithography process 155, the patterned photoresist layer 160 includes a plurality of openings, such as a plurality of openings 180 and 181, each of which exposes a portion of the upper surface of the passivation layer 150.

[0060] Now please refer to Figure 4 , an etching process 190 is performed on the IC device 100. The etching process 190 may include a dry etching process in some embodiments, a wet etching process in some other embodiments, or a combination thereof in some other embodiments. The etching process 190 further extends the plurality of openings 180 and 181 vertically downward (e.g., in a direction toward the substrate 110) using the patterned photoresist layer 160 as an etching mask. In other words, the patterned photoresist layer 160 protects portions of the underlying passivation layer 150 from being etched, while other portions of the passivation layer 150 exposed by the plurality of openings 180 and 181 are removed through the etching process 190. The plurality of openings 180 and 181 in the passivation layer 150 may have a groove-like profile and may therefore be interchangeably referred to as grooves 180 and 181. Note that the plurality of lower portions of the plurality of openings 180 and 181 are located in the passivation layer 150. Figure 4 The cross-sectional views of the plurality of openings 180 and 181 may each have a trapezoidal shape, wherein the plurality of openings 180 and 181 are each wider at the top and narrower at the bottom, with a plurality of inclined side surfaces. It should also be noted that the plurality of openings 180 and 181 may or may not extend entirely through the passivation layer 150. In other words, in some embodiments, the plurality of openings 180 and 181 may expose the plurality of upper surfaces of the interconnect structure 120, or in some embodiments, the plurality of openings 180 and 181 may not expose the plurality of upper surfaces of the interconnect structure 120.

[0061] Now please refer to Figure 5, the patterned photoresist layer 160 is removed, for example, through a photoresist stripping process or a photoresist ashing process. Thereafter, a deposition process 200 is performed on the IC device 100 to deposit a conductive layer 210 above the IC device 100. In some embodiments, the conductive layer 210 may include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a combination thereof. In some embodiments, the deposition process 200 deposits titanium nitride (TiN) as the conductive layer 210, but it should be understood that in other embodiments, other types of conductive materials (e.g., titanium aluminum or copper) may be deposited as the conductive layer 210. As Figure 5 As shown, some portions of the conductive layer 210 are formed on the plurality of upper surfaces of the passivation layer 150, and some other portions of the conductive layer 210 are formed on the plurality of bottom surfaces and the plurality of side surfaces of the plurality of openings 180 and 181. In other words, the plurality of portions of the conductive layer 210 are partially formed in the plurality of openings 180 and 181.

[0062] Now please refer to Figure 6 , an etching process 230 is performed on the IC device 100. The etching process 230 etches away a segment of the conductive layer 210 that is horizontally arranged between the metal wiring 131 and the opening 181. As a result, the opening 240 in the conductive layer 210 exposes a portion of the upper surface of the passivation layer 150 that is arranged between the metal wiring 131 and the opening 181. As a result, the conductive layer 210 is divided into two segments 210A and 210B, which are electrically isolated or separated from each other through the opening 240. Note that in some embodiments, the etching process 230 can be performed using a patterned photoresist layer as an etching mask. However, for simplicity, the formation and subsequent removal of the patterned photoresist layer are not specifically shown here.

[0063] Please refer to Figure 7 , a deposition process 260 is performed on IC device 100. Deposition process 260 may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof. The deposition process deposits insulating layer 280 over passivation layer 150 and over the plurality of conductive layer segments 210A and 210B. In some embodiments, insulating layer 280 may include a high-k dielectric material having a dielectric constant greater than that of silicon dioxide (e.g., greater than 4). In some embodiments, insulating layer 280 includes hafnium oxide. In other embodiments, insulating layer 280 includes zirconium oxide. In other embodiments, other types of dielectric materials may also be implemented as insulating layer 280.

[0064] like Figure 7 As shown, insulating layer segments 280A are deposited in openings 240 and directly on the upper surface of passivation layer 150, while the remainder of insulating layer 280 is deposited on the upper and side surfaces of conductive layer segments 210A and 210B. The presence of insulating layer segments 280A in openings 240 helps ensure that conductive layer segment 210A is electrically isolated from conductive layer segment 210B. In other words, electrical signals cannot be conducted from conductive layer segment 210A to conductive layer segment 210B (or vice versa) via insulating layer segments 280A.

[0065] Now please refer to Figure 8 After forming insulating layer 280, a deposition process 300 is performed on IC device 100. Deposition process 300 may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof. Deposition process 300 deposits conductive layer 310 over insulating layer 280. In some embodiments, conductive layer 310 may have the same material composition as the plurality of conductive layer segments 210A and 210B. For example, conductive layer 310 and the plurality of conductive layer segments 210A and 210B may both have a titanium nitride material composition. In other embodiments, conductive layer 310 may have a different material composition than the plurality of conductive layer segments 210A and 210B. Note that while the plurality of openings 180-181 and 240 are partially filled by the plurality of conductive layer segments 210A and 210B and / or insulating layer 280, the plurality of openings 180-181 and 240 are completely filled by conductive layer 310. Therefore, it can be said that portions of conductive layer 210A, portions of insulating layer 280, and portions of conductive layer 310 are collectively embedded in passivation layer 150. This is one of the unique physical properties of the present invention, the advantages of which will be discussed in more detail below.

[0066] Now please refer to Figure 9 , an etching process 330 is performed on the IC device. The etching process 330 etches away a portion of the conductive layer 310 that is horizontally arranged between the metal wiring 130 and the opening 180. As a result, the opening 340 in the conductive layer 310 exposes a portion of the upper surface of the insulating layer 280, which is arranged between the metal wiring 130 and the opening 180 (now filled with the conductive layer 210A, the insulating layer 280, and the conductive layer 310). As a result, the conductive layer 310 is divided into two segments 310A and 310B, which are electrically isolated or separated from each other through the opening 340. Note that in some embodiments, the etching process 330 can be performed using a patterned photoresist layer as an etching mask. However, for simplicity, the formation and subsequent removal of the patterned photoresist layer are not specifically shown here.

[0067] Now please refer to Figure 10, a deposition process 345 is performed on IC device 100. Deposition process 345 may include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a combination thereof, to deposit a passivation layer 350 over the upper surfaces of the plurality of conductive layer segments 310A and 310B and over the portion of the upper surface of insulating layer 280 exposed by opening 340. In some embodiments, deposition process 345 may include a high-density plasma process to form undoped silicate glass (USG) as passivation layer 350. In other embodiments, deposition process 345 may be configured such that the deposited passivation layer 350 has the same material composition as passivation layer 150. For example, passivation layer 350 has a silicon carbonitride (SiCN) material composition or a silicon nitride (SiN) material composition. In such embodiments, passivation layer 150 may also have a silicon carbonitride or silicon nitride material composition. In any case, it can be seen that the passivation layer 350 completely fills the opening 340 and prevents the plurality of conductive layer segments 310A and 310B from making electrical and / or physical contact with each other. In other words, electrical signals cannot be conducted from the conductive layer segment 310A to the conductive layer segment 310B (or vice versa) via the passivation layer 350 because the material of the passivation layer 350 is also electrically insulating.

[0068] Now please refer to Figure 11 A photolithography process 370 is performed on the IC device 100 to form a patterned photoresist layer 380 over the passivation layer 350. The photolithography process 370 may include one or more photoresist coating, pre-exposure baking, exposure, post-exposure baking, development, and rinsing processes (not necessarily in this order). As a result of the photolithography process 370, the patterned photoresist layer 380 includes a plurality of openings, such as a plurality of openings 390 and 391, each of which exposes a portion of the upper surface of the passivation layer 350.

[0069] Now please refer to Figure 12, an etching process 400 is performed on the IC device 100. The etching process 400 may include a dry etching process in some embodiments, a wet etching process in some other embodiments, or a combination thereof in some other embodiments. The etching process 400 further extends the plurality of openings 390 and 391 vertically downward (e.g., in a direction toward the substrate 110) using the patterned photoresist layer 380 as an etching mask. In other words, the patterned photoresist layer 380 protects portions of the underlying passivation layer 350 from being etched, while other portions of the passivation layer 350 exposed by the plurality of openings 390 and 391 are removed through the etching process 400. The plurality of openings 390 and 391 in the passivation layer 350 may have a groove-like profile and may therefore be interchangeably referred to as grooves 390 and 391. Note that the plurality of lower portions of the plurality of openings 390 and 391 are located in the passivation layer 350. Figure 4 The cross-sectional views of the plurality of openings 390 and 391 may each have a trapezoidal shape, wherein the plurality of openings 390 and 391 are each wider at the top and narrower at the bottom, and have a plurality of inclined side surfaces. The plurality of openings 390 and 391 may all extend through the passivation layer 150, exposing a plurality of upper surfaces of the plurality of metal wirings 130 and 131.

[0070] Now please refer to Figure 13 The patterned photoresist layer 380 is removed using a photoresist stripping process or a photoresist ashing process, after which a redistribution layer forming process 410 is performed on the IC device 100. The redistribution layer forming process 410 fills the plurality of openings 390 and 391 with one or more conductive materials, such as titanium nitride, tungsten, copper, aluminum, cobalt, ruthenium, and the like. Thus, a plurality of conductive through-vias 420 and 421 are formed to fill the plurality of openings 390 and 391, respectively. The redistribution layer forming process 410 may also form a plurality of conductive pads 430 and 431 above the plurality of conductive through-vias 420 and 421, respectively. In some embodiments, the plurality of conductive pads 430 and 431 may have the same material composition as the plurality of conductive through-vias 420 and 421. It should be understood that the plurality of conductive through-vias 420 to 421 and / or the plurality of conductive pads 430 to 431 may be collectively referred to as a plurality of redistribution structures of the IC device 100. In some embodiments, the redistribution layer forming process 410 may include an electroplating process to form various types of conductive materials of the redistribution structure.

[0071] Note that due to the etching and subsequent filling of the plurality of openings 390 and 391 (with conductive vias 420 and 421), the bottom conductive layer 210 has now been divided into a plurality of different conductive layer segments, including conductive layer segment 210A, conductive layer segment 210B, and conductive layer segment 210C. Similarly, the top conductive layer 310 has now been divided into a plurality of different conductive layer segments, including conductive layer segment 310A, conductive layer segment 310B, and conductive layer segment 310C. In addition, the insulating layer 280 has also been damaged, so that the insulating layer segment 280C is physically separated from the rest of the insulating layer 280. The insulating layer segment 280C is sandwiched between the plurality of conductive layer segments 210C and 310C.

[0072] At this stage of fabrication, a MIM capacitor 450 is formed. The MIM capacitor 450 includes the conductive layer segment 210C (serving as the bottom electrode plate), the insulating layer segment 280C, and the conductive layer segment 310C (serving as the top electrode plate). Note that due to the implementation of the insulating layer segment 280A filling the opening 240 (see above for details), the conductive layer segment 210C is formed. Figure 7 ), the electrical connection between the bottom conductive layer 210C and the conductive via 421 (and therefore the conductive pad 431) is severed. Instead, electrical access to the conductive layer segment 210C is provided by the conductive pad 430 through the conductive via 420, which is electrically connected to the conductive layer segment 210C. Similarly, due to the formation of the opening 340 (see above regarding Figure 9 ) and the subsequent filling of opening 340 with passivation layer 350, the electrical connection between top conductive layer 310C and conductive via 420 (and therefore, conductive pad 430) is severed. Instead, electrical access to conductive layer segment 310C is provided by conductive pad 431 through conductive via 421, which is electrically connected to conductive layer segment 310C. Thus, multiple conductive pads 430 and 431 can be said to be used to control the electrical operation of MIM capacitor 450. For example, different voltage potentials can be applied to multiple conductive pads 430 and 431.

[0073] One of the unique physical characteristics of the MIM capacitor 450 herein is that it has one or more portions that substantially protrude downwardly into the passivation layer 150. For example, the MIM capacitor 450 has a plurality of downward protrusions 480 and 481 that protrude downwardly toward the substrate 110, wherein the plurality of downward protrusions 480 and 481 are embedded in the passivation layer 150. These downward protrusions 480 and 481 are formed by forming a plurality of openings 180 and 181 in the passivation layer 150 (see above regarding the Figure 4 ), and various components using MIM capacitors 450 (see above for Figure 5-8This is an inherent result of filling the plurality of openings 180 and 181 (discussed in the foregoing). For example, the conductive layer segment 210C and the insulating layer segment 280C of the MIM capacitor 450 each include portions that substantially inherit the cross-sectional profile of the plurality of openings 180 and 181. The portions of the conductive layer segment 310C of the MIM capacitor 450 that fill the plurality of openings 180 and 181 also have a plurality of long, sloped sidewalls.

[0074] The multiple downward protrusions 480 and 481 of the MIM capacitor 450 can also be represented by a depth 490, which corresponds to the distance between the bottommost surface of the conductive layer segment 210C and the upper surface of the passivation layer 150 (on which the conductive layer segment 210C is formed). In some embodiments, the depth 490 is in a range between about 0.5 microns and about 0.7 microns. MIM capacitors implemented without the unique process described herein typically have smaller depths, such that they have portions that can be considered vertical protrusions. The multiple downward protrusions of the MIM capacitor 450 can also be represented by the relative sizes of the depth 490 and the thickness 500 of the conductive layer segment 210A. For example, because the MIM capacitor 450 substantially protrudes downward, the depth 490 is substantially greater (e.g., several times greater) than the thickness 500 of the conductive layer segment 210A. In some embodiments, the depth 490 is in a range between about 400 nanometers and about 800 nanometers, and the thickness 500 is in a range between about 20 nanometers and about 70 nanometers. In some embodiments, the ratio between the depth 490 and the thickness 500 is in a range between about 5.7:1 and about 40:1.

[0075] It should be understood that the aforementioned ranges of values ​​for depth 490 (including the ratio between depth 490 and thickness 500) are not randomly selected, but rather, in some embodiments, are specifically configured to optimize device performance. For example, one benefit of the plurality of downward protrusions 480-481 is that they help increase the effective surface area of ​​MIM capacitor 450. In this regard, the plurality of angled side surfaces between conductive layer segment 210C and insulating layer segment 280C, as well as the plurality of angled side surfaces between conductive layer segment 310C and insulating layer segment 280C, enable the plurality of downward protrusions 480-481 and create additional surface area that would not exist in MIM capacitor 450 without the unique process flow described herein. The additional surface area provided by the plurality of downward protrusions 480-481 results in an increase in the capacitance of MIM capacitor 450 (which is desirable) rather than an increase in the lateral dimensions of IC device 100.

[0076] On the other hand, if the range for depth 490 is too small, it means that the plurality of downward protrusions 480 - 481 are not made large enough to achieve the maximum effective capacitance gain. In other words, a certain amount of surface area increase (and therefore capacitance increase) is unnecessarily "left on the table." On the other hand, if the range for depth 490 is too large, it means that passivation layer 150 must be thicker. This would result in a larger overall vertical dimension for IC device 100, which may be undesirable, as the overall vertical dimension of IC device 100 may have been previously determined. Furthermore, even if an increase in the thickness of passivation layer 150 is tolerable, it would still translate into a deeper trench fill process, which may present certain manufacturing difficulties. In other words, the plurality of openings 180 - 181 would have a larger aspect ratio (depth to width), making them more difficult to fill (through the various components of MIM capacitor 450) without trapping air bubbles or gaps therein. Therefore, it may also be undesirable to configure the range for depth 490 to be too small. Here, the above ranges regarding depth 490 (including its ratio to thickness 500) are configured so that the MIM capacitor 450 can achieve a sufficiently large increase in capacitance (due to the additional surface area obtained) while maintaining the same vertical dimension designations as originally intended and / or minimizing manufacturing difficulties or issues.

[0077] Figure 14 A simplified schematic partial plan view of a portion of an IC device 100 is shown to provide further illustration of various aspects of the present invention. For reasons of consistency and clarity, Figures 1 to 14 Identical components appearing in the same will be labeled the same. Please understand that although Figure 14 , but for simplicity, the outlines (eg, borders or frames) of the conductive layer 210 and the conductive layer 310 are shown in FIG. Figure 14 The various outlines of the insulating layer 280 are not shown.

[0078] like Figure 14 As shown, two example parts 510 and 511 are depicted. The parts 510 and 511 may be substantially identical to each other, and the IC device 100 may include a plurality of these parts in a repeating manner. It can be said that each part 510 or 511 includes the above reference Figures 2 to 13 The MIM capacitor structure discussed. Within each portion (e.g., portion 510), the conductive layer 210 and the conductive layer 310 may each have a rectangular top view profile. The area of ​​the conductive layer 210 may be slightly larger than the area of ​​the conductive layer 310, such that the multiple boundaries of the conductive layer 310 are surrounded by the multiple boundaries of the conductive layer 210. The multiple outlines of the multiple protrusions 480 / 481 are also depicted (corresponding to the above reference Figures 4 to 8Multiple locations of multiple openings discussed). Since multiple protrusions 480 / 481 are Figure 14 They are not directly visible in the top view of , so their outlines are drawn as dashed lines in this article.

[0079] In the illustrated embodiment, each of the plurality of protrusions 480 / 481 has a rectangular top-view profile, for example, a substantially square top-view profile, with each side having a dimension 520. The plurality of protrusions 480 / 481 may be separated or spaced apart from the rest of the top view by a distance 530. In some embodiments, the dimension 520 is within a range between approximately 0.15 microns and approximately 0.3 microns, and the distance 530 is within a range between approximately 0.15 microns and approximately 0.3 microns, and the ratio between the dimension 520 and the distance 530 is within a range between approximately 0.5:1 and approximately 2:1. This ratio range is configured to densely pack a sufficient number of the plurality of protrusions 480 / 481 on the IC device 100 to increase the amount of surface area (which in turn increases the capacitance of the MIM capacitor 450), while also ensuring that the plurality of protrusions 480 / 481 are not packed too close together to avoid the risk of electrical shorting and / or complicating the manufacture of the IC device 100.

[0080] Figure 14 Also shown are multiple top views of the plurality of conductive vias 420 and 421. In the illustrated embodiment, the plurality of conductive vias 420 and 421 are depicted as having a substantially rectangular (e.g., square) top view, but it should be understood that they may have other top view shapes in alternative embodiments. As described above, the conductive vias 420 are in direct physical contact with the conductive layer 210, but are spaced apart from the conductive layer 310. To further illustrate this physical characteristic, the conductive layer 310 outline surrounding the conductive vias 420 is as follows: Figure 14 Similarly, the conductive through-hole 421 is in direct physical contact with the conductive layer 310, but is spaced apart from the conductive layer 210. To further illustrate this physical characteristic, the outline of the conductive layer 210 surrounding the conductive through-hole 421 is shown in FIG. Figure 14 480 / 481 ). Note that a minimum distance 540 is also configured between the conductive via 421 and the closest one of the plurality of protrusions 480 / 481 . In some embodiments, the minimum distance 540 is greater than or equal to approximately 2 microns. This range of values ​​ensures that the conductive via 421 is sufficiently spaced from the plurality of protrusions 480 / 481 to prevent electrical shorts while also not wasting chip space.

[0081] Figure 14A conductive via 560 is further shown that is different from the conductive vias 420 and 421. For example, the conductive via 560 may be a logic via used to provide electrical connections to multiple logic devices on the IC component 100. In this regard, the conductive via 560 is not part of the MIM capacitor 450 and is not used to operate the MIM capacitor 450. For example, the conductive via 560 is surrounded by the multiple conductive layers 310 and 210 of the MIM capacitor 450, but the conductive via 560 is not electrically coupled to the conductive layer 210 or the conductive layer 310. This aspect is also shown in FIG. Figure 15 As shown in the figure, the Figure 15 is a simplified schematic partial cross-sectional view of the conductive through-hole 560 and some of its adjacent components. Figure 15 As shown, conductive vias 560 extend vertically through conductive layer dummy segments 210D, conductive layer dummy segments 310D, and insulating layer dummy segments 280D. These dummy segments 210D, 280D, and 310D are manufactured using the same manufacturing process as the remaining portions of conductive layer 210, insulating layer 280, and conductive layer 310, respectively. However, these dummy segments 210D, 280D, and 310D are not used as capacitor structures herein, and therefore are referred to as dummy segments. Dummy segments 210D, 280D, and 310D are physically and electrically separated from the remaining portions of conductive layer 210, insulating layer 280, and conductive layer 310, respectively.

[0082] The conductive through-hole 560 itself is also spaced apart from the nearest conductive layer 210. For example, Figure 14 Top view and Figure 15 As shown in both cross-sectional views of FIG and FIG, a distance 570 separates the conductive via 560 from the nearest conductive layer 210. In some embodiments, the distance 570 is greater than or equal to about 0.8 microns. This range of values ​​ensures that the conductive via 560 is sufficiently spaced from the nearest conductive layer 210 to avoid electrical shorting while not wasting chip space.

[0083] Return Reference Figure 14 , the plurality of protrusions 480 / 481 closest to the boundary of conductive layer 310 remain spaced apart from the boundary of conductive layer 310 by a distance 580. Simultaneously, the plurality of protrusions 480 / 481 closest to the boundary of conductive layer 210 remain spaced apart from the boundary of conductive layer 210 by a distance 590. Furthermore, the plurality of portions 510 and 511 are separated from each other (e.g., in terms of the spacing between their outermost conductive layers 210) by a distance 595. In some embodiments, distance 580 is greater than or equal to approximately 0.2 microns, distance 590 is greater than or equal to approximately 0.3 microns, and distance 595 is greater than or equal to approximately 0.8 microns. This range of values ​​ensures that the fabrication of the MIM capacitor (e.g., with respect to the plurality of protrusions 480 / 481) does not encounter manufacturing difficulties and effectively utilizes chip space within IC device 100.

[0084] Figure 16 is another simplified schematic partial plan view of a portion of IC device 100. Again, for reasons of consistency and clarity, Figures 1 to 16 Identical components that appear in the same will be marked as identical. Figure 16 , depicts multiple planar top views of multiple capacitor units, such as multiple capacitor units 600A, 600B, 600C, and 600D. The multiple capacitor units 600A to 600D may be located within the boundaries of the multiple conductive layers 310 and 210, and their boundaries may also be located within the boundaries of the multiple conductive layers 310 and 210. Figure 16 Indicated in the middle.

[0085] Each of the plurality of capacitor units 600A to 600D may include a portion of the MIM capacitor 450 discussed above. In more detail, each capacitor unit 600A may be configured to have a square top-view shape, with its plurality of boundaries 610 represented by a dashed box. Each of the plurality of capacitor units 600A to 600D has a horizontal dimension 630. Each of the plurality of capacitor units 600A to 600D also includes a corresponding one of the plurality of protrusions 480 / 481 discussed above. The plurality of boundaries of the plurality of protrusions 480 / 481 are also represented by a dashed box located within the plurality of boundaries 610 of the corresponding capacitor unit. Each protrusion 480 / 481 has a horizontal dimension 520 (also in FIG. Figure 14 ), and distance 530 (also shown in Figure 14 ) separate adjacent protrusions 480 / 481. In some embodiments, dimension 630 is within a range of about 0.3 microns to about 0.6 microns, dimension 520 is within a range of about 0.15 microns to about 0.3 microns, and distance 530 is within a range of about 0.15 microns to about 0.3 microns. These ranges are carefully configured to ensure that the dimensions of protrusions 480 / 481 are optimized to provide an increase in capacitance without causing any issues related to electrical shorts and / or manufacturing processing difficulties.

[0086] It should be understood that the corresponding capacitance for each of the plurality of capacitor units 600A-600D is fairly consistent because the dimensions (e.g., depth and width) of the plurality of protrusions 480 / 481 can be finely controlled across the IC device 100. Thus, the capacitance associated with the plurality of capacitor units 600A-600D can be unitized, which can be beneficial when determining how MIM capacitors should be implemented to suit different types of IC applications. For example, based on the capacitance requirements of a given IC application, it can be calculated how many capacitor units similar to the plurality of capacitor units 600A-600D should be implemented as part of the MIM capacitor of the present invention.

[0087] Please also understand that although the plurality of capacitor units 600A to 600D and the plurality of protrusions 480 / 481 therein are depicted as having a substantially square top view profile, other embodiments may implement alternative shapes or profiles. For example, Figure 17A and 17B Two such non-limiting examples are shown in FIG. Figure 17A A top view of a plurality of capacitor cells 650 is shown, wherein each capacitor cell 650 has a substantially rectangular top-view shape. Within each capacitor cell 650, a protrusion 660 is implemented. Protrusion 660 is similar to the plurality of protrusions 480 / 481 discussed above. For example, in a cross-sectional view, protrusion 660 would also protrude vertically downward into the passivation layer (e.g., passivation layer 150 discussed above) because it comprises an insulating layer segment sandwiched between two conductive layer segments that together fill an opening or trench. The opening or trench is configured to have a rectangular top-view profile, and therefore, protrusion 660 would correspondingly inherit this rectangular top-view profile.

[0088] Similarly, Figure 17B A top view of a plurality of capacitor cells 680 is shown, wherein each capacitor cell 650 has a substantially circular top-view shape. Within each capacitor cell 680, a protrusion 690 is implemented. Protrusion 690 is also similar to the plurality of protrusions 480 / 481 discussed above. For example, in the cross-sectional view, protrusion 690 also protrudes vertically downward into the passivation layer (e.g., passivation layer 150 discussed above) because it comprises an insulating layer segment sandwiched between two conductive layer segments that together fill an opening or trench. The opening or trench is configured to have a circular top-view profile, and therefore, protrusion 660 will correspondingly inherit the circular top-view profile.

[0089] Other suitable top view profiles are also contemplated, but for simplicity they are not specifically depicted herein.

[0090] Figure 18 An integrated circuit manufacturing system 900 according to various embodiments of the present invention is shown, which can be used to manufacture the IC device 100 of the present invention discussed above. Manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916, ..., N connected via a communication network 918. Network 918 can be a single network or can be multiple different networks, such as an intranet and the Internet, and can include both wired and wireless communication channels.

[0091] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer who monitors a product of interest; entity 906 represents an engineer, such as a process engineer who controls processes and related recipes, or an equipment engineer who monitors or adjusts the conditions and settings of processing tools; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor process tool, such as an extreme ultraviolet tool for performing photolithography processes; entity 912 represents a virtual metrology module associated with process tool 910; entity 914 represents a high-level process control module associated with process tool 910 and other process tools; and entity 916 represents a sample module associated with process tool 910.

[0092] Each entity may interact with other entities and may provide integrated circuit manufacturing, process control and / or computing capabilities to other entities and / or receive such capabilities from other entities. Each entity may also include one or more computer systems for performing calculations and performing automation. For example, the high-level process control module of entity 914 may include a plurality of computer hardware having programmed software instructions therein. The computer hardware may include a hard disk, a flash drive, a read-only memory optical disk, a random access memory, a display device (e.g., a monitor), and input / output devices (e.g., a mouse and keyboard). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

[0093] The integrated circuit manufacturing system 900 enables interaction between multiple entities for integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In one embodiment, advanced process control includes adjusting process conditions, settings, and / or recipes of a process tool applied to an associated wafer based on metrology results.

[0094] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of the subset of processed wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0095] One capability provided by IC manufacturing system 900 is to enable collaboration and information access in areas such as design, engineering and process, metrology, and advanced process control. Another capability provided by IC manufacturing system 900 is to integrate systems across facilities, such as metrology tools and process tools. This integration enables facilities to coordinate their activities. For example, integrating metrology tools and process tools allows manufacturing information to be more efficiently incorporated into manufacturing flows or advanced process control modules, and wafer data from in-line or field measurements can be integrated with metrology tools integrated into related processes.

[0096] Figure 19 FIG. 1 is a flow chart of a method 1000 according to an embodiment of the present invention. The method 1000 includes step 1010 , forming a passivation layer over an interconnect structure.

[0097] The method 1000 includes step 1020 of etching an opening at least partially through the passivation layer.

[0098] The method 1000 includes step 1030 of depositing a first conductive layer over the passivation layer. The first conductive layer partially fills the opening.

[0099] The method 1000 includes step 1040 of depositing an insulating layer over the first conductive layer. The insulating layer partially fills the opening.

[0100] The method 1000 includes step 1050 of depositing a second conductive layer over the insulating layer. The second conductive layer completely fills the opening.

[0101] The method 1000 includes step 1060 of forming a first conductive structure electrically coupled to the first conductive layer and forming a second conductive structure electrically coupled to the second conductive layer.

[0102] In some embodiments, the opening is partially but not completely etched through the passivation layer.

[0103] In some embodiments, the passivation layer is a first passivation layer. The opening is a first opening. In some embodiments, the method further includes a plurality of steps performed before, during, or after the plurality of steps 1010 to 1060. For example, after depositing the second conductive layer, method 1000 may include etching a second opening through a segment of the second conductive layer outside the first opening but not through the insulating layer and the first conductive layer. Method 1000 may further include forming a second passivation layer above the second conductive layer. The second passivation layer fills the second opening. In some embodiments, forming the first conductive structure includes etching a third opening through the second passivation layer, the second conductive layer, the insulating layer, the first conductive layer, and the first passivation layer. The second opening is disposed between the first opening and the third opening. The method may further include filling the third opening with a conductive material electrically coupled to the first conductive layer. In some embodiments, the interconnect structure includes at least a first metal interconnect component and a second metal interconnect component. In some embodiments, the third opening is etched to expose a top surface of the first metal interconnect component. In some embodiments, the conductive material filling the third opening is formed directly on the first metal interconnect component. In some embodiments, the method may further include forming a conductive pad directly on the conductive material filling the third opening, such that the conductive pad is electrically coupled to the first conductive layer rather than to the second conductive layer.

[0104] In some embodiments, the opening is a first opening. In some embodiments, the method further includes steps performed before, during, or after the plurality of steps 1010 to 1060. For example, the method further includes, after depositing the first conductive layer but before depositing the insulating layer, etching a second opening through a segment of the first conductive layer outside the first opening. The deposition of the insulating layer and the deposition of the second conductive layer fill the second opening. In some embodiments, the passivation layer is a first passivation layer. In some embodiments, forming the second conductive structure includes: forming a second passivation layer above the second conductive layer; etching a third opening through the second passivation layer, the second conductive layer, the insulating layer, the first conductive layer, and the first passivation layer, wherein the second opening is disposed between the first opening and the third opening; and filling the third opening with a conductive material electrically coupled to the second conductive layer. In some embodiments, the interconnect structure includes at least a first metal interconnect component and a second metal interconnect component. In some embodiments, the third opening is etched to expose a top surface of the second metal interconnect component. In some embodiments, the conductive material filling the third opening is formed directly on the second metal interconnect component. In some embodiments, method 1000 may further include forming a conductive pad directly on the conductive material filling the third opening, such that the conductive pad is electrically coupled to the second conductive layer rather than to the first conductive layer.

[0105] In some embodiments, the first conductive layer, the insulating layer, and the second conductive layer collectively form a first metal-insulator-metal (MIM) capacitor structure. The method further includes forming a second MIM capacitor structure above the first MIM capacitor structure.

[0106] It should be understood that additional processes may be performed before, during, or after steps 1010 to 1060 of method 1000. For example, the first conductive layer, the insulating layer, and the second conductive layer may collectively form a first metal-insulator-metal (MIM) capacitor structure. Method 1000 may further include forming a second MIM capacitor structure above the first MIM capacitor structure. Method 1000 may further include forming a plurality of components of the interconnect structure or a plurality of transistors of the circuit.

[0107] In summary, the present invention relates to a unique manufacturing process for forming a MIM capacitor having multiple protruding portions embedded in a passivation layer. For example, an opening is etched in the passivation layer, and a first conductive layer, an insulating layer, and a second conductive layer are deposited to fill the opening. The MIM capacitor is formed by the first conductive layer, the insulating layer, and the second conductive layer (for example, as two electrode plates with a dielectric sandwiched therebetween). The portion of the MIM capacitor that protrudes downward into (and is embedded in) the passivation layer is an inherent result of the unique manufacturing process performed herein. For example, if no openings were etched into the passivation layer, the MIM capacitor would not have multiple downward protruding portions embedded in the passivation layer.

[0108] The MIM capacitor of the present invention offers several advantages. However, it should be understood that other embodiments may offer additional advantages, not all of which are necessarily disclosed herein, and not all embodiments require a particular advantage. One advantage is increased capacitance. More specifically, the capacitance of a capacitor is directly related to the surface area between the dielectric material and the conductive electrode plates located between the dielectric material. Other types of MIM capacitors typically increase their capacitance by expanding their lateral dimensions. Unfortunately, this comes at the cost of valuable IC chip space. In contrast, the MIM capacitor of the present invention utilizes multiple downwardly projecting portions embedded in the underlying passivation layer to create additional surface area between the insulating layer and the multiple conductive layers. Therefore, the MIM capacitor of the present invention can achieve more capacitance without requiring additional IC chip space, which is desirable. Another advantage is that the additional capacitance achieved by forming multiple portions of the MIM capacitor in the passivation layer is fairly consistent, easy to calculate, and therefore unitized. In other words, if a certain IC application requires a certain capacitance, it can be pre-determined how many MIM capacitor units (e.g., corresponding to the multiple downwardly projecting portions) are required to achieve that capacitance. Other advantages include compatibility with existing manufacturing and / or packaging processes, so the invention requires no additional processes and is therefore easy and cheap to implement.

[0109] Therefore, the present invention provides a device. The device includes an interconnect structure. A first passivation layer is disposed above the interconnect structure. A recess is disposed within the first passivation layer. A first conductive layer is disposed above the interconnect structure and partially within the recess. An insulating layer is disposed above the first conductive layer and partially within the recess. A second conductive layer is disposed above the insulating layer. The second conductive layer completely fills the recess. A second passivation layer is disposed above the second conductive layer.

[0110] The present invention also provides a device. The device includes a first passivation layer disposed above an interconnect structure. The device includes a second passivation layer disposed above the first passivation layer. The device further includes a metal-insulator-metal capacitor disposed between the first passivation layer and the second passivation layer. The metal-insulator-metal capacitor includes a downwardly protruding portion that at least partially protrudes through the first passivation layer.

[0111] The present invention further provides a method. A passivation layer is formed over an interconnect structure. An opening is etched at least partially through the passivation layer. A first conductive layer is deposited over the passivation layer. The first conductive layer partially fills the opening. An insulating layer is deposited over the first conductive layer. The insulating layer partially fills the opening. A second conductive layer is deposited over the insulating layer. The second conductive layer completely fills the opening. A first conductive structure electrically coupled to the first conductive layer is formed. A second conductive structure electrically coupled to the second conductive layer is formed.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Interconnect structure; a first passivation layer disposed above the interconnect structure; a recess disposed in the first passivation layer; a first conductive layer disposed over the interconnect structure and partially within the recess; an insulating layer disposed over the first conductive layer and partially within the recess; a second conductive layer disposed above the insulating layer, wherein the second conductive layer completely fills the recess; as well as A second passivation layer is disposed above the second conductive layer.

2. The semiconductor device according to claim 1, wherein The second passivation layer and the first passivation layer have different material compositions.

3. The semiconductor device according to claim 1, wherein Further including: a first conductive through-via extending through the second passivation layer, the second conductive layer, the insulating layer, the first conductive layer, and the first passivation layer, wherein the first conductive through-via is electrically coupled to the first conductive layer disposed in the recess but not to the second conductive layer disposed in the recess; as well as a second conductive through-hole extending through the second passivation layer, the second conductive layer, the insulating layer, the first conductive layer, and the first passivation layer, wherein the second conductive through-hole is electrically coupled to the second conductive layer configured in the recess rather than to the first conductive layer configured in the recess.

4. The semiconductor device according to claim 3, wherein in: a portion of the second passivation layer disposed between the recess and the first conductive through-hole having a downward protrusion extending through a segment of the second conductive layer rather than through the insulating layer or the first conductive layer; as well as A portion of the second conductive layer disposed between the recess and the second conductive through-hole has a downward protrusion, which extends through the insulating layer and the first conductive layer rather than through the first passivation layer.

5. The semiconductor device according to claim 1, wherein The first conductive layer, the insulating layer, and the second conductive layer together form a first metal-insulator-metal capacitor, and the device further includes a second metal-insulator-metal capacitor at least partially disposed above the second passivation layer.

6. The semiconductor device according to claim 5, wherein The first metal capacitor has a rectangular top-view outline or a circular top-view outline.

7. The semiconductor device according to claim 1, wherein in: The first conductive layer and the second conductive layer include titanium nitride; and The insulating layer includes hafnium oxide or zirconium oxide.

8. A semiconductor device, characterized in that: include: a first passivation layer disposed above the interconnect structure; a second passivation layer disposed above the first passivation layer; as well as A metal-insulator-metal capacitor is disposed between the first passivation layer and the second passivation layer, wherein the metal-insulator-metal capacitor includes a downwardly protruding portion at least partially protruding through the first passivation layer.

9. The semiconductor device according to claim 8, wherein in: The metal-insulator-metal capacitor comprises a first conductive layer, an insulating layer disposed above the first conductive layer, and a second conductive layer above the insulating layer; as well as The second conductive layer includes a further downwardly protruding portion that is in direct contact with the insulating layer and a plurality of side surfaces of the first conductive layer.

10. The semiconductor device according to claim 8, wherein in: The metal-insulating-layer metal capacitor is a first metal-insulating-layer metal capacitor; The device further includes a second metal-insulator-metal capacitor disposed above the first metal-insulator-metal capacitor; and The second metal insulating layer metal capacitor lacks a downwardly protruding portion.

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