Multi-channel alternating current stimulation system based on FPGA (Field Programmable Gate Array)

Abstract

The utility model belongs to the technical field of electrical stimulation, and particularly relates to a multi-channel alternating current electrical stimulation system based on an FPGA (Field Programmable Gate Array), which comprises an upper computer used for inputting a stimulation protocol; a plurality of signal output channels are configured on the FPGA development board, and the FPGA development board is connected with the upper computer to receive the stimulation protocol and generate stimulation waveforms of the signal output channels; the crystal oscillator is connected with the FPGA development board and controls the FPGA development board to generate a reference driving clock; the analog daughter cards are provided with DAC chips which are respectively connected with the signal output channels and the crystal oscillators; the crystal oscillator is matched with the reference driving clock to drive the DAC chip and receive the stimulation waveform sent by the corresponding signal output channel at the same time; and the DAC chip is used for converting the stimulation waveform into an electrical stimulation signal and outputting the electrical stimulation signal through the output port.

Description

Technical Field

[0001] The utility model belongs to the technical field of electric stimulation, and in particular relates to a multi-channel alternating current electric stimulation system based on FPGA. Background Art

[0002] In the field of EEG, temporal interference (TI) is a special AC electrical stimulation method that requires the stimulation signals generated simultaneously by multiple electrode channels to be superimposed on a specific position of the brain to form a deeply focused electrical stimulation. Its specific implementation method is to make multiple stimulation electrodes simultaneously output medium-frequency sinusoidal currents with small frequency difference and phase difference and the same amplitude. These currents are superimposed or offset with each other at certain moments due to interference, thereby generating a low-frequency envelope waveform that fluctuates in size in the time domain. This waveform is used to stimulate neurons deep in the brain to achieve transcranial therapeutic effects. In other words, in order to ensure that the currents of each stimulation electrode accurately interfere in the time domain and generate an envelope waveform, temporal interference stimulation is particularly sensitive to the temporal synchronization of electrical stimulation between channels.

[0003] In addition, existing transcranial electrical stimulation devices are mostly composed of low-cost, low-power MCU main control chips and peripheral analog circuits. However, due to the limitation that MCU can only adopt a single-task mechanism, synchronization between stimulation channels and high-precision frequency differences cannot be achieved in the development of high-precision time interference stimulation scenarios. Utility Model Content

[0004] The utility model provides a multi-channel alternating current electric stimulation system based on FPGA, which supports multi-channel synchronous time interference electric stimulation.

[0005] In order to solve the above technical problems, the utility model provides a multi-channel AC electric stimulation system based on FPGA, including: a host computer, on which a human-computer interaction operation interface is provided for inputting stimulation protocols; an FPGA development board, on which several signal output channels are configured, and the FPGA development board is connected to the host computer to receive the stimulation protocol and generate stimulation waveforms for each signal output channel; a crystal oscillator, connected to the FPGA development board and controlling it to generate a reference drive clock; several analog sub-cards, on which DAC chips are respectively connected to the signal output channels and the crystal oscillator; the crystal oscillator cooperates with the reference drive clock to drive the DAC chip and simultaneously receive the stimulation waveform sent by the corresponding signal output channel; the DAC chip is used to convert the stimulation waveform into an electrical stimulation signal and output it through the output port.

[0006] Furthermore, the signal output channel is connected to the SDIN pin and the SYNC pin of the DAC chip; and the crystal oscillator is connected to the SCLK pin of the DAC chip.

[0007] Furthermore, the SDIN pin and the SYNC pin are driven by the reference drive clock; and the SCLK pin is directly driven by the crystal oscillator.

[0008] Furthermore, the wiring length between the signal output channel and the SDIN pin and the SYNC pin is equal to the wiring length between the crystal oscillator and the SCLK pin.

[0009] Furthermore, the FPGA development board also includes: a phase-locked loop, connected to the crystal oscillator, and the crystal oscillator generates the reference drive clock through the phase-locked loop; the phase-locked loop is provided with a phase modulation unit for adjusting the phase of the reference drive clock to the phase of the crystal oscillator.

[0010] Furthermore, the FPGA development board also includes: a signal generator connected to the signal output channel and configured to generate the stimulation waveform according to the stimulation protocol; a multiplier connected to the signal generator and configured to control the amplitude step value of the stimulation waveform.

[0011] Furthermore, the multi-channel AC stimulation system also includes: a host, which is communicatively connected to the host computer and connected to the FPGA development board, and is used to transparently transmit the stimulation protocol issued by the host computer to the FPGA development board and report the stimulation information of the FPGA development board to the host computer; the FPGA development board is connected to the host via PCIe.

[0012] Furthermore, the analog daughter card is connected to the signal output channel via an SPI interface, and is equipped with an ADC chip, which is used to perform impedance detection and current monitoring on the signal output channel.

[0013] Furthermore, the DAC chip also includes: a RESET pin, the FPGA development board is connected to the RESET pin of the DAC chip, and is used to initialize and reset the DAC chip; a VOUT pin, the output port is connected to the VOUT pin of the DAC chip, and is used to output an electrical stimulation signal.

[0014] Furthermore, the output ports are configured as electrodes corresponding one to one with the DAC chips, so that the electrical stimulation signals are synchronously superimposed to form a time-interference electrical stimulation waveform.

[0015] The beneficial effects of the present invention are as follows: the present invention uses an FPGA development board to receive the stimulation protocol from the host computer and generate stimulation waveforms for each signal output channel; uses a crystal oscillator to connect to the FPGA development board and control it to generate a reference drive clock; uses a DAC chip connected to the signal output channel and the crystal oscillator respectively, so that the crystal oscillator cooperates with the reference drive clock to drive the DAC chip to simultaneously receive the stimulation waveform sent by the corresponding signal output channel; and the DAC chip is used to convert the stimulation waveform into an electrical stimulation signal. The present invention utilizes the parallel processing method of the FPGA development board to simultaneously generate stimulation waveforms for each stimulation channel, and uses the crystal oscillator in conjunction with the reference drive clock to efficiently control the timing to accurately ensure that multiple DAC chips synchronously receive the stimulation waveform and output the electrical stimulation signal.

[0016] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The objectives and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0017] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the specific implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 This is a principle block diagram of the multi-channel AC electric stimulation system of the present utility model.

[0020] Figure 2 This is a circuit schematic diagram of the DAC chip of the present utility model.

[0021] Figure 3 This is a schematic diagram of the pin connections between the FPGA development board and the DAC chip of the present invention. DETAILED DESCRIPTION

[0022] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0023] Example

[0024] See Figure 1-Figure 3 This embodiment provides a multi-channel AC electric stimulation system based on FPGA, including: a host computer, on which a human-computer interaction operation interface is provided for inputting a stimulation protocol; an FPGA development board, on which a plurality of signal output channels are configured, the FPGA development board is connected to the host computer to receive the stimulation protocol and generate a stimulation waveform for each signal output channel; a crystal oscillator, connected to the FPGA development board and controlling it to generate a reference driving clock for signal output; a plurality of analog sub-cards, on which DAC chips are respectively connected to the signal output channel and the crystal oscillator; the crystal oscillator cooperates with the reference driving clock to drive the DAC chip and simultaneously receive the stimulation waveform sent by the corresponding signal output channel; the DAC chip is used to convert the stimulation waveform into an electrical stimulation signal and output it through the output port.

[0025] Optionally, the host computer is provided with a human-computer interaction interface, including a display screen and a setting interface displayed on the display screen, for users to customize and input stimulation protocols; wherein the stimulation protocol includes: stimulation waveform type, number of stimulation channels, current, voltage, frequency information of each stimulation channel, etc. Optionally, each channel is controlled by an independent current source, and the phase, DC bias, and stimulation output can be controlled after the stimulation protocol is set separately, increasing the flexibility of waveform generation to adapt to different experimental designs and treatment needs. In addition, the host computer is connected to each module of the slave computer, and has functions such as controlling the stimulation protocol and issuing various instructions, impedance detection, and current monitoring and display, which are further explained later.

[0026] Optionally, the multi-channel AC stimulation system of the present invention further includes a host computer, serving as an intermediate component between a host computer and the FPGA development board. The host computer communicates with the host computer via Ethernet and connects to the FPGA development board via PCIe to achieve high-speed serial point-to-point dual-channel, high-bandwidth transmission. Specifically, the stimulation protocol issued by the host computer is processed by the host computer and transparently transmitted to the FPGA development board. The stimulation information, monitoring information, impedance, and current values ​​of the FPGA development board are then calculated and processed by the host computer and reported to the host computer.

[0027] It should be noted that the FPGA development board, as the main control chip of this system, includes: a signal generator, which is configured to generate a stimulation waveform according to the received stimulation protocol; several signal output channels, which are connected to the signal generator. After receiving instructions such as the stimulation protocol, the signal generator generates a stimulation waveform and sends it to each signal output channel for output. It is also a transmission medium for the FPGA development board to directly control multiple analog daughter cards (including ADC chips, DAC chips and peripheral circuits); a phase-locked loop, which is connected to an external crystal oscillator. The crystal oscillator generates a reference drive clock through the phase-locked loop. In addition, the phase-locked loop is provided with a phase modulation unit for adjusting the phase of the reference drive clock to the phase of the crystal oscillator; a multiplier, which is connected to the signal generator and is configured to control the amplitude step value of the stimulation waveform.

[0028] Optionally, the FPGA development board adopts but is not limited to models such as Xilinxxc7k325tffg676-2, and can be developed and configured using the Verilog language, and the stimulation waveform is generated according to the stimulation protocol through the DDS IP core. Preferably, the stimulation waveform is a digital signal of alternating current. In an optional embodiment, the stimulation waveform generated by the signal generator is a sinusoidal digital signal with a sampling rate of 1Msps, a frequency accuracy of 0.0001Hz, a frequency step value of 0.001Hz, a phase step value of 0.01°, an amplitude step value of 0.1uA, and a spurious-free dynamic range of 96dBm, which can be processed to achieve high-precision time interference electrical stimulation. The way FPGA processes multiple subtasks in parallel can improve computing efficiency, and module parallelization is achieved by inserting triggers and disassembling loops through combinational logic, thereby ensuring the output of stimulation signals with high-precision frequency differences.

[0029] Optionally, the analog daughter card is equipped with several DAC chips and high-sampling-rate ADC chips. The DAC chip is connected to the signal output channel one-to-one via the SPI interface, and is used to convert the stimulation waveform (digital signal) of each signal output channel from the FPGA development board into an electrical stimulation signal (analog signal); the ADC chip is used to perform impedance detection and current monitoring on the signal output channel. For example, it measures the voltage across the impedance of a fixed resistor on the signal output channel to obtain the current in the path, and measures the voltage value at the front end of the final output signal to obtain the stimulation voltage of the channel. The analog daughter card is connected to the signal output channel via the SPI interface to transmit the impedance and current information collected by the ADC chip back to the FPGA development board, and then it can be uploaded to the host computer to ensure the synchronization of information of each module. It should be noted that, if Figure 1 This SPI interface is different from the SPI interface connecting the DAC chip and the signal output channel. Optionally, the ADC chip uses, but is not limited to, an analog-to-digital conversion chip such as AFE948 or ADX923.

[0030] Optionally, the output port is connected to a DAC chip to amplify and regulate the voltage of the electrical stimulation signal converted by the DAC chip and output the electrical stimulation. For example, using four analog daughter cards, each equipped with eight DAC chips and three ADC chips, the device is equipped with four output ports, each supporting eight stimulation outputs, thus achieving 32 electrical stimulation outputs. For example, the output port is a stimulation electrode patch that fits the surface of the brain.

[0031] As an optional implementation of DAC chip circuit design.

[0032] The circuit diagram of the DAC chip of this embodiment is as follows: Figure 2 As shown, the chip's SDIN, SYNC, SCLK, and RESET pins serve as input pins, and VOUT serves as an output pin. The SPI interface connecting the signal output channel, crystal oscillator, and DAC chip includes the SDIN, SYNC, and SCLK pins. Optionally, the SDIN and SYNC pins are directly connected to an FPGA development board, which controls the input of the stimulation waveform. The FPGA development board is connected to the RESET pin of the DAC chip to initialize and reset all DAC chips. The output port is connected to the VOUT pin of the DAC chip to output the electrical stimulation signal.

[0033] Optionally, the DAC chip uses, but is not limited to, a DAC82001 or other digital-to-analog converter chip. This chip is a single-channel 16-bit low-interference-noise, unbuffered voltage-output digital-to-analog converter with 16-bit performance (1-LSB DNL and 2-LSB INTL), low glitch pulse energy, and a 2.7V to 5.5V wide power supply.

[0034] 2.0V to VDD wide reference range, 250μA (at 5.0V) low power consumption, 3-wire serial peripheral SPI interface, frequency up to 50MHz, tiny 10-pin WSON package.

[0035] As an optional implementation of synchronously transmitting stimulation waveforms.

[0036] The pin connection method between the FPGA development board and the DAC chip is as follows Figure 3As shown in the figure, it's important to note that the crystal oscillator, as a stable frequency reference source, provides a precise time base for the device. It generates the reference drive clock for the FPGA development board through a phase-locked loop (PLL), enabling the output signal to automatically track the input signal. The SCLK pin is the drive clock pin for the DAC chip. The SCLK signal is an oscillating signal that tells the receiver (DAC chip) to sample the signal on the data line at the exact moment. SPI is a synchronous data bus that ensures perfect synchronization between the transmitter (FPGA development board) and receiver (DAC chip). The signal output channel is connected to the SDIN and SYNC pins of the DAC chip, which are driven by the reference drive clock. The crystal oscillator is connected to the SCLK pin of the DAC chip, and the SCLK pins of all DAC chips are directly driven by the crystal oscillator. If the SCLK pin is also driven by the FPGA development board's reference clock, its drive capability is lower than that of direct crystal oscillator drive. Furthermore, each SCLK pin connected to the FPGA development board requires a clock buffer chip, which increases circuit design complexity and design area, significantly reducing the synchronization of stimulus waveform transmission. Therefore, compared with the traditional method (where all SPI interfaces are connected to the FPGA development board and driven by the reference clock), the crystal oscillator-driven SCLK signal, combined with the reference clock to drive the SDIN and SYNC signals, more efficiently enables the DAC chip to simultaneously receive stimulus waveforms from all signal output channels. Furthermore, the wiring lengths between the signal output channels and the SDIN and SYNC pins are designed to be equal to the wiring lengths between the crystal oscillator and the SCLK pins, and also between the FPGA development board and the RESET pin. By ensuring equal lengths for the transmission lines of the delayed frequency signals on the FPGA development board and for the DAC control signals within the FPGA module, high hardware synchronization of the DAC chip is ensured.

[0037] Optionally, when the system is working, the FPGA development board configures the signal generator to generate a stimulation waveform according to the stimulus protocol issued; after receiving the start command, each signal output channel is started simultaneously at the rising edge of the reference drive clock. At this moment, the stimulation waveform is input from the signal stimulation channel to the DAC chip through the SDIN pin according to the SPI protocol. The SYNC signal completes the data update of the DAC chip at the rising edge of the same reference drive clock, ensuring a microsecond delay from the generation and transmission of the stimulation waveform to the DAC chip, thereby realizing multi-channel output of highly synchronized sinusoidal electrical stimulation signals.

[0038] Preferably, the stimulation waveform is configured as a time-interferometric electrical stimulation waveform. This method requires the host computer to adjust the output frequency of each stimulation channel to generate a stimulation electric field with frequency and phase differences in each stimulation area of ​​the brain through the electrode channel, forming a deeply focused electrical stimulation. The spatial depth of the stimulation is adjusted by adjusting the output current of each stimulation channel. Optionally, stimulation protocols for other AC or DC stimulation methods can also be used to generate corresponding waveforms.

[0039] In summary, the operation mode of the FPGA-based multi-channel AC electric stimulation system of the present invention is as follows: after the system is powered on, the FPGA development board controls all DAC chips through the RESET pin to perform initialization and reset operations; the stimulation protocol is input in the human-computer interaction interface of the host computer; the stimulation protocol is processed by the host and transmitted to the FPGA development board; the signal generator on the FPGA development board simultaneously generates stimulation waveforms according to the received stimulation protocol and sends them to each signal output channel to wait for the instruction output; after the system receives the start command, the DAC chip simultaneously receives the stimulation waveforms of each signal output channel through the SPI interface and immediately converts them into electric stimulation signals; finally, the electric stimulation signal is amplified and voltage-regulated and output through the output port. The system uses the parallel processing method of the FPGA development board to simultaneously generate stimulation waveforms for each stimulation channel, and uses the crystal oscillator in conjunction with the reference drive clock to efficiently control the timing to accurately ensure that multiple DAC chips synchronously receive the stimulation waveforms released by the FPGA development board and then output the electric stimulation signal, effectively meeting the technical requirements of multi-channel high synchronization receiving stimulation signals and releasing electric stimulation in the time interference electric stimulation scenario.

[0040] In the description of the embodiments of the present invention, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0041] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely to facilitate the description of this utility model and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is merely a logical functional division, and actual implementation may have other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not implemented.

[0043] Based on the above-mentioned ideal embodiment of the present invention, and in accordance with the above description, relevant personnel can make various changes and modifications without departing from the technical scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, but must be determined according to the scope of the claims.

Claims

1. A multi-channel AC stimulation system based on FPGA, characterized in that: include: A host computer, on which a human-computer interaction interface is provided for inputting stimulation protocols; An FPGA development board, on which a plurality of signal output channels are configured, the FPGA development board being connected to the host computer to receive a stimulation protocol and generate a stimulation waveform for each signal output channel; Crystal oscillator, connected to the FPGA development board and controls it to generate the reference drive clock; Several analog daughter cards, each equipped with a DAC chip connected to a signal output channel and a crystal oscillator; The crystal oscillator cooperates with the reference drive clock to drive the DAC chip and simultaneously receives the stimulation waveform sent by the corresponding signal output channel; The DAC chip is used to convert the stimulation waveform into an electrical stimulation signal and output it through the output port.

2. The multi-channel AC electrical stimulation system according to claim 1, characterized in that: The signal output channel is connected to the SDIN pin and the SYNC pin of the DAC chip; The crystal oscillator is connected to the SCLK pin of the DAC chip.

3. The multi-channel AC electrical stimulation system according to claim 2, characterized in that: The SDIN pin and the SYNC pin are driven by the reference drive clock; The SCLK pin is directly driven by the crystal oscillator.

4. The multi-channel AC electrical stimulation system according to claim 3, characterized in that: The wiring length between the signal output channel and the SDIN pin and the SYNC pin is equal to the wiring length between the crystal oscillator and the SCLK pin.

5. The multi-channel AC electrical stimulation system according to claim 1, characterized in that: The FPGA development board also includes: A phase-locked loop (PLL) is connected to the crystal oscillator, and the crystal oscillator generates the reference driving clock through the PLL; The phase-locked loop is provided with a phase modulation unit for adjusting the phase of the reference driving clock to the phase of the crystal oscillator.

6. The multi-channel AC electrical stimulation system according to claim 1, characterized in that: The FPGA development board also includes: a signal generator connected to the signal output channel and configured to generate the stimulation waveform according to the stimulation protocol; A multiplier is connected to the signal generator and is configured to control the amplitude step value of the stimulation waveform.

7. The multi-channel AC electrical stimulation system according to claim 1, characterized in that: Also includes: A host computer is connected to the host computer and the FPGA development board, and is used to transmit the stimulation protocol issued by the host computer to the FPGA development board and report the stimulation information of the FPGA development board to the host computer; The FPGA development board is connected to the host via PCIe.

8. The multi-channel AC electrical stimulation system according to claim 7, characterized in that: The analog daughter card is connected to the signal output channel via an SPI interface and is equipped with an ADC chip. The ADC chip is used to perform impedance detection and current monitoring on the signal output channel.

9. The multi-channel AC electrical stimulation system according to claim 1, characterized in that: The DAC chip further includes: RESET pin, the FPGA development board is connected to the RESET pin of the DAC chip, and is used to initialize and reset the DAC chip; VOUT pin, the output port is connected to the VOUT pin of the DAC chip and is used to output the electrical stimulation signal.

10. The multi-channel AC electrical stimulation system according to claim 1, characterized in that: The output ports are configured as electrodes corresponding one to one with the DAC chips, so that the electrical stimulation signals are synchronously superimposed to form a time-interference electrical stimulation waveform.

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