Chip and consumable box

Abstract

The utility model relates to a chip and a consumable box, comprising an original chip substrate and a regeneration wafer installed on the original chip substrate, the original chip substrate is provided with a first function terminal and a second function terminal, the second function terminal is electrically connected to the regeneration wafer, the original chip substrate is provided with a first lead, the first lead is electrically connected to the regeneration wafer, and the second lead is electrically connected to the regeneration wafer. The two ends of the first wire are electrically connected with the first function terminal and the second function terminal respectively, so that the first function terminal is electrically connected to the regeneration wafer through the second function terminal.

Description

[0001] This application is a divisional application filed on October 25, 2023, with application number 202322877622X and invention name “A chip and consumable box”. Technical Field

[0002] The utility model relates to the field of chip transformation and reuse, in particular to a chip and consumable material box. Background Art

[0003] During normal printer operation, the printer's contact unit needs to work with the consumable cartridge chip to complete printing tasks. For example, the consumable cartridge chip can be an ink cartridge chip. This chip is mainly responsible for communication between the printer and the cartridge chip, ink cartridge color recognition, ink volume control, and data storage. The consumable cartridge can also be a toner cartridge or a toner cartridge.

[0004] A chip typically consists of three parts: a wafer, a substrate, and external components. One side of the substrate is equipped with contacts that connect to the printer's stylus pins, enabling signal communication between the chip and the printer. The other side of the substrate is equipped with corresponding circuits and solder points for connecting the wafer to external components.

[0005] It can be seen from this that the contacts and the substrate are fixedly connected, and the number is generally fixed. When the product is upgraded, the number of contacts required for the new generation of chips changes. The old chips can no longer be used and are then scrapped, forming non-degradable electronic waste and causing a lot of pollution to the environment. Utility Model Content

[0006] Based on this, it is necessary to provide a chip and consumables box to address the problem that the old version of the chip can no longer be used after the product is upgraded.

[0007] A chip includes an original chip substrate and a regenerated wafer mounted on the original chip substrate, wherein a first functional terminal and a second functional terminal are provided on the original chip substrate, and the second functional terminal is electrically connected to the regenerated wafer; a first wire is provided on the original chip substrate, and the two ends of the first wire are electrically connected to the first functional terminal and the second functional terminal respectively, so that the first functional terminal is electrically connected to the regenerated wafer through the second functional terminal.

[0008] The original chip substrate of the present invention is provided with a third functional terminal and a third wire, and the two ends of the third wire are electrically connected to the third functional terminal and the first functional terminal respectively, so that the third functional terminal is electrically connected to the regenerated wafer through the first functional terminal and the second functional terminal.

[0009] The surface of the original chip substrate of the present invention is covered with a first insulating layer, and the first conductive wire and the third conductive wire are separated by the first insulating layer.

[0010] The number of the first functional terminals of the present invention is at least two, and at least some of the first functional terminals have conducting ports.

[0011] The original chip substrate of the present invention is provided with a second wire, and both ends of the second wire are electrically connected to the second functional terminal and the regenerated wafer respectively, so that the second functional terminal is electrically connected to the regenerated wafer through the second wire;

[0012] The surface of the original chip substrate is covered with a first insulating layer. The first wire and the second wire are separated by the first insulating layer. The first wire is located on a side of the first insulating layer facing away from the original chip substrate.

[0013] In the present invention, the second functional terminal is electrically connected to only one first functional terminal via the first conductive wire.

[0014] A chip includes an original chip substrate and a regenerated wafer mounted on the original chip substrate, wherein a fifth functional terminal and a second functional terminal are provided on the original chip substrate, and a second wire and a fourth wire are provided on the original chip substrate, wherein the two ends of the second wire are electrically connected to the second functional terminal and the regenerated wafer respectively, so that the second functional terminal is electrically connected to the regenerated wafer through the second wire, and the two ends of the fourth wire are electrically connected to the fifth functional terminal and the regenerated wafer respectively, so that the fifth functional terminal is electrically connected to the regenerated wafer through the fourth wire, and the surface of the original chip substrate is covered with a first insulating layer and / or a third insulating layer, and the fourth wire and the second wire are separated by the first insulating layer and / or the third insulating layer.

[0015] A chip includes an original chip substrate and a regenerated wafer mounted on the original chip substrate, wherein a fourth wire and at least two fifth functional terminals are provided on the original chip substrate, wherein the fifth functional terminals are electrically connected to a conduction port, and the two ends of the fourth wire are respectively electrically connected to the conduction port and the regenerated wafer, and different conduction ports are disconnected.

[0016] The original chip substrate of the present invention is provided with a second functional terminal and a second wire, two ends of the second wire are electrically connected to the second functional terminal and the regenerated wafer respectively, and the second functional terminal does not have the conduction port.

[0017] A consumables box includes a chip.

[0018] The chip of the present invention uses the second functional terminal that does not need to contact the printer contact pin as a conductor, and converts the terminals that were originally unable to be electrically connected to the wafer into the first functional terminal at a lower cost. The terminals can be electrically connected to the regenerated wafer through the second functional terminal. The first functional terminal plays the role of information exchange between the printer contact pin and the regenerated wafer, thereby adapting to changes in the number and / or position of the contact pins after the printer is upgraded, avoiding the direct scrapping of old chips, and reducing environmental pollution and the upgrade cost of the printer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the main structure of the chip in prior art 1;

[0020] Figure 2 Schematic diagram of the top view of the chip in prior art 1;

[0021] Figure 3 This is a schematic diagram of the main structure of the chip after modification in Example 1 of the present utility model;

[0022] Figure 4 This is a schematic diagram of the top view of the chip after modification in Example 1 of the present utility model;

[0023] Figure 5 Schematic diagram of the top view of a five-terminal chip in the prior art;

[0024] Figure 6 This is a bottom view of the chip after modification in Example 2 of the present utility model;

[0025] Figure 7 Schematic diagram of the top view of the chip in prior art 2;

[0026] Figure 8 Schematic diagram of the top view of the chip after modification in Example 3 of the present utility model;

[0027] Figure 9 Schematic diagram of the top view of the chip in prior art 3;

[0028] Figure 10 This is a schematic diagram of the top view of the chip after modification in Example 4 of the present utility model;

[0029] Figure 11 This is a bottom view of the chip after modification in Example 1 of the present utility model;

[0030] Figure 12 This is a schematic diagram of the three-dimensional structure of the consumables box in Example 7 of the present utility model.

[0031] Reference numerals:

[0032] 1. Substrate; 10. Original chip substrate; 2. Wafer; 20. Regenerated wafer; 301. First terminal; 302. Second terminal; 303. Third terminal; 304. Fourth terminal; 305. Fifth terminal; 306. Sixth terminal; 307. Seventh terminal; 308. Eighth terminal; 309. Ninth terminal; 41. First functional terminal; 42. Second functional terminal; 43. Third functional terminal; 44. Fourth functional terminal; 45. Fifth functional terminal; 46. Sixth functional terminal; 51. First wire; 52. Second wire; 54. Fourth wire; 541. Conductive port; 601. Tenth terminal; 602. Eleventh terminal; 605. Twelfth terminal; 606. Thirteenth terminal; 609. Fourteenth terminal; 3011. Fifteenth terminal; 3091. Sixteenth terminal; 7. Resistor; 81. Chip; 82. Box body DETAILED DESCRIPTION

[0033] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the following detailed description of specific embodiments of the present invention is provided in conjunction with the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0034] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of this utility model, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0036] In this utility model, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on specific circumstances.

[0037] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0038] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only implementation methods.

[0039] The purpose of this utility model is to modify the old version chip so that the modified chip can be used in updated printers and adapt to the changes in the stylus pins in the printer, thereby avoiding the direct scrapping of the old version chip. After the printer is upgraded, the number of stylus pins may increase or decrease.

[0040] Prior art 1:

[0041] See also Figure 1-Figure 2 As a common old version chip before modification, it includes a substrate 1 and a wafer 2 mounted on the back of the substrate 1. The surface of the wafer 2 can be covered with vinyl for protection. The front of the substrate 1 is provided with several terminals. The terminals can be divided into fourth functional terminals 44 and second functional terminals 42 based on the electrical connection with the wafer 2. The second functional terminal 42 is electrically connected to the wafer 2, while the fourth functional terminal 44 is not electrically connected to the wafer 2.

[0042] If the old version chip is a nine-pin chip, the nine terminals are respectively referred to as first terminal 301, second terminal 302, third terminal 303, fourth terminal 304, fifth terminal 305, sixth terminal 306, seventh terminal 307, eighth terminal 308, and ninth terminal 309. Nine-pin chips are mainly used in printers with a nine-pin structure.

[0043] In accordance with some common existing printer specifications, the first terminal 301 serves as a first short-circuit detection terminal, the second terminal 302 serves as a CE reset terminal, the third terminal 303 serves as a CLK clock terminal, the fourth terminal 304 serves as a second short-circuit detection terminal, the fifth terminal 305 serves as a first high-voltage terminal, the sixth terminal 306 serves as a VDD power supply terminal, the seventh terminal 307 serves as a GND ground terminal, the eighth terminal 308 serves as a DATE data terminal, and the ninth terminal 309 serves as a second high-voltage terminal. In this prior art, the second terminal 302, the third terminal 303, the sixth terminal 306, the seventh terminal 307, and the eighth terminal 308 are all electrically connected (by means including but not limited to wires and vias) to the wafer 2. Therefore, the second terminal 302, the third terminal 303, the sixth terminal 306, the seventh terminal 307, and the eighth terminal 308 are all second functional terminals 42, while the first terminal 301, the fourth terminal 304, the fifth terminal 305, and the ninth terminal 309 are all fourth functional terminals 44. In conjunction with the above-mentioned terminal functions, three third wires (not shown in the figure) are also provided on the front of the substrate 1. The two ends of one of the third wires are respectively provided on the first terminal 301 and the fourth terminal 304 to electrically connect the first terminal 301 and the fourth terminal 304. The other two third wires are connected in series through the resistor 7 and then provided between the fifth terminal 305 and the ninth terminal 309, thereby forming a series conductive structure of the fifth terminal 305, the third wire, the resistor 7, the third wire and the ninth terminal 309, wherein the end of the third wire electrically connected to the resistor 7 is a conductive port. The front of the substrate 1 is coated with a first insulating layer. During the coating process, the first insulating layer avoids the various terminals so that all terminals are exposed to the first insulating layer. The first insulating layer covers all wires on the front of the substrate 1, including the third wire, thereby increasing safety and reducing the risk of short circuits.

[0044] Example 1:

[0045] This embodiment provides a chip obtained by modifying the old version chip in the prior art 1. The modified chip in this embodiment is mainly used for a printer with five contact pins.

[0046] See also Figure 3 、 Figure 4 and Figure 11The modified chip includes a substrate and a wafer mounted on the back of the substrate. Since the substrate in the prior art 1 was directly used during the modification process, and the wafer was replaced to accommodate the five-pin printer, the substrate of the modified chip is the original chip substrate 10, and the wafer is the replaced regenerated wafer 20. For ease of distinction, the term "substrate" specifically refers to the substrate before the chip is modified, the term "original chip substrate 10" specifically refers to the substrate after the chip is modified, the term "subsequent wafer" specifically refers to the wafer on the substrate before the chip is modified, and the term "regenerated wafer 20" specifically refers to the wafer on the original chip substrate 10 after the chip is modified.

[0047] The front surface of the original chip substrate 10 still retains the first terminal 301, the second terminal 302, the third terminal 303, the fourth terminal 304, the fifth terminal 305, the sixth terminal 306, the seventh terminal 307, the eighth terminal 308, the ninth terminal 309, and the first insulating layer. The regenerated wafer 20 is mounted on the original chip substrate 10 in the same position as the replaced wafer. The second terminal 302, the third terminal 303, the sixth terminal 306, the seventh terminal 307, and the eighth terminal 308 are all directly electrically connected to the regenerated wafer 20. Therefore, the second terminal 302, the third terminal 303, the sixth terminal 306, the seventh terminal 307, and the eighth terminal 308 still serve as the second functional terminals 42.

[0048] The main difference between the modified chip and the prior art 1 is that three first wires 51 are arranged on the side of the first insulating layer facing away from the original chip substrate 10, the two ends of the first first wire 51 are respectively arranged between the third terminal 303 and the ninth terminal 309, the two ends of the second first wire 51 are respectively arranged between the fourth terminal 304 and the eighth terminal 308, and the two ends of the third first wire 51 are respectively arranged between the fifth terminal 305 and the seventh terminal 307. Through the first wire 51, the fourth terminal 304 is electrically connected to the regenerated wafer 20 through the eighth terminal 308 (second functional terminal 42), the ninth terminal 309 is electrically connected to the regenerated wafer 20 through the third terminal 303 (second functional terminal 42), and the fifth terminal 305 is electrically connected to the regenerated wafer 20 through the seventh terminal 307 (second functional terminal 42). As a result, the fourth terminal 304, the ninth terminal 309, and the fifth terminal 305 are converted from fourth functional terminals to first functional terminals 41. The first functional terminal 41 is defined as a terminal electrically connected to the second functional terminal 42 through the first wire 51 and electrically connected to the regenerated wafer 20 through the second functional terminal 42. That is, the first functional terminal 41 is not directly electrically connected to the regenerated wafer 20, but needs to be electrically connected to the regenerated wafer 20 through another terminal.

[0049] In some other embodiments, the main difference between the modified chip and the prior art 1 may be that the first terminal 301 is electrically connected to the third terminal 303 via the first wire 51, the fifth terminal 305 is electrically connected to the eighth terminal 308 via the first wire 51, and the ninth terminal 309 is electrically connected to the seventh terminal 307 via the first wire 51. In other words, the first terminal 301, the fifth terminal 305, and the ninth terminal 309 are electrically connected to the regenerated wafer 20 via the third terminal 303, the seventh terminal 307, and the eighth terminal 308, respectively.

[0050] On the other hand, since the first terminal 301 was already electrically connected to the fourth terminal 304 via the third wire before the chip was modified, the first terminal 301 can only be electrically connected to the reconstituted wafer 20 through the third wire, the fourth terminal 304, the first wire 51, and the eighth terminal 308. Therefore, in this embodiment, the first terminal 301 is transformed into a third functional terminal 43, i.e., a terminal that requires at least two other terminals to be electrically connected to the reconstituted wafer 20. Correspondingly, for the modified chip, the two ends of the third wire are respectively provided at the third functional terminal 43 and the first functional terminal 41.

[0051] The five-terminal chip directly prepared in the prior art is as follows Figure 5 As shown, it only has the tenth terminal 601 , the eleventh terminal 602 , the twelfth terminal 605 , the thirteenth terminal 606 , and the fourteenth terminal 609 , and the size of the substrate 1 between the five-terminal chip and the nine-terminal chip is similar.

[0052] Among them, the positions of the tenth terminal 601 and the first terminal 301 on their respective substrates 1 are close to or consistent with the position of the eleventh terminal 602 on the substrate 1 and the position of the second terminal 302 on the original chip substrate 10 are close to or consistent with the position of the twelfth terminal 605 on the substrate 1 and the position of the fifth terminal 305 on the original chip substrate 10, the position of the thirteenth terminal 606 on the substrate 1 and the position of the sixth terminal 306 on the original chip substrate 10, and the position of the fourteenth terminal 609 on the substrate 1 and the position of the ninth terminal 309 on the original chip substrate 10 are close to or consistent with each other.

[0053] The tenth terminal 601, the eleventh terminal 602, the twelfth terminal 605, the thirteenth terminal 606, and the fourteenth terminal 609 serve as the DATE data terminal, the CE reset terminal, the CLK clock terminal, the VDD power supply terminal, and the GND ground terminal, respectively. Therefore, the tenth terminal 601, the eleventh terminal 602, the twelfth terminal 605, the thirteenth terminal 606, and the fourteenth terminal 609 are all electrically connected to the wafer and respectively contact and mate with the five stylus pins of the five-stylus printer. Therefore, the relative positions of the tenth terminal 601, the eleventh terminal 602, the twelfth terminal 605, the thirteenth terminal 606, and the fourteenth terminal 609 also match the relative positions of the five stylus pins. Correspondingly, the relative positions of the first terminal 301, the second terminal 302, the fifth terminal 305, the sixth terminal 306, and the ninth terminal 309 also match the relative positions of the five stylus pins.

[0054] After the modified nine-terminal chip of this embodiment is applied to a five-pin printer, the first terminal 301, the second terminal 302, the fifth terminal 305, the sixth terminal 306, and the ninth terminal 309 can contact the five pins respectively. Since the first terminal 301, the second terminal 302, the fifth terminal 305, the sixth terminal 306, and the ninth terminal 309 of the modified nine-terminal chip are all electrically connected to the regenerated wafer 20, the modified nine-terminal chip can be directly used as a five-terminal chip directly prepared in the prior art, thereby achieving the purpose of recycling the nine-terminal chip that is discarded during product iteration.

[0055] In this embodiment, in the modified nine-terminal chip, the third terminal 303, the fourth terminal 304, the seventh terminal 307, and the eighth terminal 308 do not need to contact the contact pins of the five-pin printer, but are used as wires, and cooperate with the third wire inherent in the original chip substrate 10 to maximize the secondary utilization of the conductive structure inherent in the nine-terminal chip, reduce the required length of the first wire 51, and thus reduce the modification cost of the nine-terminal chip.

[0056] Before the chip is modified, the fifth terminal 305 and the ninth terminal 309 in the prior art 1 are fourth functional terminals electrically connected through a resistor. During the chip modification process, in order to be converted into the first functional terminal 41, the fifth terminal 305 and the ninth terminal 309 not only need to be electrically connected to the regenerated wafer 20, but the resistor between the fifth terminal 305 and the ninth terminal 309 can also be removed, thereby avoiding direct electrical connection between the fifth terminal 305 and the ninth terminal 309.

[0057] It is particularly noteworthy that in this embodiment, the first terminal 301 is electrically connected to the regenerated wafer 20 through the third wire, the fourth terminal 304, the first wire 51, and the eighth terminal 308 in sequence, the second terminal 302 is directly electrically connected to the regenerated wafer 20, the fifth terminal 305 is electrically connected to the regenerated wafer 20 through the first wire 51 and the seventh terminal 307 in sequence, the sixth terminal 306 is directly electrically connected to the regenerated wafer 20, and the ninth terminal 309 is electrically connected to the regenerated wafer 20 through the first wire 51 and the third terminal 303 in sequence. As long as the original resistance between the fifth terminal 305 and the ninth terminal 309 is removed, it can be ensured that the five contact pins can realize signal transmission between the first terminal 301, the second terminal 302, the fifth terminal 305, the sixth terminal 306 and the ninth terminal 309 through relatively independent conductive paths and the regenerated wafer 20, thereby avoiding mutual interference between the signals of the five different contact pins and ensuring the stability of signal transmission between the modified nine-terminal chip and the five-contact pin printer.

[0058] The above-mentioned improvement in signal transmission stability requires that the second functional terminal 42 is electrically connected to only one first functional terminal 41 through the first wire 51, and that more than two first functional terminals 41 are avoided from being connected in parallel to the same second functional terminal 42, so as to prevent different contact pins from transmitting signals to the same second functional terminal 42 through different first functional terminals 41, so that different signals interfere with each other in the second functional terminal 42 before being transmitted to the regenerated wafer 20.

[0059] After the resistor between the fifth terminal 305 and the ninth terminal 309 is removed, the two third wires between the fifth terminal 305 and the ninth terminal 309 no longer serve to electrically connect the fifth terminal 305 and the ninth terminal 309. Consequently, the third wires are converted into electrical connection residues in the modified chip, and the conductive ports 541 of the third wires are retained. Thus, for the modified chip, the fifth terminal 305 and the ninth terminal 309 serve as the first functional terminals 41 and are electrically connected to the conductive ports 541. Furthermore, the conductive ports 541 on different first functional terminals 41 are disconnected from each other. In other words, if the resistor between the fifth terminal 305 and the ninth terminal 309 was soldered to the substrate 1 before removal, then after the resistor is removed, a pit or electrical opening will form on the surface of the original chip substrate 10 where the resistor was originally soldered, ultimately causing the electrical connection between the fifth terminal 305 and the ninth terminal 309 to be disconnected.

[0060] For the chip before modification, in some existing technologies, a portion of the third wire is located between the first insulating layer and the substrate 1. For the chip after modification, the first wire 51 is arranged on the side of the first insulating layer away from the original chip substrate 10. Therefore, for the third wire that has not been converted into an electrical connection residue after modification, it and the first wire 51 are separated on both sides of the first insulating layer, thereby directly realizing the separation between the first wire 51 and the third wire, avoiding the occurrence of a short circuit between the first wire 51 and the third wire. Therefore, the specific extension method of the first wire 51 during the chip modification process can ignore the third wire and match the terminal arrangement method on the surface of the substrate 1 in a more free and flexible manner.

[0061] In some prior art designs, a second wire 52 is provided on the substrate 1. The portion of the second wire 52 on the front of the substrate 1 is located between the substrate 1 and the first insulating layer. This wire, along with the third wire, was already on the substrate 1 before the chip was modified. Therefore, for the modified chip, the portion of the second wire 52 on the front of the original chip substrate 10 can also avoid the first wire 51 through the first insulating layer, thus preventing the second wire 52 from interfering with the routing of the first wire 51. The function of the second wire 52 is to electrically connect the second functional terminal 42 to the regenerated wafer 20. Its two ends are located on the second functional terminal 42 and the regenerated wafer 20, respectively.

[0062] During the modification process of a portion of the chips, the first insulating layer may be removed. In this case, during the modification process, the wiring process of the first wire 51 needs to avoid the second wire 52 and the third wire.

[0063] In some prior art, vias are provided on the second functional terminals 42. The wafer and the second functional terminals 42 are disposed on opposite sides of the substrate 1. The second functional terminals 42 are electrically connected to the wafer through the vias, thereby avoiding the need to provide the second wires 52 on the front side of the substrate 1. This completely eliminates the interference of the second wires 52 with the wiring pattern of the first wires 51 on the surface of the original chip substrate 10 during the chip modification process.

[0064] More preferably, after the chip modification is completed, a second insulating layer can be provided on the side of the first insulating layer facing away from the original chip substrate 10, so that the first wire 51 is located between the first insulating layer and the second insulating layer to avoid exposure of the first wire 51 and improve the safety of the modified chip.

[0065] This embodiment additionally provides a chip processing method to transform the old version chip in the prior art 1 into the chip of this embodiment. The chip processing method includes the following steps:

[0066] Step A1: Place the chip on a jig, and remove the wafer and the black glue on the surface of the substrate 1 by heating, softening, manual scraping, or scraping with an apparatus;

[0067] Step A2: removing the resistor between the fifth terminal 305 and the ninth terminal 309 to disconnect the fifth terminal 305 from the ninth terminal 309 and expose two conducting ports 541 electrically connected to the fifth terminal 305 and the ninth terminal 309 respectively;

[0068] Step A3: Clean the substrate 1 to expose all wafer pad contacts, thereby converting the substrate 1 into an original chip substrate 10;

[0069] Step A4: Using the COB process, a new regenerated wafer 20 is placed on the original chip substrate 10 so that the wafer pad contacts are electrically connected to the solder joints of the regenerated wafer 20;

[0070] Step A5: Laying out the first wire 51 so that the third terminal 303 is electrically connected to the ninth terminal 309 , the fourth terminal 304 is electrically connected to the eighth terminal 308 , and the fifth terminal 305 is electrically connected to the seventh terminal 307 . The first wire 51 can be made of a conductive material such as silver paste, copper paste, or carbon oil.

[0071] In some other embodiments, the layout of the first wire 51 can also be adjusted, as long as the first terminal 301, the fifth terminal 305 and the ninth terminal 309 are electrically connected to the regenerated wafer 20 using the third terminal 303, the seventh terminal 307 and the eighth terminal 308 respectively.

[0072] Methods for preparing the first conductive line 51 include, but are not limited to, welding copper wires, printing carbon oil or silver paste, and mounting conductive materials.

[0073] Step A6: Apply black glue on the new regenerated wafer 20 and place it in an oven for curing.

[0074] Example 2:

[0075] This embodiment also modifies the old version chip in the prior art 1 to obtain a modified chip.

[0076] See also Figure 2 and Figure 6The modified chip also includes the original chip substrate 10 and the regenerated wafer 20 mounted on the back of the original chip substrate 10. The modification process includes two parts. The first part is to remove the electrical connection between at least part of the fourth functional terminals 44, such as removing the resistor between the fifth terminal 305 and the ninth terminal 309. The second part is to make at least part of the fourth functional terminals 44 not pass through the second functional terminals 42, but directly electrically connected to the regenerated wafer 20, so that the fourth functional terminals 44 (the fifth terminal 305 and the ninth terminal 309 in this embodiment) are converted into fifth functional terminals. The fifth functional terminals are terminals that are not electrically connected to the wafer before the chip modification, and are electrically connected to the regenerated wafer 20 without relying on the second functional terminals 42 through the chip modification.

[0077] Since the contact pins in a five-pin printer are not electrically connected to the fourth terminal 304, the electrical connection between the fourth terminal 304 and the first terminal 301 does not need to be removed during the chip modification process. The first terminal 301 can still be electrically connected to the fourth terminal 304 via the third wire, and the fourth terminal 304 can be electrically connected to the third terminal 303, the seventh terminal 307, or the eighth terminal 308 via the first wire, thereby electrically connecting to the reconstituted wafer 20.

[0078] Thus, the first terminal 301, the second terminal 302, the fifth terminal 305, the sixth terminal 306, and the ninth terminal 309 (i.e., all fifth functional terminals, at least some of the first functional terminals, and at least some of the second functional terminals 42) can also be independently electrically connected to the regenerated wafer 20 and match the stylus position distribution of a five-stylus printer, thereby being suitable for a five-stylus printer. In one existing design, the resistor and the wafer are simultaneously provided on the back side of the substrate 1.

[0079] Before chip modification, a second wire 52 is also provided on the substrate 1, and the second functional terminal 42 is electrically connected to the wafer via the second wire 52. If the second wire 52 is partially located on the front surface of the substrate 1, it can be covered by the first insulating layer. After chip modification, a fourth wire 54 is provided on the original chip substrate 10. The ends of the fourth wire 54 are respectively provided on the fifth functional terminal and the regenerated wafer 20, so that the fifth functional terminal is electrically connected to the regenerated wafer 20 via the fourth wire 54. The end of the fourth wire 54 is electrically connected to the fifth functional terminal via the conductive port 541.

[0080] In this embodiment, the regenerated wafer 20 is located on the back of the original chip substrate 10, so the second wire 52 and the fourth wire 54 are at least partially located on the back of the original chip substrate 10. Based on this, during the modification process of the chip in this embodiment, a third insulating layer can be first coated on the back of the original chip substrate 10, and the third insulating layer can cover the portion of the second wire 52 on the back of the original chip substrate 10, and then the fourth wire 54 can be prepared. The third insulating layer can block the portions of the fourth wire 54 and the second wire 52 on the back of the original chip substrate 10 to improve safety.

[0081] If the third insulating layer is not provided, the second conductive wire 52 needs to be avoided during the routing of the fourth conductive wire 54 , or the second conductive wire 52 needs to be provided with an insulating coating.

[0082] This embodiment also provides a chip processing method for converting the old version chip in the prior art 1 into the chip of this embodiment. The chip processing method includes the following steps:

[0083] Step B1: Place the old chip on the jig and remove the wafer on the substrate and the black glue on the wafer surface by heating, softening, manual scraping or equipment scraping;

[0084] Step B2: removing the resistor between the fifth terminal 305 and the ninth terminal 309 to disconnect the fifth terminal 305 from the ninth terminal 309 and expose two conducting ports 541 electrically connected to the fifth terminal 305 and the ninth terminal 309 respectively;

[0085] Step B3: Clean the substrate and expose all wafer pad contacts to convert the substrate into an original chip substrate 10;

[0086] Step B4: using a COB process to place the regenerated wafer 20 on the original chip substrate 10 so that the wafer pad contacts are electrically connected to the solder joints of the regenerated wafer 20;

[0087] Step B5: Laying out the fourth wire 54 and the first wire so that the ninth terminal 309 and the fifth terminal 305 are both electrically connected to the regenerated wafer 20 through their respective fourth wires 54, and the fourth terminal 304 is electrically connected to the third terminal 303, the seventh terminal 307, or the eighth terminal 308 through the first wire, thereby being electrically connected to the regenerated wafer 20; the fourth wire 54 and the first wire can be made of conductive materials such as silver paste, copper paste, and carbon oil; the fifth terminal 305 and the ninth terminal 309 are both electrically connected to the corresponding end of the fourth wire 54 through their respective electrically connected conductive ports 541;

[0088] Methods for preparing the fourth conductive line 54 include, but are not limited to, welding copper wires, printing carbon oil or silver paste, and mounting conductive materials.

[0089] Step B6: Apply black glue on the regenerated wafer 20 and place it in an oven for curing.

[0090] Prior art 2:

[0091] See also Figure 7 This prior art provides a seven-terminal chip. Unlike prior art 1, it lacks the first and fourth terminals. Substrate 1 only has second terminal 302, third terminal 303, fifth terminal 305, sixth terminal 306, seventh terminal 307, eighth terminal 308, and ninth terminal 309. Similarly, fifth terminal 305 and ninth terminal 309 serve as fourth functional terminals 44, while second terminal 302, third terminal 303, sixth terminal 306, seventh terminal 307, and eighth terminal 308 serve as second functional terminals 42.

[0092] Example 3:

[0093] See also Figure 7 and Figure 8 In this embodiment, the seven-terminal chip in the prior art 2 is modified to obtain a modified chip. The modification method includes the following steps:

[0094] Step C1: Place the old chip on a jig, and remove the wafer on the substrate 1 and the black glue on the wafer surface by heating, softening, manual scraping, or scraping with a machine;

[0095] Step C2: Removing the resistor between the fifth terminal 305 and the ninth terminal 309 to electrically disconnect the fifth terminal 305 and the ninth terminal 309, exposing two conductive ports electrically connected to the fifth terminal 305 and the ninth terminal 309, respectively. A fifteenth terminal 3011 is formed on the front surface of the substrate 1 by welding, etching, or mounting. The position of the fifteenth terminal 3011 on the substrate 1 corresponds to the position of the first terminal in the prior art 1. The fifteenth terminal 3011 is the sixth functional terminal 46, which is a terminal newly welded to the substrate 1 during the chip modification process.

[0096] Step C3: cleaning the substrate 1 to expose all wafer pad contacts, so as to convert the substrate 1 into an original chip substrate 10;

[0097] Step C4: placing the regenerated wafer on the original chip substrate 10 using a COB process so that the wafer pad contacts are electrically connected to the solder points of the regenerated wafer;

[0098] Step C5: Laying a fifth wire and two fourth wires, wherein the two fourth wires are respectively arranged between the fifth terminal 305 and the regenerated wafer and between the ninth terminal 309 and the regenerated wafer, so that the ninth terminal 309 and the fifth terminal 305 are transformed from the fourth functional terminal 44 to the fifth functional terminal 45, wherein the fifth terminal 305 and the ninth terminal 309 are both electrically connected to the corresponding end of the fourth wire 54 through their respective electrically connected conductive ports;

[0099] Two ends of the fifth wire are respectively arranged between the fifteenth terminal 3011 and the regenerated wafer to achieve electrical connection between the fifteenth terminal 3011 and the regenerated wafer;

[0100] The fifth and fourth conductors can be complete metal wires, vias, or a combination of metal wires and vias. Methods for preparing the fifth and fourth conductors include, but are not limited to, soldering copper wires, printing carbon ink or silver paste, and mounting conductive materials.

[0101] Step C6: Apply black glue on the regenerated wafer and place it in an oven for curing.

[0102] When the modified chip is used in a five-pin printer, the fifteenth terminal 3011, the second terminal 302, the fifth terminal 305, the sixth terminal 306, and the ninth terminal 309 can each contact the five pins, allowing each pin to exchange information with the regenerated wafer via its own independent pathway. The third terminal 303, the seventh terminal 307, and the eighth terminal 308 are idle. Of course, when the modified chip is used in printers of other specifications, the third terminal 303, the seventh terminal 307, and the eighth terminal 308 can also contact the pins, enabling information exchange between the pins and the regenerated wafer, depending on the situation. Therefore, the modified chip has high versatility.

[0103] Prior Art 3:

[0104] See also Figure 9 , the present prior art provides a four-terminal chip, whose substrate 1 only has a second terminal 302, a fifth terminal 305, a sixth terminal 306 and a seventh terminal 307, wherein the second terminal 302, the sixth terminal 306 and the seventh terminal 307 are all second functional terminals 42 and are electrically connected to the wafer, and the fifth terminal 305 is a fourth functional terminal 44 and is not electrically connected to the wafer.

[0105] Example 4:

[0106] See also Figure 9 and Figure 10 In this embodiment, the four-terminal chip in the prior art 3 is modified to obtain a modified chip. The modification method includes the following steps:

[0107] Step D1: Place the old chip on a jig, and remove the black glue on the wafer and the surface of the wafer on the substrate 1 by heating, softening, manual scraping, or scraping with a machine;

[0108] Step D2: Soldering a fifteenth terminal 3011 and a sixteenth terminal 3091 on the front surface of the substrate 1. The welding position of the fifteenth terminal 3011 corresponds to the position of the first terminal in the prior art 1, and the welding position of the sixteenth terminal 3091 corresponds to the position of the ninth terminal in the prior art 1. The fifteenth terminal 3011 and the sixteenth terminal 3091 are both sixth functional terminals 46. The sixth functional terminal 46 is a terminal newly soldered to the substrate 1 during the chip modification process.

[0109] Step D3: Clean the substrate 1 to expose all wafer pad contacts, so as to convert the substrate 1 into an original chip substrate 10;

[0110] Step D4: using a COB process to place the regenerated wafer on the original chip substrate 10 so that the wafer pad contacts are electrically connected to the solder points of the regenerated wafer;

[0111] Step D5: Laying out two fifth wires and one fourth wire, with both ends of the fourth wire respectively arranged between the fifth terminal 305 and the regenerated wafer, so that the fifth terminal 305 is converted from the fourth functional terminal 44 to the fifth functional terminal 45. The two fifth wires are respectively arranged between the fifteenth terminal 3011 and the regenerated wafer and between the sixteenth terminal 3091 and the regenerated wafer, so as to achieve electrical connection between the fifteenth terminal 3011 and the regenerated wafer and between the sixteenth terminal 3091 and the regenerated wafer. The main difference between the fifth functional terminal 45 and the sixth functional terminal 46 is that the fifth functional terminal 45 is a terminal already located on the substrate 1 before the chip is modified, while the sixth functional terminal 46 is a terminal newly soldered to the original chip substrate 10 during the modification process;

[0112] Methods for preparing the fifth and fourth conductors include, but are not limited to, soldering copper wires, printing carbon oil or silver paste, and mounting conductive materials;

[0113] Step D6: Apply black glue on the regenerated wafer and place it in an oven for curing.

[0114] Thus, the fifteenth terminal 3011, the second terminal 302, the fifth terminal 305, the sixth terminal 306 and the sixteenth terminal 3091 can respectively contact the five stylus pins of the five-stylus printer, thereby realizing signal exchange between the five stylus pins and the regenerated wafer through five relatively independent paths.

[0115] Prior Art 4:

[0116] The difference between the present prior art and prior art 1 is that the second terminal and the first terminal are electrically connected to the wafer via a wire.

[0117] Example 5:

[0118] This embodiment uses a chip processing method similar to that in Example 1 to process and modify the chip in the prior art 4. The only difference is that the wire between the second terminal and the first terminal is additionally cut off, so that the second terminal and the first terminal on the modified chip cannot be directly electrically connected. The chip structure obtained after the modification is similar to Figure 3 The chip structure remains consistent.

[0119] Example 6:

[0120] This embodiment provides a chip processing method, comprising the following steps:

[0121] Step S1: determining the number and spatial arrangement of the fourth functional terminals and the second functional terminals on the chip, wherein the second functional terminals are directly electrically connected to the wafer, and the fourth functional terminals are not electrically connected to the wafer;

[0122] Step S2: determining the number and distribution of contact pins in the target compatible printer to compare with the number and spatial arrangement of the fourth functional terminals and the second functional terminals, and replacing the wafer in the chip before transformation with the regenerated wafer;

[0123] Step S3: If some of the contact pins lack corresponding terminals at corresponding positions on the substrate, the substrate of the chip before modification is used as the original chip substrate, and a sixth functional terminal and a fifth wire are additionally soldered on the original chip substrate. The sixth functional terminal is electrically connected to the regenerated wafer through the fifth wire;

[0124] Step S4: preparing a first conductive wire between at least part of the fourth functional terminal and the second functional terminal, using methods including but not limited to welding copper wire, printing carbon oil or silver paste, and applying conductive material, so that at least part of the fourth functional terminal is converted into a first functional terminal and electrically connected to the regenerated wafer through the second functional terminal. As a result, part of the fourth functional terminal may be converted into a third functional terminal, and the third functional terminal is electrically connected to the regenerated wafer through the first functional terminal and the second functional terminal by using a third conductive wire inherent between the third functional terminal and the first functional terminal;

[0125] Step S5: Disposing a fourth wire between a portion of the fourth functional terminals and the regenerated wafer to convert the portion of the fourth functional terminals into a fifth functional terminal.

[0126] Among them, steps S3, S4 and S5 can be performed in any one, any two or all steps according to the comparison result in step S2.

[0127] Step S6: Optionally, the electrical connection between some of the fourth functional terminals is cut off, thereby ensuring that each contact pin is directly connected in series to the regenerated wafer.

[0128] Example 7:

[0129] See also Figure 12 This embodiment provides a consumables box, comprising a chip 81 modified from the above embodiment and a box body 82. The chip 81 is located on the outer wall of the box body 82 to contact the printer's contact pins. The consumables box can specifically be an ink cartridge, a toner cartridge, or a toner cartridge.

[0130] Of course, when the modified chip 81 is used in printers of other specifications, part of the first functional terminal, part of the second functional terminal, part of the third functional terminal or part of the fourth functional terminal may be in contact with the contact pin or not, depending on the situation, mainly depending on the number and position of the printer contact pins, etc., thereby realizing different combinations of information interaction between the contact pins and the regenerated wafer. Therefore, the modified chip 81 has high versatility.

[0131] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above-described embodiments merely represent several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present utility model patent shall be determined by the appended claims.

Claims

1. A chip, characterized in that: It includes an original chip substrate and a regenerated wafer mounted on the original chip substrate, wherein the original chip substrate is provided with a first functional terminal, a second functional terminal and a fifth functional terminal, and the original chip substrate is provided with a first wire, a second wire and a fourth wire, the two ends of the second wire are respectively electrically connected to the second functional terminal and the regenerated wafer, so that the second functional terminal is electrically connected to the regenerated wafer through the second wire, the two ends of the first wire are respectively electrically connected to the first functional terminal and the second functional terminal, so that the first functional terminal is electrically connected to the regenerated wafer through the second functional terminal, and the two ends of the fourth wire are respectively electrically connected to the fifth functional terminal and the regenerated wafer, so that the fifth functional terminal is electrically connected to the regenerated wafer through the fourth wire.

2. The chip according to claim 1, characterized in that A third functional terminal and a third wire are also provided on the original chip substrate, and the two ends of the third wire are electrically connected to the third functional terminal and the first functional terminal respectively, so that the third functional terminal is electrically connected to the regenerated wafer through the first functional terminal and the second functional terminal.

3. The chip according to claim 2, characterized in that The surface of the original chip substrate is covered with a first insulating layer, the first wire and the third wire are separated by the first insulating layer, and / or a second insulating layer is provided on the side of the first insulating layer facing away from the original chip substrate, and the first wire is located between the first insulating layer and the second insulating layer.

4. The chip according to claim 3, characterized in that The surface of the original chip substrate is covered with a third insulating layer, and the fourth wire and the second wire are separated by the third insulating layer.

5. The chip according to claim 3, characterized in that The first conductive line is located on a side of the first insulating layer facing away from the original chip substrate, and the second conductive line is located between the original chip substrate and the first insulating layer at a portion on the front side of the original chip substrate.

6. The chip according to claim 1, characterized in that The second functional terminal is electrically connected to only one first functional terminal through the first conductive wire.

7. The chip according to claim 1, characterized in that There are at least two fifth functional terminals, each of which is electrically connected to a conduction port. Two ends of the fourth wire are electrically connected to the conduction port and the regenerated wafer respectively, and different conduction ports are disconnected.

8. A chip, characterized in that: The invention comprises an original chip substrate and a regenerated wafer mounted on the original chip substrate, wherein the original chip substrate is provided with a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, a seventh terminal, an eighth terminal, a ninth terminal, a second wire, a third wire, a first wire and a fourth wire; There are five second wires, corresponding to the second terminal, the third terminal, the sixth terminal, the seventh terminal, and the eighth terminal, respectively. The second terminal, the third terminal, the sixth terminal, the seventh terminal, and the eighth terminal are electrically connected to the regenerated wafer through the corresponding second wires. The first terminal is electrically connected to the fourth terminal through the third wire, and the fourth terminal is electrically connected to the third terminal or the seventh terminal or the eighth terminal through the first wire; There are two fourth wires, corresponding to the fifth terminal and the ninth terminal respectively. The fifth terminal and the ninth terminal are electrically connected to the regenerated wafer through the corresponding fourth wires.

9. The chip according to claim 8, characterized in that The first terminal is a first short-circuit detection terminal, the second terminal is a CE reset terminal, the third terminal is a CLK clock terminal, the fourth terminal is a second short-circuit detection terminal, the fifth terminal is a first high-voltage terminal, the sixth terminal is a VDD power supply terminal, the seventh terminal is a GND ground terminal, the eighth terminal is used as a DATE data terminal, and the ninth terminal is a second high-voltage terminal.

10. A consumables box, characterized in that: Comprising a chip as claimed in any one of claims 1 to 9.

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