Semiconductor lead frame

Abstract

The utility model discloses a semiconductor lead frame, which relates to the field of semiconductor packaging and manufacturing, and comprises a slide glass, the slide glass is provided with a slide glass area and a silver plating area I, the slide glass is also provided with an isolation strip positioned on the outer side of the silver plating area I, and the isolation strip is provided with a bulge structure. According to the utility model, when the semiconductor lead frame is stacked, packaged and transported, the projection structure can support the semiconductor lead frame on the upper layer, so that the silver plating area I is not in direct contact with the surface of the semiconductor lead frame on the upper layer, thereby preventing a silver layer of the silver plating area I from being scratched; and the quality of the semiconductor lead frame is ensured.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor packaging manufacturing, in particular to a semiconductor lead frame. Background Art

[0002] As the chip carrier of integrated circuits, the lead frame is a key structural component that uses bonding materials (gold wire, aluminum wire, copper wire) to achieve electrical connection between the internal circuit lead ends of the chip and the external leads to form an electrical circuit. It acts as a bridge connecting to external wires. Lead frames are required in most semiconductor integrated blocks and are an important basic material in the electronic information industry.

[0003] like Figure 1 As shown, to improve waterproofness, existing TO-220H lead frames have wafer-carrying waterproof grooves stamped on both sides of the lead frame's wafer-carrying area and on the side of the wafer-carrying area close to the lead pins. Furthermore, to facilitate gold wire soldering, a silver-plated area is provided on the lead frame's wafer-carrying area and two inner leads, and the silver-plated area is silver-plated. However, the wafer-carrying waterproof grooves on the TO-220H lead frame do not protect the silver layer in the silver-plated area. As a result, the silver layer in the wafer-carrying area is easily scratched during subsequent stacking, packaging, and transportation of the TO-220H lead frame, resulting in unstable soldering of the gold wire and its easy detachment. Utility Model Content

[0004] The utility model aims to provide a semiconductor lead frame to solve the problem that the silver layer on the carrier is easily scratched during the subsequent stacking, packaging and transportation of the lead frame.

[0005] To achieve the purpose of the utility model, the technical solution adopted is: a semiconductor lead frame, including a carrier, the carrier having a carrier area and a silver-plated area I, the carrier also having an isolation belt located outside the silver-plated area I, and the isolation belt has a raised structure.

[0006] Furthermore, the isolation zone is a V-shaped groove, and the protruding structure is connected between the V-shaped groove and the surface of the carrier.

[0007] Furthermore, the isolation belt is H-shaped, and the wafer carrier area and the silver-plated area I are located in two openings of the isolation belt.

[0008] Furthermore, the nodes of the isolation zone are disconnected.

[0009] Furthermore, the protrusion height of the protrusion structure is 0.01 mm to 0.02 mm.

[0010] Furthermore, the semiconductor lead frame also includes a heat sink, inner leads, outer leads and connecting ribs, the inner leads and outer leads are all connected to the connecting ribs, and there are three inner leads and three outer leads, one of the inner leads is connected to the carrier, and the other two inner leads have silver-plated area II; the heat sink is located on the side of the carrier away from the connecting ribs.

[0011] The beneficial effects of the utility model are:

[0012] 1. By adopting an isolation tape with a raised structure, the raised structure can support the upper semiconductor lead frame when the semiconductor lead frame is stacked and packaged for transportation, so that the silver-plated area I will not directly contact the surface of the upper semiconductor lead frame, thereby avoiding scratches on the silver layer of the silver-plated area I, so that the quality of the semiconductor lead frame is guaranteed.

[0013] 2. By setting the isolation belt as a V-shaped groove and connecting the protruding structure between the two sides of the V-shaped groove and the surface of the carrier, it can not only prevent the scratches of the silver-plated area I, but also increase the contact area between the plastic encapsulation material and the carrier when the chip is encapsulated with plastic encapsulation material, making the plastic encapsulation material more firmly attached to the carrier and avoiding delamination of the plastic encapsulation material and the carrier.

[0014] 3. By setting the isolation belt to H-shape and disconnecting the nodes of the isolation belt, when the chip is soldered on the carrier, even if excess solder flows into the nodes of the isolation belt, the excess solder flowing into the nodes of the isolation belt will not directly enter the silver-plated area I, but will continue to flow directly through the isolation belt outside the silver-plated area I, thereby effectively avoiding the solder from affecting the silver-plated area I and preventing it from affecting the subsequent gold wire welding. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the description, are used to explain the principles of the present invention. These drawings are included to provide a further understanding of the present invention, and are included in and constitute a part of this specification.

[0016] Figure 1 It is a structural diagram of the existing TO-220H lead frame;

[0017] Figure 2 This is a structural diagram of a semiconductor lead frame provided by the present invention;

[0018] Figure 3 is a schematic cross-sectional view of the isolation zone;

[0019] Figure 4 This is a cross-sectional view of the junction between the isolation tape and the plastic sealing material after plastic sealing;

[0020] Figure 5This is the flow diagram of the solder entering the isolation belt when the chip is soldered in the download area with the isolation belt not disconnected;

[0021] Figure 6 This is the flow diagram of the solder entering the isolation belt when the chip is soldered in the download area with the isolation belt disconnected;

[0022] Figure 7 This is a state diagram of two adjacent layers of semiconductor lead frames when the semiconductor lead frames are stacked and packaged.

[0023] Markings and corresponding parts names in the accompanying drawings:

[0024] 1. Chip carrier, 2. Heat sink, 3. Inner lead, 4. Outer lead, 5. Connecting rib, 6. Chip carrier area, 7. Silver-plated area I, 8. Silver-plated area II, 9. Isolation tape;

[0025] 91. V-shaped groove, 92. Raised structure. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to explain the relevant content and are not intended to limit the present invention. It should also be noted that, for ease of description, only the parts relevant to the present invention are shown in the accompanying drawings.

[0027] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0028] like Figure 1 As shown, the present invention provides a semiconductor lead frame, comprising a heat sink 2, a carrier 1, inner leads 3, outer leads 4, and connecting ribs 5. The inner leads 3 and outer leads 4 are connected by connecting ribs 5. There are three inner leads 3 and three outer leads 4, respectively. The three outer leads 4 are spaced apart along the width of the semiconductor lead frame, and the three outer leads 4 correspond one-to-one with the three inner leads 3. The carrier 1 is connected to the inner lead located in the middle of the semiconductor lead frame, and the heat sink 2 is located on the side of the carrier 1 away from the inner leads 3.

[0029] The carrier 1 has a carrier area 6 and a silver-plated area I7. The carrier area 6 is used for welding chips, and the chip is plastic-sealed with a plastic sealing material after welding. The silver-plated area I7 is used for welding gold wires, and the silver-plated area I7 is silver-plated before welding the gold wires. At the same time, the silver-plated area I7 is silver-plated before welding the chips.

[0030] The carrier 1 also has an isolation tape 9, which is used to isolate the carrier area 6 and the silver-plated area I7, so that the carrier area 6 and the silver-plated area I7 are separated; at the same time, in order to prevent the upper semiconductor lead frame from scratching the silver-plated area I7 on the lower semiconductor lead frame when the semiconductor lead frame is stacked and packaged for transportation, the isolation tape 9 has a protruding structure 92, so that when multiple semiconductor lead frames are stacked, the protruding structure 92 can be supported between the lower surface of the upper semiconductor lead frame and the upper surface of the lower semiconductor lead frame, so that there is a certain distance between the lower surface of the upper semiconductor lead frame and the upper surface of the lower semiconductor lead frame, so that the silver-plated area I7 on the lower semiconductor lead frame will not contact the lower surface of the upper semiconductor lead frame, thereby effectively preventing the silver-plated area I7 from being scratched. Figure 7 shown.

[0031] In this utility model, if Figure 3 As shown, the isolation belt 9 is a V-shaped groove 91, and the convex structure 92 is connected between the V-shaped groove 91 and the surface of the carrier 1, so that the opening edge of the V-shaped groove 91 is convex, so that when the carrier area 6 is soldering the chip, the excess solder of the soldered chip can be effectively intercepted by the isolation belt 9, preventing the excess solder from entering the silver-plated area Ⅰ7, thereby effectively preventing the solder from contaminating the silver-plated area Ⅰ7, so that the subsequent soldering of the gold wire will not be affected; at the same time, the utility model can also increase the contact area between the plastic sealing material and the carrier when the chip is packaged with plastic sealing material in the carrier area, so that the plastic sealing material is more firmly attached to the carrier, and the plastic sealing material and the carrier are prevented from being delaminated. Figure 4 shown.

[0032] In the present invention, by using V-grooves 91 as isolation strips 9, excess solder from soldering the chips can flow along the V-grooves 91. Furthermore, during stamping, the V-grooves 91 produce a slight protrusion at the recessed portion of the carrier 1. This slight protrusion forms a raised structure 92, eliminating the need for secondary processing. This allows the semiconductor lead frame provided by the present invention to prevent scratches on the silver-plated area 17 while also preventing solder from contaminating the silver-plated area 17. In the present invention, by using stamped V-grooves 91 to form the raised structure 92, the raised structure 92 becomes smoother, effectively preventing the raised structure 92 from scratching the lower surface of the upper semiconductor lead frame during stacked packaging and transportation, thereby effectively protecting the quality of the semiconductor lead frame.

[0033] like Figure 1 、 Figure 5As shown, the isolation belt 9 of the present invention is H-shaped, so that the isolation belt 9 forms two U-shaped areas, and the carrier area 6 and the silver-plated area Ⅰ7 are respectively located in the two U-shaped areas, and the silver-plated area Ⅰ7 and the carrier area 6 are isolated by the middle part of the isolation belt 9. Since the left and right sides of the silver-plated area Ⅰ7 and the left and right sides of the carrier area 6 are provided with isolation belts 9, it is possible not only to prevent the solder of the carrier area 6 from overflowing the carrier area 6 as much as possible, but also to prevent the solder overflowing from the carrier area 6 from entering the silver-plated area Ⅰ7 as much as possible, so that the protection effect of the silver-plated area Ⅰ7 is better. In addition, even if the solder of the carrier area 6 accidentally enters the isolation belt 9, the solder will only flow along the isolation belt 9 and will not enter the silver-plated area Ⅰ7. Figure 5 As shown, the protection effect of the silver-plated area Ⅰ7 is better.

[0034] The nodes of the isolation belt 9 in the present invention are disconnected. Specifically, the isolation belt 9 is divided into five parts in total, two of which are located on both sides of the carrier area 6, the other two parts of the isolation belt 9 are located on both sides of the silver-plated area Ⅰ7, and the other part of the isolation belt 9 is located between the silver-plated area Ⅰ7 and the carrier area 6. A certain distance is retained between the two isolation belts 9 on the same side of the silver-plated area Ⅰ7 and the carrier area 6. A certain distance is also retained between the isolation belts 9 on both sides of the silver-plated area Ⅰ7, the isolation belts 9 on both sides of the carrier area 6, and the isolation belt 9 located between the silver-plated area Ⅰ7 and the carrier area 6, so that the five parts of the isolation belt 9 are not seamlessly connected. This design ensures that when the chip is soldered, even if the solder accidentally enters the isolation belts 9 on the left and right of the carrier area 6, the solder will only flow downward along the two sides of the carrier area 6 to the disconnection point, and will not only enter the isolation belts 9 on both sides of the silver-plated area Ⅰ7, thereby shortening the flow distance. Figure 6 shown.

[0035] In the present invention, the raised height of the raised structure 92 is 0.01 mm to 0.02 mm, ensuring that a certain distance is maintained between the upper and lower layers of semiconductor lead frames without affecting the stacking of the semiconductor lead frames during packaging and transportation. Furthermore, the isolation band 9 can be formed by stamping, reducing processing difficulty. Of course, in the present invention, if only the silver-plated area I7 is not scratched, the raised height can be less than 0.01 mm or greater than 0.02 mm. In other words, the specific selection of the raised height can be determined based on actual conditions.

[0036] In the present invention, the inner leads 3 located on both sides of the semiconductor lead frame further have silver-plated areas II8.

[0037] In the present invention, when only considering that the silver-plated area Ⅰ7 is not affected during the stacking packaging and transportation of the semiconductor lead frame, the isolation belt 9 can also be changed in the following aspects: 1. The isolation belt 9 can also be directly a convex ridge protruding upward; 2. The V-shaped groove 91 can also be replaced by an arc groove, a U-shaped groove, a trapezoidal groove, etc.; 3. The isolation belt 9 can also only wrap around the silver-plated area Ⅰ7, or the isolation belt 9 is only set between the carrier area 6 and the silver-plated area Ⅰ7 and between the silver-plated area Ⅰ7 and the inner lead 3, or the isolation belt 9 is only located on one side of the silver-plated area Ⅰ7 or on two adjacent sides or on two opposite sides.

[0038] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in an appropriate manner in any one or more embodiments / methods or examples. In addition, those skilled in the art may combine and combine different embodiments / methods or examples described in this specification and the features of different embodiments / methods or examples, unless they are contradictory.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0040] Those skilled in the art will appreciate that the above embodiments are merely for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention. Other variations or modifications may be made based on the above disclosure, and such variations or modifications are still within the scope of the present invention.

Claims

1. A semiconductor lead frame, characterized in that: The invention comprises a carrier (1), wherein the carrier (1) has a carrier area (6) and a silver-plated area I (7), and the carrier (1) also has an isolation belt (9) located outside the silver-plated area I (7), and the isolation belt (9) has a protruding structure (92).

2. The semiconductor lead frame according to claim 1, wherein The isolation belt (9) is a V-shaped groove (91), and the protruding structure (92) is connected between the V-shaped groove (91) and the surface of the carrier (1).

3. The semiconductor lead frame according to claim 1, wherein The isolation belt (9) is H-shaped, and the carrier area (6) and the silver-plated area I (7) are located in two openings of the isolation belt (9).

4. The semiconductor lead frame according to claim 3, wherein The nodes of the isolation belt (9) are disconnected.

5. The semiconductor lead frame according to claim 1, wherein The protrusion height of the protrusion structure (92) is 0.01 mm to 0.02 mm.

6. The semiconductor lead frame according to any one of claims 1 to 5, wherein: The semiconductor lead frame further comprises a heat sink (2), inner leads (3), outer leads (4) and connecting ribs (5), wherein the inner leads (3) and the outer leads (4) are both connected to the connecting ribs (5), and there are three inner leads (3) and three outer leads (4), one of the inner leads (3) is connected to the carrier (1), and the other two inner leads (3) are each provided with a silver-plated area II (8); the heat sink (2) is located on a side of the carrier (1) away from the connecting ribs (5).

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