Package structure

Abstract

A package structure is provided. The package structure includes a first wafer structure having a conductive bonding structure and a dielectric bonding structure surrounding the conductive bonding structure, where a top surface of the conductive bonding structure is coplanar with a top surface of the dielectric bonding structure; a second wafer structure bonded to the dielectric bonding structure and the conductive bonding structure by dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitor element laterally separated from the second wafer structure; and an insulating layer laterally surrounding the second wafer structure and at least a portion of the capacitive element.

Description

Technical Field

[0001] The utility model relates to a packaging structure, in particular to a packaging structure with a capacitor element. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Continuous advancements in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and / or higher levels of integration. Functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be produced using a process) has decreased. This miniaturization process generally benefits by increasing production efficiency and reducing associated costs.

[0003] Chip packaging not only protects semiconductor devices from environmental contamination, but also provides a connection interface for the semiconductor devices packaged therein. Smaller packaging structures with smaller areas or lower heights have been developed to package semiconductor devices.

[0004] New packaging technologies have been developed to further improve the density and functionality of semiconductor dies. These relatively new semiconductor die packaging technologies face manufacturing challenges. Utility Model Content

[0005] The purpose of the present invention is to provide a packaging structure to solve at least one of the above problems.

[0006] An embodiment of the present invention provides a method for forming a packaging structure, comprising: receiving a first chip structure, wherein the first chip structure has a conductive bonding structure and a dielectric bonding structure surrounding the conductive bonding structure, and the top surface of the conductive bonding structure is coplanar with the top surface of the dielectric bonding structure; bonding a second chip structure to the dielectric bonding structure and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding; forming an insulating layer above the first chip structure, wherein the insulating layer laterally surrounds the second chip structure; and forming a capacitor element, which is laterally separated from the second chip structure, wherein the insulating layer at least partially surrounds the capacitor element.

[0007] An embodiment of the present invention provides a packaging structure, comprising: a first chip structure having a conductive bonding structure and a dielectric bonding structure surrounding the conductive bonding structure, wherein a top surface of the conductive bonding structure is coplanar with a top surface of the dielectric bonding structure; a second chip structure bonded to the dielectric bonding structure and the conductive bonding structure through dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitor element laterally separated from the second chip structure; and an insulating layer laterally surrounding the second chip structure and at least a portion of the capacitor element.

[0008] According to some embodiments, the capacitor element includes: a first conductive layer extending along a plurality of inner sidewalls of the insulating layer; a capacitor dielectric layer located above the first conductive layer; and a second conductive layer located above the capacitor dielectric layer.

[0009] According to some embodiments, the capacitor dielectric layer covers a top surface of the first conductive layer and a top surface of the insulating layer.

[0010] According to some embodiments, an outermost edge of the insulating layer is coplanar with an outermost edge of the first wafer structure.

[0011] According to some embodiments, no tin-containing solder element is formed between the first wafer structure and the second wafer structure.

[0012] An embodiment of the present invention provides a packaging structure, comprising: a first chip structure; a second chip structure having a conductive bonding structure and a dielectric bonding structure surrounding the conductive bonding structure, wherein a top surface of the conductive bonding structure is coplanar with a top surface of the dielectric bonding structure, and the second chip structure is bonded to the first chip structure through dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitor element laterally separated from the second chip structure, wherein the first chip structure extends across opposite edges of the second chip structure and opposite edges of the capacitor element; and an insulating layer laterally surrounding the second chip structure.

[0013] According to some embodiments, a top surface of the insulating layer is coplanar with a top surface of the second wafer structure.

[0014] According to some embodiments, the capacitor element has a capacitor dielectric layer covering the top surface of the insulating layer, and a bottommost surface of the capacitor dielectric layer is located between the top surface and a bottom surface of the insulating layer.

[0015] According to some embodiments, the package structure further includes: a second capacitor element laterally spaced apart from the second wafer structure, wherein the first wafer structure extends across opposite edges of the second capacitor element.

[0016] According to some embodiments, the capacitor element comprises a first conductive layer and a first capacitor dielectric layer located above the first conductive layer. The second capacitor element comprises a second conductive layer and a second capacitor dielectric layer located above the second conductive layer, and a first contact area between the first conductive layer and the first capacitor dielectric layer is larger than a second contact area between the second conductive layer and the second capacitor dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components may be arbitrarily increased or decreased to clearly illustrate the features of the embodiments of the present invention.

[0018] Figures 1A-1G are cross-sectional views of various stages of a process for forming a portion of a package structure according to some embodiments.

[0019] Figure 2 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0020] Figure 3 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0021] Figure 4 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0022] Figure 5 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0023] Figures 6A-6J are cross-sectional views, each showing a portion of a capacitor element of a package structure according to some embodiments.

[0024] Figure 7 is a plan view of a portion of a package structure according to some embodiments.

[0025] Figure 8 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0026] Figure 9 is a cross-sectional view of a portion of a package structure according to some embodiments.

[0027] The accompanying drawings are described as follows:

[0028] 10, 20, 20A, 20B, 20C: Chip structure

[0029] 100:Semiconductor substrate

[0030] 102: Device elements

[0031] 104a, 104b, 104c: dielectric structure

[0032] 106a, 106b, 106c: conductive parts

[0033] 108: Dielectric bonding structure

[0034] 110: Conductive bonding structure / conductive component

[0035] 112: Insulation layer

[0036] 114: Open

[0037] 116A, 116B: conductive layer

[0038] 118: capacitor dielectric layer

[0039] 120A, 120B: conductive layer

[0040] 122: dielectric layer

[0041] 124A, 124B, 124C: conductive parts

[0042] 126: passivation layer

[0043] 128: Protective layer

[0044] 130A, 130B, 130C: conductive parts

[0045] 132:UBM structure

[0046] 200:Semiconductor substrate

[0047] 202: Device components

[0048] 204a, 204b, 204c: dielectric structure

[0049] 206a, 206b, 206c: conductive parts

[0050] 208: Dielectric bonding structure

[0051] 210: Conductive bonding structure

[0052] 240:Through-wafer vias

[0053] 318A, 318B, 318C: capacitor dielectric layer

[0054] 702A, 702B, 702C, 702D, 702E, 702F, 702G, 702H, 702I: Capacitor elements

[0055] 818: capacitor dielectric layer

[0056] C, C1, C2, C3, C3', C3": capacitor elements. DETAILED DESCRIPTION

[0057] The present invention provides a number of embodiments or examples below for implementing different elements of the subject matter provided. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, and it may also include an embodiment in which an additional element is formed between the first and second elements so that they are not in direct contact. In addition, the embodiments of the present invention may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and is not intended to indicate the relationship between the different embodiments and / or configurations discussed.

[0058] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and similar terms, may be used to facilitate describing the relationship between one component or feature and another component or feature in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 90 degrees or in other orientations, the spatially relative adjectives used therein will also be interpreted based on the rotated orientation.

[0059] The following describes some embodiments of the present invention. Additional steps may be provided before, during, and / or after the various stages described in these embodiments. Some of the stages described may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described may be replaced or deleted in different embodiments. Although some embodiments are discussed as performing steps in a specific order, these steps may also be performed in another logical order.

[0060] It should be understood that the terms and expressions in the present invention are for the purpose of description rather than limitation, so that the terms and expressions in this specification should be interpreted by those having ordinary knowledge in the relevant fields based on the teachings of the present invention.

[0061] In some embodiments, the terms "about" and "substantially" can mean that the numerical value of a given amount varies within 5% of the numerical value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the numerical value). These numerical values ​​are merely examples and are not limiting. The terms "about" and "substantially" can refer to percentages of numerical values ​​that would be interpreted by one skilled in the relevant art based on the teachings herein.

[0062] Embodiments of the present invention may be relevant to three-dimensional (3D) packaging, 3D-IC devices, and 2.5D packaging. Embodiments of the present invention form a package structure comprising a substrate supporting one or more dies or packages, and a protective element (e.g., a protective lid) positioned adjacent to the die or package. This protective element may also serve as a warpage control element and / or heat sink.

[0063] Other components and processes may also be included. For example, test structures may be included to facilitate verification testing of 3D packages, 3D-IC devices, and / or 2.5D packages. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allow testing using probes or probe cards and the like. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with intermediate verification testing methods that include known good die (KGD) to improve yield and reduce costs.

[0064] Figures 1A-1G 1 is a cross-sectional view of various stages of a process for forming a portion of a package structure according to some embodiments. Figure 1A As shown, according to some embodiments, a wafer structure (or chip-containing structure) 10 is received. In some embodiments, wafer structure 10 is a semiconductor wafer containing multiple semiconductor chips. After a subsequent sawing process, multiple semiconductor chips can be separated from each other. In some other embodiments, wafer structure 10 is a single semiconductor chip.

[0065] In some embodiments, wafer structure 10 includes a semiconductor substrate 100. In some embodiments, semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. Semiconductor substrate 100 may include silicon or another elemental semiconductor material, such as germanium. Semiconductor substrate 100 may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, semiconductor substrate 100 includes an epitaxially grown semiconductor layer disposed on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0066] In some other embodiments, the semiconductor substrate 100 comprises a compound semiconductor. For example, the compound semiconductor comprises one or more Group III V compound semiconductors having a composition defined by the chemical formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of these is greater than or equal to zero, and together they equal one. The compound semiconductor may comprise silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable substrates comprising Group II VI compound semiconductors may also be used.

[0067] In some embodiments, semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof. In some other embodiments, semiconductor substrate 100 comprises a multilayer structure. For example, semiconductor substrate 100 comprises a silicon germanium layer formed on a bulk silicon layer.

[0068] Various device elements 102 are formed in or on the semiconductor substrate 100 . Figure 1A One of the device elements 102 is shown. Examples of various device elements 102 include a transistor (e.g., a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel field effect transistor (PFET), and / or an n-channel field effect transistor (NFET), etc.), a diode, or another suitable element. In some embodiments, Figure 1A The device element 102 shown includes a baseband device, a logic device, or another suitable device. Various processes may be used to form the various device elements, including deposition, etching, implantation, photolithography, annealing, and other suitable processes.

[0069] The wafer structure 10 may include a front-side interconnect structure. In some embodiments, the front-side interconnect structure includes a plurality of dielectric structures 104a, 104b, and 104c, and a plurality of conductive components 106a, 106b, and 106c surrounded by the dielectric structures 104a, 104b, and 104c. Each dielectric structure 104a, 104b, and 104c may include one or more dielectric layers. The conductive components 106a, 106b, and 106c may include conductive lines, conductive pads, conductive contacts, and conductive vias. In some embodiments, the conductive component 106c is a conductive pad connected to the top metal of the conductive line. In some embodiments, the conductive component 106b is a conductive via that penetrates multiple dielectric layers.

[0070] The dielectric layers of the dielectric structures 104a, 104b, and 104c may be made of, or include, silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon nitride, carbon-containing silicon oxynitride, other suitable materials, or combinations thereof. The conductive members 106a, 106b, and 106c may be made of, or include, copper, tungsten, cobalt, aluminum, tantalum, gold, other suitable materials, or combinations thereof. The formation of the front-side interconnect structure may involve multiple deposition processes, patterning processes, planarization processes, other suitable processes, or combinations thereof.

[0071] The device elements of the chip structure 10 are interconnected by the front-side interconnect structure to form an integrated circuit device, such as a logic device, a memory device (e.g., static random access memory (SRAM)), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, one or more other types of devices, or a combination thereof.

[0072] like Figure 1A As shown, according to some embodiments, the wafer structure 10 further includes a plurality of conductive bonding structures 110 and a dielectric bonding structure 108. The dielectric bonding structure 108 laterally surrounds the conductive bonding structure 110. The dielectric bonding structure 108 can be made of or include silicon oxide, carbon-containing silicon oxide, silicon oxynitride, another suitable material, or a combination thereof. The dielectric bonding structure 108 can be deposited over the front-side interconnect structure using a chemical vapor deposition (CVD) process.

[0073] Then, according to some embodiments, as Figure 1AAs shown, a conductive bonding structure 110 is formed within the dielectric bonding structure 108. In some embodiments, some of the conductive bonding structures 110 are electrically connected to the conductive features 106b below them. In some embodiments, the conductive bonding structure 110 and the conductive features 106b below them are two connected parts of a single conductive structure formed in the same process.

[0074] In some embodiments, as Figure 1A As shown, the top surface of the dielectric bonding structure 108 is coplanar with the top surface of the conductive bonding structure 110. In some embodiments, the formation of the conductive bonding structure 110 involves one or more planarization processes to ensure that the top surface of the dielectric bonding structure 108 is coplanar with the top surface of the conductive bonding structure 110. For example, a chemical mechanical polishing (CMP) process is used.

[0075] like Figure 1A As shown, according to some embodiments, a wafer structure (or structure including a wafer) 20 is picked up and prepared for bonding to a wafer structure 10. In some embodiments, wafer structure 10 is wider than wafer structure 20. In some embodiments, wafer structure 20 is a single semiconductor wafer. In some embodiments, wafer structure 20 is a known good die (KGD) that has been tested.

[0076] In some embodiments, similar to wafer structure 10, wafer structure 20 includes a semiconductor substrate 200. In some embodiments, semiconductor substrate 200 is a bulk semiconductor substrate. Semiconductor substrate 200 may include silicon or another elemental semiconductor material, such as germanium. Semiconductor substrate 200 may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, semiconductor substrate 200 includes an epitaxially grown semiconductor layer disposed on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0077] In some other embodiments, semiconductor substrate 200 comprises a compound semiconductor. For example, the compound semiconductor comprises one or more Group III V compound semiconductors having a composition defined by the chemical formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of these is greater than or equal to zero, and together they equal one. The compound semiconductor may comprise silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations thereof. Other suitable substrates comprising Group II VI compound semiconductors may also be used.

[0078] In some embodiments, semiconductor substrate 200 is an active layer of an SOI substrate. The SOI substrate can be manufactured using a SIMOX process, a wafer bonding process, another applicable method, or a combination thereof. In some other embodiments, semiconductor substrate 200 comprises a multilayer structure. For example, semiconductor substrate 200 comprises a silicon germanium layer formed on a bulk silicon layer.

[0079] Various device elements 202 are formed in or on the semiconductor substrate 200 . Figure 1A One of the device elements 202 is shown. Examples of various device elements 202 include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel field effect transistors (PFETs) and / or n-channel field effect transistors (NFETs), etc.), diodes, or other suitable elements. In some embodiments, Figure 1A The device element 202 shown includes an RF device, an analog device, or another suitable device. Various processes can be used to form the various device elements, including deposition, etching, implantation, photolithography, annealing, and other suitable processes.

[0080] The wafer structure 20 may include a front-side interconnect structure. In some embodiments, the front-side interconnect structure includes a plurality of dielectric structures 204a, 204b, and 204c, and a plurality of conductive components 206a, 206b, and 206c surrounded by the dielectric structures 204a, 204b, and 204c. Each dielectric structure 204a, 204b, and 204c may include one or more dielectric layers. The conductive components 204a, 204b, and 204c may include conductive lines, conductive pads, conductive contacts, and conductive vias. In some embodiments, the conductive component 206c is a conductive pad connected to the top metal of the conductive line. In some embodiments, the conductive component 206b is a conductive via extending through multiple dielectric layers.

[0081] The dielectric layers of dielectric structures 204a, 204b, and 204c may be made of, or include, silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon nitride, carbon-containing silicon oxynitride, other suitable materials, or combinations thereof. Conductive members 206a, 206b, and 206c may be made of, or include, copper, tungsten, cobalt, aluminum, tantalum, gold, other suitable materials, or combinations thereof. Formation of the front-side interconnect structure may involve multiple deposition processes, patterning processes, planarization processes, other suitable processes, or combinations thereof.

[0082] The device elements of the chip structure 20 are interconnected by the front-side interconnect structure to form an integrated circuit device, such as an analog device, a memory device (SRAM), an RF device, an input / output (I / O) device, a SoC device, a logic device, one or more other types of devices, or a combination thereof.

[0083] In some embodiments, the chip structure 20 includes a plurality of through-chip vias 240 extending into the semiconductor substrate 200. Figure 1A FIG2 shows one of the through-wafer vias 240. Each through-wafer via 240 can be electrically connected to one or more conductive features 206a formed in the front-side interconnect structure. In some embodiments, an insulating layer is formed between the semiconductor substrate 200 and the through-wafer via 240 to prevent short circuits between the through-wafer via 240 and the semiconductor substrate 200. The insulating layer can be made of or include silicon oxide, silicon oxynitride, silicon nitride, another suitable material, or a combination thereof. In some embodiments, the through-wafer via 240 extends through the semiconductor substrate 200. In other embodiments, the through-wafer via 240 extends into the semiconductor substrate 200 without completely passing through the semiconductor substrate 200.

[0084] like Figure 1A As shown, according to some embodiments, the wafer structure 20 further includes a plurality of conductive bonding structures 210 and a dielectric bonding structure 208. The dielectric bonding structure 208 laterally surrounds the conductive bonding structure 210. The dielectric bonding structure 208 can be made of or include silicon oxide, carbon-containing silicon oxide, silicon oxynitride, another suitable material, or a combination thereof. The dielectric bonding structure 208 can be deposited over the front-side interconnect structure using a CVD process.

[0085] Then, according to some embodiments, as Figure 1A As shown, conductive bonding structures 210 are formed within dielectric bonding structures 208. In some embodiments, some conductive bonding structures 210 are electrically connected to underlying conductive features 206b. In some embodiments, conductive bonding structures 210 and underlying conductive features 206b are two connected portions of a single conductive structure formed in the same process.

[0086] In some embodiments, as Figure 1A As shown, the top surface of the dielectric bonding structure 208 is coplanar with the top surface of the conductive bonding structure 210. In some embodiments, the formation of the conductive bonding structure 210 involves one or more planarization processes to ensure that the top surfaces of the dielectric bonding structure 208 and the conductive bonding structure 210 are coplanar. For example, a CMP process is used.

[0087] like Figure 1BAs shown, according to some embodiments, wafer structure 10 and wafer structure 20 are bonded together by direct bonding. Direct bonding can be a hybrid bonding including dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, no tin-containing solder element or solder bump is formed between wafer structure 10 and wafer structure 20. In some embodiments, the bond between wafer structures 10 and 20 is a bumpless thermos-compression hybrid bond.

[0088] In some embodiments, wafer structure 20 is picked up and placed directly on dielectric bonding structure 108 and conductive bonding structure 110. Thus, dielectric bonding structure 108 of wafer structure 10 is in direct contact with dielectric bonding structure 208 of wafer structure 20. Conductive bonding structure 110 of wafer structure 10 is in direct contact with conductive bonding structure 210 of wafer structure 20.

[0089] Prior to placement of the wafer structure 20, a planarization process is performed to provide a highly planarized bonding surface. In some embodiments, there is no gap between the dielectric bonding structure 108 and the dielectric bonding structure 208. In some embodiments, there is no gap between the conductive bonding structure 110 and the conductive bonding structure 210. In some embodiments, a thermal operation is then used to enhance the bonding between the conductive bonding structure 110 and the conductive bonding structure 210. The temperature of the thermal operation may be between about 100 degrees Celsius and about 500 degrees Celsius. In some embodiments, a hot pressing process is used to enhance the bonding between the wafer structure 10 and the wafer structure 20. The hot pressing process may be performed at a temperature of about 400 degrees Celsius for about 2 hours.

[0090] like Figure 1C As shown, according to some embodiments, an insulating layer 112 is formed over the wafer structure 10 to laterally surround the wafer structure 20. In some embodiments, as shown in FIG. Figure 1C As shown, the top surface of the insulating layer 112 is coplanar with the surface of the semiconductor substrate 200 and the surface of the through-wafer via 240. In some embodiments, the top surface of the insulating layer 112 is coplanar with the surface of the semiconductor substrate 200 and the surface of the through-wafer via 240. The insulating layer 112 can be made of or include silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, another suitable material, or a combination thereof. In some embodiments, the insulating layer 112 is not made of a molding compound material or an epoxy-based resin material.

[0091] In some embodiments, a layer of insulating material for forming insulating layer 112 is deposited over wafer structure 10 and wafer structure 20. The insulating material layer can be deposited using a CVD process, an atomic layer deposition (ALD) process, a flowable chemical vapor deposition (FCVD) process, a spin-coating process, another applicable process, or a combination thereof. A planarization process is then used to partially remove the insulating material layer. The planarization process can be performed until through-wafer vias 240 are exposed. In some embodiments, portions of semiconductor substrate 200 and / or through-wafer vias 240 are removed during the planarization process. Thus, the remaining portion of the insulating material layer forms insulating layer 112. The planarization process can include a CMP process, a grinding process, an etching process, a dry polishing process, another applicable process, or a combination thereof.

[0092] like Figure 1D As shown, according to some embodiments, the insulating layer 112 is partially removed to form an opening 114. The opening 114 may expose one or more conductive bonding structures 110 thereunder. The opening 114 may be formed using one or more optical lithography processes and one or more etching processes. For example, a patterned photoresist layer or a patterned dry film may be formed to assist in the formation of the opening 114. The opening 114 may have various cross-sectional shapes. Each opening 114 may have a circular cross-sectional shape, a rectangular cross-sectional shape, a square cross-sectional shape, an elliptical cross-sectional shape, or another suitable cross-sectional shape. Each opening 114 may have a width of between approximately 0.05 μm and approximately 0.5 μm.

[0093] Then, according to some embodiments, as Figure 1D As shown, conductive layers 116A and 116B are formed along the bottom and sidewalls of the left opening 114 and the bottom and sidewalls of the right opening 114, respectively. Conductive layers 116A and 116B can be made of, or include, copper, cobalt, gold, another suitable material, or a combination thereof. In some embodiments, each conductive layer 116A and 116B is electrically connected to the same underlying conductive bonding structure 110. In these cases, conductive layers 116A and 116B are electrically connected to each other. In some embodiments, conductive layers 116A and 116B are electrically connected to one of the conductive bonding structures 208 of the chip structure 20 through the underlying conductive bonding structure 110.

[0094] However, the embodiments of the present invention are not limited thereto. The embodiments of the present invention may be subjected to many changes and / or modifications. In some other embodiments (such as Figure 2As shown in FIG, the conductive layer 116A and the conductive layer 116B are electrically connected to different conductive bonding structures 110 thereunder. Therefore, the conductive layer 116A and the conductive layer 116B are not electrically connected to each other.

[0095] In some embodiments, electrochemical plating (ECP) is used to form conductive layer 116A and conductive layer 116B. A patterned seed layer may be formed above the bottom and sidewalls of opening 114. In some embodiments, a patterned mask layer is formed to cover portions not designated for forming the patterned seed layer.

[0096] A metal layer is then deposited over the patterned mask layer, the bottom of opening 114, and the sidewalls of opening 114. The patterned mask layer is then removed, along with the portion of the metal layer located above the patterned mask layer. The remaining portion of the metal layer thus forms a patterned seed layer. One or more ECP processes are then performed to plate a conductive material onto the patterned seed layer. The patterned seed layer and the plated conductive material together form conductive layer 116A and conductive layer 116B. In some embodiments, conductive layer 116A and conductive layer 116B are formed simultaneously.

[0097] like Figure 1E As shown, according to some embodiments, capacitor dielectric layer 118 is formed over conductive layer 116B. In some embodiments, a portion of capacitor dielectric layer 118 extends over the top surface of conductive layer 116B and over the top surface of insulating layer 112. Capacitor dielectric layer 118 may be made of a high-k material. Capacitor dielectric layer 118 may be made of, or include, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide, hafnium silicon oxide, zirconium titanium oxide, titanium oxide, tantalum oxide, strontium titanium oxide, barium titanium oxide, barium strontium titanium oxide, lead zirconium titanium oxide, silicon nitride, another suitable material, or a combination thereof.

[0098] The CVD process, ALD process, low-temperature plasma enhanced CVD process, physical vapor deposition (PVD) process, spin coating process, another applicable process or a combination thereof may be used. Figure 1D A capacitor dielectric material layer is deposited over the structure shown. The deposition temperature of the capacitor dielectric material layer may be between about 150 degrees Celsius and about 400 degrees Celsius. In some other embodiments, the deposition temperature of the capacitor dielectric material layer may be between about 180 degrees Celsius and about 250 degrees Celsius. Then, one or more optical lithography processes and one or more etching processes (e.g., one or more plasma etching processes) are used to partially remove the capacitor dielectric material layer. Thus, as shown in FIG. Figure 1E As shown, the remaining portion of the capacitor dielectric material layer forms the capacitor dielectric material layer 118 .

[0099] Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, a liquid-phase material is used to form the capacitor dielectric layer 118. For example, a liquid-phase oxide material (e.g., liquid-phase silicon oxide and spin-on glass) and / or a liquid-phase polymer material (e.g., polyimide and polybenzoxazoles (PBO)) may be used to form the capacitor dielectric layer 118. In some embodiments, a thermal curing operation is used to harden the liquid-phase material into the capacitor dielectric layer 118.

[0100] In some embodiments, capacitor dielectric layer 118 is a single layer. In other embodiments, capacitor dielectric layer 118 includes multiple sub-layers. In some embodiments, some of the sub-layers are made of different materials. In other embodiments, the sub-layers are made of the same material. In some embodiments, capacitor dielectric layer 118 includes an aluminum oxide sub-layer and two zirconium oxide sub-layers. The aluminum oxide sub-layer may be sandwiched between the zirconium oxide sub-layers.

[0101] like Figure 1F As shown, according to some embodiments, conductive layer 120A and conductive layer 120B are formed over conductive layer 116A and capacitor dielectric layer 118, respectively. In some embodiments, conductive layer 120A and conductive layer 120B fill the remaining space of opening 114. In some embodiments, the top surface of conductive layer 120A is substantially coplanar with the top surface of insulating layer 112. In some embodiments, the top surface of conductive layer 120B is substantially coplanar with the top surface of capacitor dielectric layer 118.

[0102] The materials of the conductive layer 120A and the conductive layer 120B may be the same or similar to the materials of the conductive layer 116A and the conductive layer 116B. In some embodiments, the conductive material layer is deposited on Figure 1E The structure shown is overfilled with opening 114. In some embodiments, an ECP process is used to deposit a conductive material layer. Figure 1E A seed layer is deposited over the structure shown to assist in the formation of the conductive material layer. A planarization process is then used to partially remove the conductive material layer. As a result, the remaining portions of the conductive material layer form conductive layer 120A and conductive layer 120B. For example, the planarization process may be a CMP process or another suitable process. In some embodiments, conductive layer 120A and conductive layer 120B are formed simultaneously.

[0103] In some embodiments, the conductive layer 116B, the capacitor dielectric layer 118, and the conductive layer 120B together form a capacitor element C. The capacitor element C may be a decoupling capacitor. Figure 1F As shown, the capacitor element C is laterally separated from the chip structure 20. The capacitor element C can help reduce signal noise during operation of the chip structure 20 and / or the chip structure 10. In some embodiments, the insulating layer 112 laterally surrounds the lower portion of the capacitor element C. In some embodiments, as shown in FIG. Figure 1F As shown, the upper portion of capacitor dielectric layer 118 and the upper portion of conductive layer 120B protrude above the top surface of insulating layer 112. In some embodiments, the bottommost surface of capacitor dielectric layer 118 is disposed between the top surface and the bottom surface of insulating layer 112.

[0104] Figures 6A-6J The cross-sectional views of some embodiments each show a portion of a capacitor element of a package structure. The capacitor element C may be formed to have Figures 6A-6J The capacitance of the capacitor element C can be adjusted by fine-tuning the size, profile, and / or shape of the capacitor element. The capacitance can be adjusted within a range of approximately 100 fF to approximately 500 nF, which is suitable for various applications.

[0105] like Figure 1G As shown, according to some embodiments, the dielectric layer 122 is deposited on Figure 1F 104c. The dielectric layer 122 is formed of the same material and by a method similar to that of dielectric structure 104c. Dielectric layer 122 is then patterned to form openings that expose the underlying conductive features. For example, conductive layer 116A, conductive layer 120A, conductive layer 120B of capacitor element C, and through-wafer via 240 are exposed.

[0106] Then, if Figure 1GAs shown, according to some embodiments, conductive features 124A, 124B, and 124C are formed within the openings of dielectric layer 122 to form electrical connections to underlying conductive features. The materials and formation methods of conductive features 124A, 124B, and 124C can be the same as or similar to those of conductive layer 120A and conductive layer 124B.

[0107] like Figure 1G As shown, according to some embodiments, a patterned passivation layer 126 is then formed over dielectric layer 122 and over conductive features 124A, 124B, and 124C. Patterned passivation layer 126 has a plurality of openings that expose conductive features 124A, 124B, and 124C. Patterned passivation layer 126 may be made of or include silicon nitride, silicon oxynitride, another suitable material, or a combination thereof. Formation of patterned passivation layer 126 may involve one or more deposition processes and one or more patterning processes.

[0108] Then, conductive members 130A, 130B, and 130C are formed over conductive member 124A, conductive member 124B, and conductive member 124C, respectively. Conductive members 130A, 130B, and 130C may serve as conductive pads. Conductive members 130A, 130B, and 130C may be made of, or include, copper, aluminum, cobalt, another suitable material, or a combination thereof.

[0109] like Figure 1G As shown, a protective layer 128 is then formed over the passivation layer 126 to laterally surround the lower portions of the conductive components 130A, 130B, and 130C. The protective layer 128 may be made of, or include, a polymer material. The polymer material may be made of, or include, PBO, polyimide, epoxy, another suitable polymer material, or a combination thereof. In some other embodiments, the protective layer 128 is made of, or includes, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, another suitable dielectric material, or a combination thereof. The protective layer 128 may be formed using a spin coating process, a CVD process, another applicable process, or a combination thereof.

[0110] Then, if Figure 1GAs shown, according to some embodiments, an under-bump metallization (UBM) structure 132 is formed over the conductive features 130A, 130B, and 130C. The UBM structure 132 can be used to receive and hold tin-containing solder bumps. The UBM structure 132 can be made of or include nickel, palladium, gold, another suitable material, or a combination thereof. The UBM structure 132 can be formed using an electroplating process, an ECP process, an immersion process, another suitable process, or a combination thereof.

[0111] Then, in some embodiments, a sawing process is used to separate this structure into multiple package structures. One of these package structures is shown in FIG. Figure 1G In some embodiments, the wafer structure 10 is initially a semiconductor wafer. After the sawing process, Figure 1G The wafer structure 10 shown may be a single semiconductor wafer. In some embodiments, the outermost edge of the insulating layer 112 is coplanar with the outermost edge of the wafer structure 10 . Figure 1G The package structure shown can be used as a system on integrated chips (SoIC), which can be further integrated into a chip on wafer on substrate (CoWoS) package structure, an integrated fan-out (InFO) package structure, or similar structures. Because the capacitor element C is formed within the SoIC package structure, the interconnect length between the capacitor element C and the chip structure is very short, which allows for faster operation.

[0112] like Figure 1G As shown, the chip structure 10 extends across opposite edges of the chip structure 20 and opposite edges of the capacitor element C formed by the capacitor dielectric layer 118 and the conductive layers 116B and 120B. Figure 1G As shown, conductive layer 120B serves as an electrode of capacitor element C and is electrically connected to conductive member 130B. In some embodiments, conductive member 130B is used to provide an electrical connection to ground. In some embodiments, conductive layer 116B serves as an electrode of capacitor element C and is electrically connected to conductive member 130A of wafer structure 20 and conductive bonding structure 208 of wafer structure 20. Conductive member 130A can be used to provide signals and / or power to capacitor element C and wafer structure 20.

[0113] Many changes and / or modifications may be made to the embodiments of the present invention. Figure 2 FIG. 1 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 1GIn some embodiments, as shown in the packaging structure Figure 2 As shown, the conductive layer 116B of the capacitor element C is not electrically connected to the conductive layer 116A and the conductive layer 120A.

[0114] Many changes and / or modifications may be made to the embodiments of the present invention. Figure 3 FIG. 1 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 2 In some embodiments, capacitor elements C1 and C2 are formed to fill the opening formed in the insulating layer 112. The materials and formation methods of capacitor elements C1 and C2 can be the same or similar. Figure 1G The materials and forming methods of the capacitor element C are shown in FIG. Figure 3 As shown, capacitor element C1 is electrically connected to wafer structure 20, while capacitor element C2 is electrically connected to wafer structure 10. In some embodiments, wafer structure 10 extends across opposite edges of capacitor element C1 and opposite edges of capacitor element C2.

[0115] In some embodiments, capacitor element C1 includes capacitor dielectric layer 318B, and capacitor element C2 includes capacitor dielectric layer 318A. The materials and formation methods of capacitor dielectric layer 318A and capacitor dielectric layer 318B may be the same or similar. Figure 1G 1 and 2. The materials and formation methods of the capacitor dielectric layer 118 of the capacitor element C shown in FIG. In some embodiments, the capacitor dielectric layer 318A and the capacitor dielectric layer 318B are patterned from the same capacitor dielectric layer and thus have the same composition. In some embodiments, the capacitor dielectric layer 318A and the capacitor dielectric layer 318B are formed simultaneously. In some embodiments, the capacitor element C1 and the capacitor element C2 have the same capacitance. In some embodiments, the size and / or shape of the capacitor element C1 and the capacitor element C2 are different from each other. In these cases, the capacitor element C1 and the capacitor element C2 can have different capacitances.

[0116] Many changes and / or modifications may be made to the embodiments of the present invention. Figure 4 FIG. 1 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 3 In some embodiments, a capacitor element C3 is formed. Figure 4 As shown, the chip structure 20 is located between the capacitor element C1 and the capacitor element C3. The material and formation method of the capacitor element C3 can be the same as or similar to the material and formation method of the capacitor element C1. In some embodiments, the capacitor element C3 is electrically connected to the chip structure 20.

[0117] In some embodiments, capacitor element C3 has a capacitor dielectric layer 318C. The material and formation method of capacitor dielectric layer 318C may be the same or similar to the material and formation method of capacitor dielectric layer 318B of capacitor element C1. In some embodiments, capacitor dielectric layers 318A, 318B, and 318C are patterned from the same capacitor dielectric layer and thus have the same composition. In some embodiments, capacitor dielectric layers 318A, 318B, and 318C are formed simultaneously. In some embodiments, capacitor elements C1, C2, and C3 have the same capacitance. In some embodiments, the size and / or shape of capacitor elements C1, C2, and C3 are different from each other. In these cases, two or more of capacitor elements C1, C2, and C3 may have different capacitances.

[0118] Many changes and / or modifications may be made to the embodiments of the present invention. Figure 5 FIG. 1 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 1G In some embodiments, a capacitor element C3' is formed. Figure 5 As shown, the chip structure 20 is located between the capacitor element C1 and the capacitor element C3 ′. The material and formation method of the capacitor element C3 ′ can be the same as or similar to the material and formation method of the capacitor element C1. In some embodiments, the capacitor element C3 ′ is electrically connected to the chip structure 20.

[0119] In some embodiments, capacitor element C3′ includes a capacitor dielectric layer 318C′. The material and formation method of capacitor dielectric layer 318C′ can be the same as or similar to the material and formation method of capacitor dielectric layer 318B of capacitor element C1. In some embodiments, capacitor dielectric layer 318B and capacitor dielectric layer 318C′ are patterned from different capacitor dielectric layers. In some embodiments, capacitor dielectric layer 318B and capacitor dielectric layer 318C′ have different compositions. In some embodiments, capacitor element C1 and capacitor element C3′ have different capacitances.

[0120] Many changes and / or modifications may be made to the embodiments of the present invention. Figures 6A-6J 1 and 2 are cross-sectional views each showing a portion of a capacitor element of a package structure according to some embodiments. Figure 1A-5 Each capacitor element formed in the embodiment shown in FIG. 1 is formed to have Figures 6A-6J The capacitance of the capacitor element can be adjusted accordingly by fine-tuning the size, profile and / or shape of the capacitor element.

[0121] For example, there is Figure 6B The first capacitive element shown in the cross-section may have a Figure 6DThe second capacitor element shown in the cross-section has a higher capacitance. The contact area between the first capacitor element's dielectric layer 118 and the first capacitor element's conductive layer 116B is greater than the contact area between the second capacitor element's dielectric layer 118 and the second capacitor element's conductive layer 116B.

[0122] In some embodiments, as Figures 6A-6J As shown, each capacitor element has an outer electrode (i.e., conductive layer 116B) and an inner electrode (i.e., conductive layer 120B). In some embodiments, the inner electrode (i.e., conductive layer 120B) serves as a ground electrode. However, embodiments of the present invention are not limited thereto. In some other embodiments, the outer electrode (i.e., conductive layer 116B) serves as a ground electrode.

[0123] Many variations and / or modifications may be made to the embodiments of the present invention. In some embodiments, two or more wafer structures are bonded to the wafer structure 10 via dielectric-to-dielectric bonding and metal-to-metal bonding. Figure 7 FIG. 1 is a plan view of a portion of a package structure according to some embodiments. In some embodiments, a plurality of wafer structures 20A, 20B, 20C are disposed above the wafer structure 10. In some embodiments, the wafer structures 20A, 20B, 20C are bonded to the wafer structure 10 below them by dielectric-to-dielectric bonding and metal-to-metal bonding. In some embodiments, similar to Figure 1B The bond between wafer structure 10 and wafer structure 20 is shown without tin-containing solder elements or solder bumps formed between the lower and upper wafer structures.

[0124] In some embodiments, a plurality of capacitor elements 702A-702I are formed on the wafer structure 10. The materials and the formation methods of the capacitor elements 702A-702I can be the same or similar. Figure 1A-6J Capacitor elements 702A-702I are shown. Capacitor elements 702A-702I can have different shapes, different profiles, and / or different capacitor dielectric layers to provide different capacitances as needed. In some embodiments, capacitor elements 702A-702D are formed adjacent to wafer structure 20. In some embodiments, capacitor elements 702E-702I are formed in the spaces between adjacent wafer structures.

[0125] Many variations and / or modifications may be made to the embodiments of the present invention. In some embodiments, one or more capacitor elements have two or more capacitor dielectric layers. Figure 8 FIG. 1 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 4 In some embodiments, a capacitor element C3 is formed. Figure 8As shown, the chip structure 20 is located between the capacitor element C1 and the capacitor element C3 ″. The material and formation method of the capacitor element C3 ″ can be the same as or similar to the material and formation method of the capacitor element C1 . In some embodiments, the capacitor element C3 ″ is electrically connected to the chip structure 20 .

[0126] In some embodiments, capacitor element C3″ includes a first capacitor dielectric layer 318C and a second capacitor dielectric layer 818. The materials and formation methods of capacitor dielectric layer 318C and capacitor dielectric layer 818 may be the same as or similar to the materials and formation methods of capacitor dielectric layer 318B of capacitor element C1. In some embodiments, capacitor dielectric layer 318C and capacitor dielectric layer 818 are made of different materials. In some other embodiments, capacitor dielectric layer 318C and capacitor dielectric layer 818 are made of the same material.

[0127] In some embodiments, the capacitor elements C1, C2, and C3" have different capacitances. The capacitances of the capacitor elements can be fine-tuned accordingly by forming additional capacitor dielectric layers.

[0128] In some embodiments, the capacitor element has vertical sidewalls. However, the embodiments of the present invention are not limited thereto. The embodiments of the present invention may be subjected to numerous variations and / or modifications. In some other embodiments, one or more capacitor elements have slanted sidewalls. The capacitance of the capacitor element can be adjusted accordingly by fine-tuning the slope of the slanted sidewalls.

[0129] Figure 9 FIG. 1 is a cross-sectional view of a portion of a package structure according to some embodiments. Figure 8 In some other embodiments, the capacitor elements C1 , C2 , and C3 ″ have inclined sidewalls. Each capacitor element C1 , C2 , and C3 ″ gradually narrows in a direction toward the chip structure 10 .

[0130] Many variations and / or modifications may be made to the embodiments of the present invention. In some other embodiments, one or more capacitor elements have curved sidewalls.

[0131] The packaging structure formed by the embodiments of the present invention includes a stack of multiple chip structures. The upper chip structure and the lower chip structure are directly bonded to each other by dielectric-to-dielectric bonding and metal-to-metal bonding. One or more embedded capacitor elements are formed above the lower chip structure and separated from the upper chip structure. The size and material of the embedded capacitor elements can be changed to provide various capacitances. The capacitance and area of ​​the embedded capacitor elements are adjustable, which greatly improves the routing flexibility. The embedded capacitor elements have a shorter interconnect length, which allows for shorter time delays. The performance and reliability of the packaging structure are significantly improved, which is suitable for future advanced portable products, such as new generations of smart phones, tablets, the Internet of Things, cloud computing devices and similar products.

[0132] According to some embodiments, a method for forming a packaging structure is provided. The method includes receiving a first wafer structure, wherein the first wafer structure has a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures. The top surface of the conductive bonding structure is coplanar with the top surface of the dielectric bonding structure. The method also includes bonding a second wafer structure to the dielectric bonding structure and the conductive bonding structure by dielectric-to-dielectric bonding and metal-to-metal bonding. The method also includes forming an insulating layer above the first wafer structure, wherein the insulating layer laterally surrounds the first wafer structure. In addition, the method includes forming a capacitor element, wherein the capacitor element is laterally separated from the second wafer structure, and the insulating layer partially surrounds the capacitor element. In some embodiments, the method also includes partially removing the insulating layer to form an opening to expose one of the conductive bonding structures; forming a first conductive layer, wherein the first conductive layer extends along the bottom and sidewalls of the opening; forming a capacitor dielectric layer above the first conductive layer; and forming a second conductive layer above the capacitor dielectric layer, wherein the first conductive layer, the capacitor dielectric layer, and the second conductive layer together form a capacitor element. In some embodiments, the method also includes forming a second capacitor dielectric layer above the capacitor dielectric layer before the step of forming the second conductive layer. In some embodiments, the capacitor dielectric layer and the second capacitor dielectric layer are made of the same material. In some embodiments, the capacitor dielectric layer and the second capacitor dielectric layer are made of different materials. In some embodiments, a portion of the capacitor dielectric layer is formed above the top surface of the second capacitor dielectric layer and above the top surface of the first conductive layer. In some embodiments, the method further includes partially removing the insulating layer to form a second opening through the insulating layer; forming a third conductive layer, the third conductive layer extending along the bottom and sidewalls of the second opening; and forming a fourth conductive layer above the third conductive layer to fill the second opening. In some embodiments, the third conductive layer is formed simultaneously with the first conductive layer, and the fourth conductive layer is formed simultaneously with the second conductive layer. In some embodiments, the method further includes forming a second capacitor element, the second capacitor element being laterally separated from the second chip structure, wherein the insulating layer at least partially surrounds the second capacitor element. In some embodiments, the method further includes disposing a third chip structure above the first chip structure, wherein the capacitor element is located between the second chip structure and the third chip structure.

[0133] According to some embodiments, a packaging structure is provided. The packaging structure includes a first chip structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures. The top surface of the conductive bonding structure is coplanar with the top surface of the dielectric bonding structure. The packaging structure also includes a second chip structure bonded to the dielectric bonding structure and the conductive bonding structure by dielectric-to-dielectric bonding and metal-to-metal bonding. The packaging structure also includes a capacitor element laterally separated from the second chip structure; and an insulating layer laterally surrounding the second chip structure and a portion of the capacitor element. In some embodiments, the packaging structure includes a first conductive layer extending along the inner side wall of the insulating layer; a capacitor dielectric layer located above the first conductive layer; and a second conductive layer located above the capacitor dielectric layer. In some embodiments, the capacitor dielectric layer covers the top surface of the first conductive layer and the top surface of the insulating layer. In some embodiments, the outermost edge of the insulating layer is coplanar with the outermost edge of the first chip structure. In some embodiments, no tin-containing solder element is formed between the first chip structure and the second chip structure.

[0134] According to some embodiments, a packaging structure is provided. This packaging structure includes a first chip structure and a second chip structure, the second chip structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structure. The top surface of the conductive bonding structure is coplanar with the top surface of the dielectric bonding structure, and the second chip structure is bonded to the first chip structure by dielectric-to-dielectric bonding and metal-to-metal bonding. This packaging structure also includes a capacitor element, which is laterally separated from the second chip structure. The first chip structure extends across the relative edges of the second chip structure and the relative edges of the capacitor element. This packaging structure also includes an insulating layer, which laterally surrounds the second chip structure. In some embodiments, the top surface of the insulating layer is coplanar with the top surface of the second chip structure. In some embodiments, the capacitor element has a capacitor dielectric layer, the capacitor dielectric layer covers the top surface of the insulating layer, and the bottommost surface of the capacitor dielectric layer is located between the top surface of the insulating layer and the bottom surface of the insulating layer. In some embodiments, a second capacitor element is also included, which is laterally separated from the second chip structure, wherein the first chip structure extends across the relative edges of the second capacitor element. In some embodiments, the capacitor element has a first conductive layer and a first capacitor dielectric layer located above the first conductive layer, the second capacitor element has a second conductive layer and a second capacitor dielectric layer located above the second conductive layer, and a first contact area between the first conductive layer and the first capacitor dielectric layer is larger than a second contact area between the second conductive layer and the second capacitor dielectric layer.

[0135] The above summarizes the components of several embodiments so that those skilled in the art can more easily understand the concepts of the present invention. Those skilled in the art will understand that they can use the present invention as a basis to design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A packaging structure, characterized in that: include: a first wafer structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures, wherein top surfaces of the conductive bonding structures are coplanar with a top surface of the dielectric bonding structure; a second wafer structure bonded to the dielectric bonding structure and the conductive bonding structure via dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitor element laterally separated from the second chip structure; and An insulating layer laterally surrounds the second chip structure and at least a portion of the capacitor element.

2. The packaging structure according to claim 1, wherein: The capacitor element includes: a first conductive layer extending along a plurality of inner sidewalls of the insulating layer; a capacitor dielectric layer located above the first conductive layer; and A second conductive layer is located above the capacitor dielectric layer.

3. The packaging structure according to claim 2, wherein: The capacitor dielectric layer covers a top surface of the first conductive layer and a top surface of the insulating layer.

4. The packaging structure according to claim 1, wherein: An outermost edge of the insulating layer is coplanar with an outermost edge of the first chip structure.

5. The packaging structure according to claim 1, wherein: No tin-containing solder element is formed between the first wafer structure and the second wafer structure.

6. A packaging structure, characterized in that: include: a first chip structure; a second wafer structure having a plurality of conductive bonding structures and a dielectric bonding structure surrounding the conductive bonding structures, wherein top surfaces of the conductive bonding structures are coplanar with a top surface of the dielectric bonding structure, and the second wafer structure is bonded to the first wafer structure via dielectric-to-dielectric bonding and metal-to-metal bonding; a capacitive element laterally spaced from the second wafer structure, wherein the first wafer structure extends across opposite edges of the second wafer structure and opposite edges of the capacitive element; and An insulating layer laterally surrounds the second chip structure.

7. The packaging structure according to claim 6, wherein: The top surface of the insulating layer is coplanar with the top surface of the second wafer structure.

8. The packaging structure according to claim 7, wherein: The capacitor element has a capacitor dielectric layer, which covers the top surface of the insulating layer, and a bottommost surface of the capacitor dielectric layer is located between the top surface of the insulating layer and a bottom surface of the insulating layer.

9. The packaging structure according to claim 6, wherein: Also includes: A second capacitor element is laterally spaced apart from the second wafer structure, wherein the first wafer structure extends across opposite edges of the second capacitor element.

10. The packaging structure according to claim 9, wherein: in: The capacitor element has a first conductive layer and a first capacitor dielectric layer located above the first conductive layer. The second capacitor element has a second conductive layer and a second capacitor dielectric layer located above the second conductive layer, and A first contact area between the first conductive layer and the first capacitor dielectric layer is larger than a second contact area between the second conductive layer and the second capacitor dielectric layer.

Images