Super capacitor charging and discharging management module based on temperature monitoring circuit
Through the supercapacitor charge and discharge management module based on the temperature monitoring circuit, the safety hazards and layout problems of supercapacitors in high temperature environments are solved, and the safe and reliable operation and long-term backup power of terminal equipment are achieved.
Patent Information
- Application Number
- CN202422346759.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-09-16
- Estimated Expiration
- 2034-09-26
AI Technical Summary
In high-temperature environments, the charging and discharging of supercapacitors poses safety risks and affects the life of components. In addition, large-capacity capacitors take up a large space and are difficult to arrange reasonably in smart terminal devices.
A supercapacitor charge and discharge management module based on a temperature monitoring circuit is used, including an MCU system, a charging circuit, a temperature monitoring circuit, and a discharge circuit. The temperature monitoring circuit detects the ambient temperature, controls the charging circuit to stop charging when the temperature is high, and restarts it after the temperature recovers. Combined with a voltage equalization circuit, the capacitor voltage consistency is ensured.
In high-temperature environments, it ensures the safety of supercapacitors and extends their service life. At the same time, it ensures that terminal equipment can continue to operate for at least 3 minutes after a mains power outage, and is suitable for the layout requirements of different terminal equipment.
Smart Images
Figure CN223348387U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of capacitor charging and discharging, in particular to a supercapacitor charging and discharging management module based on a temperature monitoring circuit. Background Art
[0002] Currently, many smart terminal devices require backup power, so supercapacitors are often used as energy storage devices for charging and discharging in backup power circuit design. Current smart data collection terminal devices require that after a 220V mains power outage, the terminal device be able to operate normally for at least three minutes, collect power usage data, and report power outage records. Because smart terminal devices have certain backup time requirements, supercapacitors are often large in capacity. However, large-capacity capacitors have relatively large structures and require a larger space, which places high demands on the circuit layout of the terminal device and the placement of the supercapacitor. Currently, there are two main ways to layout supercapacitors. One is to place them directly on the terminal device's main control board, which makes the other circuit layouts more compact and is suitable for terminal devices with larger spatial structures. The other is to design the supercapacitor into a module.
[0003] Currently, supercapacitor charging and discharging modules are mostly used in smart terminal devices as a separate modular design. Considering that the terminal devices are hung outdoors for operation, the normal operation of the terminal devices themselves will increase the internal temperature of the devices. If they are in a high-temperature outdoor environment, the internal temperature of the devices will be even higher. When the temperature is too high, charging and discharging supercapacitors will have certain safety hazards, which will often reduce the service life of components and even cause damage. Utility Model Content
[0004] The present invention aims to solve the above problems and provides a supercapacitor charge and discharge management module based on a temperature monitoring circuit. The technical solution adopted is as follows:
[0005] A supercapacitor charge and discharge management module based on a temperature monitoring circuit includes an MCU system, a charging circuit, a temperature monitoring circuit, and a discharge circuit. The MCU system outputs a control signal to the charging circuit via a charge control pin, and the MCU system outputs a discharge signal to the discharge circuit via a discharge control pin. The charging circuit is used to charge the supercapacitor. The temperature monitoring circuit is used to detect the real-time temperature of the charging environment in which the supercapacitor is located. When the capacitor temperature is higher than a predetermined temperature, the temperature monitoring circuit controls the charging circuit to stop charging the supercapacitor. The discharge circuit controls the supercapacitor to supply power to a load circuit.
[0006] Based on the above scheme, the temperature monitoring circuit includes a voltage detection chip N761, a resistor R218, a resistor R219, a resistor R36, a thermistor RT5 and a capacitor C135. The thermistor RT5 is a negative temperature coefficient thermistor. The Vout terminal of the voltage detection chip N761 is the output terminal EN_C. One end of the resistor R36 is connected to the voltage VDD3V3, and the other end is connected to the Vout terminal of the voltage detection chip N761. One end of the resistor R218 is connected to the voltage VDD3V3, and the other end is connected to the first end of the resistor R219 and the Vdd terminal of the voltage detection chip N761. The second end of the resistor R219 is connected to the first end of the thermistor RT5, and the second end of the thermistor RT5 is connected to the GND terminal of the voltage detection chip N761. The GND terminal of the voltage detection chip N761 is connected to the system reference ground. The capacitor C135 is connected in parallel between the first end of the resistor R219 and the second end of the thermistor RT5.
[0007] Preferably, the charging circuit includes a buck chip UQ2, a diode DU1, a diode DU2, a diode VD27, a transistor Q1, a resistor RU1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor RQ3, a resistor RQ4, a resistor RQ5, a resistor RE11, a resistor RE12, a capacitor CQ1, a capacitor CQ23, a capacitor CQ2, a capacitor CLQ1, a capacitor CQ12, a capacitor CQ13, a capacitor CQ3, a capacitor CQ4 and an inductor LQ1, wherein the positive electrodes of the diode DU1 and the diode DU2 are connected in parallel and then connected to the 4-pin EN port of the buck chip UQ2, and the negative electrode of the diode DU1 is connected to the temperature The output end EN_C of the monitoring circuit and the cathode of the diode DU2 are connected to the charging control pin BAT_CONTRL of the MCU system. The 4th pin of the buck chip UQ2 is controlled by AND gate logic. The anode of the diode DU1 is connected to one end of the resistor RU1. The other end of the resistor RU1 is connected to the power supply VDD3V3. The capacitor CQ1 and the capacitor CQ23 are connected in parallel between the 5-pin IN port and the 2-pin GND port of the buck chip UQ2. The 5-pin IN port of the buck chip UQ2 is connected to the +12V voltage. The 2-pin GND of the buck chip UQ2 is connected to the system reference ground. The capacitor CQ2 is connected in parallel between the 1-pin BST port and the 6-pin Between the SW ports, the 6-pin SW port of the buck chip UQ2 is connected to the first end of the inductor LQ1, the first end of the capacitor CLQ1 and the capacitor CQ12 are connected in parallel to the second end of the inductor LQ1, the second end of the capacitor CLQ1 and the capacitor CQ12 are connected in parallel to the system reference ground, the second end of the inductor LQ1 is connected to the emitter of the transistor CQ12, the collector of the transistor CQ12 is connected to the 3-pin FB port of the buck chip UQ2, the first end of the resistor R2 and the capacitor CQ13 are connected in parallel to the base of the transistor CQ12, the second end of the resistor R2 and the capacitor CQ13 are connected in parallel to the positive electrode of the diode VD27, the resistor R1, the resistor R3 and resistor R4 are connected in parallel between the emitter of transistor CQ12 and the positive electrode of diode VD27. The negative electrode of diode VD27 is connected to the supercapacitor charging terminal CAP. Resistors RQ3 and RQ4 are connected in series and then connected in parallel with capacitor CQ4. A first end of capacitor CQ4 is connected to the supercapacitor charging terminal CAP. The first end of capacitor CQ3 and resistor RQ5 in parallel is connected to the 3-pin FB port of buck chip UQ2 and the second end of capacitor CQ4. The second end of capacitor CQ3 and resistor RQ5 in parallel is connected to the system reference ground GND. Resistors RE11 and RE12 are connected in series between the supercapacitor charging terminal CAP and the system reference ground GND.
[0008] On the basis of the above solution, the charging circuit further includes a capacitor CE1 , and the capacitor CE1 is connected in parallel with the resistor RE12 .
[0009] Preferably, the discharge circuit includes a boost chip UQ3, a capacitor CQ36, a capacitor CQ31, a capacitor CQ32, a capacitor CQ33, a capacitor CQ11, a capacitor CQ34, an electrolytic capacitor EQ31, a resistor RQ15, a resistor RQ16, a resistor RQ40, a resistor RQ33, a resistor RQ342, a resistor RQ31, a resistor RQ34, a resistor RQ35, an inductor LQ3, a diode DQ31, a diode DQ32, a diode DQ33, a transistor QC1, and a PMOS tube Q11. The first end of the capacitor CQ36 and the resistor RQ35 connected in parallel is connected to the supercapacitor charging terminal CAP and connected to the PMOS tube. The source of the S transistor Q11 and the second end are connected to the first end of the resistor RQ40. The second end of the resistor RQ40 is connected to the collector of the transistor QC1. The base of the transistor QC1 is connected in series with the resistor RQ16 and then connected to the power supply VDD3V3. The emitter of the transistor QC1 is connected to the discharge control pin CORE_POWER of the MCU system. The gate of the PMOS transistor Q11 is connected to the first end of the resistor RQ40. The drain of the PMOS transistor Q11 is connected to the switch control terminal CAP' of the boost chip UQ3. The SW terminal of the 1st pin of the boost chip UQ3 is connected in series with the inductor LQ3 and then connected to the switch control terminal CAP'. The capacitor CQ31 and the capacitor C Q32 is connected in parallel between the switch control terminal CAP' and the 2-pin GND terminal of the boost chip UQ3. The 2-pin GND terminal of the boost chip UQ3 is connected to the system reference ground. The 1-pin SW terminal of the boost chip UQ3 is connected to the positive electrode of the diode DQ31. The negative electrode of the diode DQ31 is connected to the first end of the capacitor CQ33 and the first end of the resistor RQ31. The second end of the capacitor CQ33 and the second end of the resistor RQ31 are connected to the 3-pin FB terminal of the boost chip UQ3. The resistor RQ33 and the resistor RQ342 are connected in parallel between the 3-pin FB terminal of the boost chip UQ3 and the system reference ground. The resistor RQ35 is connected between the 4-pin EN terminal of the boost chip UQ3 and the 5-pin V S terminal, the 4-pin EN terminal of the boost chip UQ3 is simultaneously connected to the first end of the resistor RQ34 and the first end of the capacitor CQ11, the second end of the resistor RQ34 is connected to the switch control terminal CAP', the second end of the capacitor CQ11 is connected to the system reference ground, the 5-pin VS terminal of the boost chip UQ3 is connected to the power supply +9.6V, the electrolytic capacitor EQ31 and the capacitor CQ34 are connected in parallel between the 5-pin VS terminal of the boost chip UQ3 and the system reference ground, the diode DQ32 and the diode DQ33 are connected in parallel, and the positive pole is connected to the 5-pin VS terminal of the boost chip UQ3 and the negative pole is connected to DVDD12V, and DVDD12V is connected to the main circuit of the terminal equipment.
[0010] Preferably, a voltage balancing circuit is further included, and the voltage balancing circuit is used to protect the supercapacitor from overvoltage and keep the voltages of multiple supercapacitors consistent.
[0011] On the basis of the above scheme, the voltage balancing circuit includes a voltage balancing chip D11, a voltage balancing chip D12, a resistor RE1, a resistor RE3, a resistor RE6, a resistor RE8, a MOS tube QM1, a MOS tube QM2, a supercapacitor E1 and a supercapacitor E2. The two ends of the supercapacitor E1 are respectively connected to the supercapacitor charging terminal CAP and the 2-pin VSS terminal of the voltage balancing chip D11. The resistor RE1 and the resistor RE3 are connected in parallel between the supercapacitor charging terminal CAP and the drain of the MOS tube QM1. The source of the MOS tube QM1 is connected to the 2-pin VSS terminal of the voltage balancing chip D11. The MOS tube QM1 The gate is connected to the 4-pin VOUT terminal of the voltage balancing chip D11, and the 5-pin VDD terminal of the voltage balancing chip D11 is connected to the supercapacitor charging terminal CAP; the first end of the supercapacitor E2 is connected to the supercapacitor E1, and the second end is connected to the system reference ground. Resistor RE6 and resistor RE7 are connected in parallel between the first end of the supercapacitor E2 and the drain of the MOS tube QM2. The source of the MOS tube QM2 is connected to the 2-pin VSS terminal of the voltage balancing chip D12. The gate of the MOS tube QM2 is connected to the 4-pin VOUT terminal of the voltage balancing chip D12, and the 5-pin VDD terminal of the voltage balancing chip D12 is connected to the first end of the supercapacitor E2.
[0012] Based on the above solution, the voltage balancing circuit further includes a resistor RQ1 and a resistor RQ2. The resistor RQ1 is connected between the supercapacitor charging terminal CAP and the gate of the MOS transistor QM1, and the resistor RQ2 is connected between the first terminal of the supercapacitor E2 and the gate of the MOS transistor QM2.
[0013] The beneficial effects of the present invention are as follows: it provides a supercapacitor charge and discharge management module based on a temperature monitoring circuit, which can ensure that the terminal device can continue to operate for no less than 3 minutes when the mains power is cut off, can achieve a longer backup power, and is suitable for different terminal devices; the design of the temperature monitoring circuit can effectively monitor and control the operation of the charging circuit in a high-temperature environment. When the set high temperature of 93°C is reached, the charging of the supercapacitor is automatically disconnected in time, and when the environment returns to 60°C, charging is restarted, thereby improving the service life of the supercapacitor while ensuring the safety of the entire modular product. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 : Principle block diagram of the utility model;
[0015] Figure 2 : Circuit diagram of the temperature monitoring circuit of the utility model;
[0016] Figure 3 : Circuit diagram of the charging circuit of the utility model;
[0017] Figure 4 : Circuit diagram of the voltage equalizing circuit of the utility model;
[0018] Figure 5 : Circuit diagram of the discharge circuit of the utility model;
[0019] Figure 6 : Schematic diagram of the appearance structure of the utility model. DETAILED DESCRIPTION
[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments:
[0021] In this utility model, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; they can refer to direct connection or indirect connection through an intermediate medium; they can refer to internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on specific circumstances.
[0022] In the description of the present invention, it should be understood that the terms "center", "length", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.
[0023] like Figures 1 to 6As shown, a supercapacitor charge and discharge management module based on a temperature monitoring circuit includes an MCU system, a charging circuit, a temperature monitoring circuit, and a discharge circuit. The MCU system outputs a control signal BAT_CONTRL to the charging circuit through a charging control pin, and the MCU system outputs a discharge signal CORE_POWER to the discharge circuit through a discharge control pin. The charging circuit is used to charge supercapacitors E1 and E2. In this embodiment, the specifications of supercapacitors E1 and E2 are 3V and 180F. The temperature monitoring circuit is used to detect the real-time temperature of the charging environment in which the supercapacitor is located. When the capacitor temperature is higher than a predetermined temperature, the temperature monitoring circuit controls the charging circuit to stop charging the supercapacitor. When the temperature returns to the set value, power is supplied to the supercapacitor again. The discharge circuit is used to control the supercapacitor to supply power to the load circuit. Specifically, the discharge circuit obtains a feedback output voltage through a boost chip, continuously supplies power to the load circuit, and realizes the collection and reporting of power consumption data and power outage records when the power is off.
[0024] The temperature monitoring circuit includes a voltage detection chip N761, a resistor R218, a resistor R219, a resistor R36, a thermistor RT5 and a capacitor C135. The thermistor RT5 is a negative temperature coefficient thermistor. The voltage detection chip N761 is an open drain output chip. The pin 1 Vout end of the voltage detection chip N761 is the output end EN_C. The resistance of the resistor R36 is 10kΩ. One end of the resistor R36 is connected to the voltage VDD3V3, and the other end is connected to the pin 1 Vout end of the voltage detection chip N761. In this embodiment, the resistor R218 The resistance of resistor R219 is 360Ω, the resistance of resistor R219 is 1.5kΩ, one end of resistor R218 is connected to voltage VDD3V3, and the other end is connected to the first end of resistor R219 and the Vdd terminal of pin 2 of the voltage detection chip N761, the second end of resistor R219 is connected to the first end of the thermistor RT5, the second end of the thermistor RT5 is connected to the GND terminal of pin 3 of the voltage detection chip N761, the GND terminal of pin 3 of the voltage detection chip N761 is connected to the system reference ground, and capacitor C135 is connected in parallel between the first end of resistor R219 and the second end of the thermistor RT5.
[0025] The charging circuit includes a step-down chip UQ2, a diode DU1, a diode DU2, a diode VD27, a transistor Q1, a resistor RU1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor RQ3, a resistor RQ4, a resistor RQ5, a resistor RE11, a resistor RE12, a capacitor CQ1, a capacitor CQ23, a capacitor CQ2, a capacitor CLQ1, a capacitor CQ12, a capacitor CQ13, a capacitor CQ3, a capacitor CQ4 and an inductor LQ1, wherein the positive electrodes of the diode DU1 and the diode DU2 are connected in parallel and then connected to the 4-pin EN port of the step-down chip UQ2, the negative electrode of the diode DU1 is connected to the output terminal EN_C of the temperature monitoring circuit, the positive electrode of the diode DU1 is connected to one end of the resistor RU1, and the other end of the resistor RU1 is connected to the output terminal EN_C of the temperature monitoring circuit. One end is connected to the power supply VDD3V3, and the cathode of diode DU2 is connected to the MCU system's charge control pin BAT_CONTRL. Pin 4 of the buck chip UQ2 is controlled by AND gate logic. The control principle is as follows: When the output EN_C of pin 1 of the voltage detection chip N761 is high, the charge control pin BAT_CONTRL of the MCU's I / O port is set to low. At this time, the enable pin of pin 4 of the buck chip UQ2 is low, the enable pin is turned off, the buck chip UQ2 does not operate, and the supercapacitor does not charge. When the charge control pin BAT_CONTRL of the MCU's I / O port is set to high, the enable pin of pin 4 of the buck chip UQ2 is high, the enable pin is turned on, the buck chip UQ2 starts operating, and the supercapacitor starts charging. Using EN_C and BAT_CONTRL, the AND gate logic controls the opening and closing of pin 4 of the buck chip UQ2, thereby controlling the operation of the buck chip UQ2. Capacitor CQ1 and capacitor CQ23 are connected in parallel between the 5-pin IN port and the 2-pin GND port of the buck chip UQ2. The 5-pin IN port of the buck chip UQ2 is connected to the +12V voltage, and the 2-pin GND of the buck chip UQ2 is connected to the system reference ground. Capacitor CQ2 is connected in parallel between the 1-pin BST port and the 6-pin SW port of the buck chip UQ2. The 6-pin SW port of the buck chip UQ2 is connected to the first end of the inductor LQ1. After the capacitor CLQ1 and capacitor CQ12 are connected in parallel, the first end is connected to the second end of the inductor LQ1. The second end of the capacitor CLQ1 and capacitor CQ12 are connected in parallel. Connect to the system reference ground. The second end of inductor LQ1 is connected to the emitter of transistor CQ12. The collector of transistor CQ12 is connected to pin 3 of step-down chip UQ2. The first end of resistor R2 and capacitor CQ13 connected in parallel is connected to the base of transistor CQ12. The second end of resistor R2 and capacitor CQ13 connected in parallel is connected to the anode of diode VD27. Resistors R1, R3, and R4 are connected in parallel between the emitter of transistor CQ12 and the anode of diode VD27 to adjust the supercapacitor charging current, thereby controlling the supercapacitor charging time.In this embodiment, the resistance values of resistors R1, R3, and R4 are all 3Ω, and the on-state voltage drop of transistor Q1 is approximately 0.6V, so the charging current is approximately 383mA. The charging current can be adjusted by adjusting the resistance values of resistors R1, R3, and R4 or increasing or decreasing the corresponding resistors. The cathode of diode VD27 is connected to the supercapacitor charging terminal CAP. Resistors RQ3 and RQ4 are connected in series and then in parallel with capacitor CQ4. A first end of capacitor CQ4 is connected to the supercapacitor charging terminal CAP. The first end of the parallel connection of capacitor CQ3 and resistor RQ5 is connected to the 3-pin FB port of the buck chip UQ2 and the second end of capacitor CQ4. The second end of the parallel connection of capacitor CQ3 and resistor RQ5 is connected to the system reference ground GND. The 3-pin FB terminal of the buck chip UQ2 is the feedback terminal. Resistors RQ3, RQ4, and RQ5 are feedback resistors of the buck chip UQ2, used to set the feedback output voltage of the buck chip UQ2. In this embodiment, the feedback voltage is 5.2V. The resistance of resistor RQ3 is 10kΩ, the resistance of resistor RQ4 is 1kΩ, and the resistance of resistor RQ5 is 2kΩ. Resistors RE11 and RE12 are connected in series between the supercapacitor charging terminal CAP and the system reference ground GND. To detect the supercapacitor's charging voltage, the MCU's I / O port, CAP_check, is used to sample the supercapacitor voltage. A 1:1 sampling resistor ratio is used in the hardware circuit design, so the voltage sampled by the I / O port, CAP_check, is half the supercapacitor's voltage. During the actual charging process, the supercapacitor's charging voltage can be detected in real time, providing a basis for turning the charging control pin, BAT_CONTRL, on and off.
[0026] When the working environment reaches 93°C, the resistance of thermistor RT5 will decrease. At this time, the Vdd input terminal of pin 2 of the voltage detection chip N761 will detect a voltage of 2.9V. At this time, the output EN_C of the Vout terminal of pin 1 of N761 is low, the buck chip enable of the charging circuit becomes low, the DC-DC buck chip UQ2 will stop working, and the supercapacitor will no longer continue to charge, ensuring the safety of the supercapacitor.
[0027] Preferably, the charging circuit further includes a capacitor CE1 , which is connected in parallel with the resistor RE12 . The capacitor CE1 can be installed or removed according to actual needs.
[0028] The discharge circuit includes a boost chip UQ3, a capacitor CQ36, a capacitor CQ31, a capacitor CQ32, a capacitor CQ33, a capacitor CQ11, a capacitor CQ34, an electrolytic capacitor EQ31, a resistor RQ15, a resistor RQ16, a resistor RQ40, a resistor RQ33, a resistor RQ342, a resistor RQ31, a resistor RQ34, a resistor RQ35, an inductor LQ3, a diode DQ31, a diode DQ32, a diode DQ33, a transistor QC1, and a PMOS tube Q11. The first end of CQ36 connected in parallel with the resistor RQ35 is connected to the supercapacitor charging terminal CAP and connected to the source of the PMOS tube Q11. The second end is connected to the first end of the resistor RQ40. The second end of the resistor RQ40 is connected to the collector of the transistor QC1. The base of the transistor QC1 is connected in series with the resistor RQ16 and then connected to the power supply VDD3V3. The emitter of the transistor QC1 is connected to the discharge control pin CORE_POWER of the MCU system, thereby controlling the opening and closing of the boost chip UQ3 through the MCU system. The gate of the PMOS transistor Q11 is connected to the first end of the resistor RQ40, and the drain of the PMOS transistor Q11 is connected to the switch control terminal CAP' of the boost chip UQ3. The SW terminal of the 1st pin of the boost chip UQ3 is connected in series with the inductor LQ3 and then connected to the switch control terminal CAP'. The capacitor CQ31 and the capacitor CQ32 are connected in parallel between the switch control terminal CAP' and the GND terminal of the 2nd pin of the boost chip UQ3. The GND terminal of the 2nd pin of the boost chip UQ3 is connected to the system reference ground. The SW terminal of the 1st pin of the boost chip UQ3 is connected to the anode of the diode DQ31. The diode DQ31 The negative electrode is connected to the first end of the capacitor CQ33 and the first end of the resistor RQ31, the second end of the capacitor CQ33 and the second end of the resistor RQ31 are connected to the 3-pin FB end of the boost chip UQ3, and the resistor RQ33 and the resistor RQ342 are connected in parallel between the 3-pin FB end of the boost chip UQ3 and the system reference ground as feedback resistors. In this embodiment, the power supply voltage of the terminal device is 12V, and the feedback output voltage is set to 9.6V. The resistance of the resistor RQ31 is 51kΩ, the resistance of the resistor RQ33 is 240kΩ, and the resistance of the resistor RQ33 is 7.5kΩ. Resistor RQ35 is connected between the EN terminal (pin 4) and the VS terminal (pin 5) of the boost chip UQ3. The EN terminal (pin 4) of the boost chip UQ3 is the enable terminal, which is also connected to the first end of resistor RQ34 and the first end of capacitor CQ11. The second end of resistor RQ34 is connected to the switch control terminal CAP', and the second end of capacitor CQ11 is connected to the system reference ground. When the PMOS tube Q11 is turned on, the voltage at the switch control terminal CAP' reaches the turn-on threshold of the EN terminal (pin 4) of the boost chip UQ3, and the boost chip UQ3 is turned on.The 5-pin VS terminal of the boost chip UQ3 is connected to the power supply +9.6V, the electrolytic capacitor EQ31 and the capacitor CQ34 are connected in parallel between the 5-pin VS terminal of the boost chip UQ3 and the system reference ground, the diode DQ32 and the diode DQ33 are connected in parallel, and the positive pole is connected to the 5-pin VS terminal of the boost chip UQ3 and the negative pole is connected to DVDD12V. DVDD12V is connected to the main circuit of the terminal device to power the terminal device.
[0029] It also includes a voltage balancing circuit, which is used to protect the supercapacitor from overvoltage and keep the voltages of multiple supercapacitors consistent. The voltage balancing circuit includes a voltage balancing chip D11, a voltage balancing chip D12, a resistor RE1, a resistor RE3, a resistor RE6, a resistor RE8, a MOS tube QM1, a MOS tube QM2, a supercapacitor E1 and a supercapacitor E2. The two ends of the supercapacitor E1 are respectively connected to the supercapacitor charging terminal CAP and the 2-pin VSS terminal of the voltage balancing chip D11. The resistor RE1 and the resistor RE3 are connected in parallel between the supercapacitor charging terminal CAP and the drain of the MOS tube QM1. The source of the MOS tube QM1 is connected to the 2-pin VSS terminal of the voltage balancing chip D11, and the gate of the MOS tube QM1 is connected to Pin 4 VOUT and pin 5 VDD of the voltage balancing chip D11 are connected to the supercapacitor charging terminal CAP; the first end of the supercapacitor E2 is connected to the supercapacitor E1, and the second end is connected to the system reference ground. Resistors RE6 and RE7 are connected in parallel between the first end of the supercapacitor E2 and the drain of the MOS transistor QM2. The source of the MOS transistor QM2 is connected to the pin 2 VSS of the voltage balancing chip D12. The gate of the MOS transistor QM2 is connected to the pin 4 VOUT of the voltage balancing chip D12. The pin 5 VDD of the voltage balancing chip D12 is connected to the first end of the supercapacitor E2.
[0030] Based on the above solution, the voltage balancing circuit further includes a resistor RQ1 and a resistor RQ2. The resistor RQ1 is connected between the supercapacitor charging terminal CAP and the gate of the MOS transistor QM1, and the resistor RQ2 is connected between the first terminal of the supercapacitor E2 and the gate of the MOS transistor QM2.
[0031] The present invention is described above by way of examples, but the present invention is not limited to the above specific embodiments. Any changes or modifications based on the present invention fall within the scope of protection claimed by the present invention.
Claims
1. A supercapacitor charge and discharge management module based on a temperature monitoring circuit, characterized in that: The system includes an MCU system, a charging circuit, a temperature monitoring circuit, and a discharge circuit. The MCU system outputs a control signal to the charging circuit through a charging control pin, and the MCU system outputs a discharge signal to the discharge circuit through a discharge control pin. The charging circuit is used to charge the supercapacitor. The temperature monitoring circuit is used to detect the real-time temperature of the charging environment in which the supercapacitor is located. When the capacitor temperature is higher than a predetermined temperature, the temperature monitoring circuit controls the charging circuit to stop charging the supercapacitor. The discharge circuit controls the supercapacitor to supply power to the load circuit. The charging circuit includes a step-down chip UQ2, a diode DU1, a diode DU2, a diode VD27, a transistor Q1, a resistor RU1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor RQ3, a resistor RQ4, a resistor RQ5, a resistor RE11, a resistor RE12, a capacitor CQ1, a capacitor CQ23, a capacitor CQ2, a capacitor CLQ1, a capacitor CQ12, a capacitor CQ13, a capacitor CQ3, a capacitor CQ4 and an inductor LQ1, wherein the positive poles of the diode DU1 and the diode DU2 are connected in parallel and then connected to the 4-pin EN port of the step-down chip UQ2, and the negative pole of the diode DU1 is connected to the temperature monitoring circuit. The output end EN_C of the circuit, the cathode of diode DU2 is connected to the charging control pin BAT_CONTRL of the MCU system, the 4th pin of the buck chip UQ2 is controlled by AND gate logic, the anode of diode DU1 is connected to one end of resistor RU1, the other end of resistor RU1 is connected to the power supply VDD3V3, capacitor CQ1 and capacitor CQ23 are connected in parallel between the 5-pin IN port and the 2-pin GND port of the buck chip UQ2, the 5-pin IN port of the buck chip UQ2 is connected to the +12V voltage, the 2-pin GND of the buck chip UQ2 is connected to the system reference ground, and capacitor CQ2 is connected in parallel between the 1-pin BST port and the 6-pin SW port of the buck chip UQ2. Between the ports, the 6-pin SW port of the buck chip UQ2 is connected to the first end of the inductor LQ1, the first end of the capacitor CLQ1 and the capacitor CQ12 are connected in parallel to the second end of the inductor LQ1, the second end of the capacitor CLQ1 and the capacitor CQ12 are connected in parallel to the system reference ground, the second end of the inductor LQ1 is connected to the emitter of the transistor CQ12, the collector of the transistor CQ12 is connected to the 3-pin FB port of the buck chip UQ2, the first end of the resistor R2 and the capacitor CQ13 are connected in parallel to the base of the transistor CQ12, the second end of the resistor R2 and the capacitor CQ13 are connected in parallel to the positive electrode of the diode VD27, the resistor R1 and the resistor R 3 and resistor R4 are connected in parallel between the emitter of transistor CQ12 and the anode of diode VD27. The cathode of diode VD27 is connected to the supercapacitor charging terminal CAP. Resistors RQ3 and RQ4 are connected in series and then connected in parallel with capacitor CQ4. A first end of capacitor CQ4 is connected to the supercapacitor charging terminal CAP. A first end of the capacitor CQ3 and resistor RQ5 are connected in parallel to the 3-pin FB port of the buck chip UQ2 and the second end of capacitor CQ4. A second end of the capacitor CQ3 and resistor RQ5 are connected in parallel to the system reference ground GND. Resistors RE11 and RE12 are connected in series between the supercapacitor charging terminal CAP and the system reference ground GND.
2. A supercapacitor charge and discharge management module based on a temperature monitoring circuit according to claim 1, characterized in that: The temperature monitoring circuit includes a voltage detection chip N761, a resistor R218, a resistor R219, a resistor R36, a thermistor RT5 and a capacitor C135. The thermistor RT5 is a negative temperature coefficient thermistor. The Vout terminal of pin 1 of the voltage detection chip N761 is the output terminal EN_C. One end of the resistor R36 is connected to the voltage VDD3V3, and the other end is connected to the Vout terminal of pin 1 of the voltage detection chip N761. One end of the resistor R218 is connected to the voltage VDD3V3, and the other end is connected to the first end of the resistor R219 and the Vdd terminal of pin 2 of the voltage detection chip N761. The second end of the resistor R219 is connected to the first end of the thermistor RT5, the second end of the thermistor RT5 is connected to the GND terminal of pin 3 of the voltage detection chip N761, the GND terminal of pin 3 of the voltage detection chip N761 is connected to the system reference ground, and the capacitor C135 is connected in parallel between the first end of the resistor R219 and the second end of the thermistor RT5.
3. The supercapacitor charge and discharge management module based on a temperature monitoring circuit according to claim 1, characterized in that: The charging circuit further includes a capacitor CE1 , and the capacitor CE1 is connected in parallel with the resistor RE12 .
4. The supercapacitor charge and discharge management module based on a temperature monitoring circuit according to claim 1, characterized in that: The discharge circuit includes a boost chip UQ3, a capacitor CQ36, a capacitor CQ31, a capacitor CQ32, a capacitor CQ33, a capacitor CQ11, a capacitor CQ34, an electrolytic capacitor EQ31, a resistor RQ15, a resistor RQ16, a resistor RQ40, a resistor RQ33, a resistor RQ342, a resistor RQ31, a resistor RQ34, a resistor RQ35, an inductor LQ3, a diode DQ31, a diode DQ32, a diode DQ33, a transistor QC1, and a PMOS transistor Q11. The first end of the capacitor CQ36 and the resistor RQ35 connected in parallel is connected to the supercapacitor charging terminal CAP and connected to the PMOS transistor Q The source of 11 is connected to the first end of the resistor RQ40, the second end of the resistor RQ40 is connected to the collector of the transistor QC1, the base of the transistor QC1 is connected in series with the resistor RQ16 and then connected to the power supply VDD3V3, the emitter of the transistor QC1 is connected to the discharge control pin CORE_POWER of the MCU system, the gate of the PMOS tube Q11 is connected to the first end of the resistor RQ40, the drain of the PMOS tube Q11 is connected to the switch control terminal CAP' of the boost chip UQ3, the 1-pin SW terminal of the boost chip UQ3 is connected in series with the inductor LQ3 and then connected to the switch control terminal CAP', the capacitor CQ31 and the capacitor CQ3 2 is connected in parallel between the switch control terminal CAP' and the 2-pin GND terminal of the boost chip UQ3, the 2-pin GND terminal of the boost chip UQ3 is connected to the system reference ground, the 1-pin SW terminal of the boost chip UQ3 is connected to the positive electrode of the diode DQ31, the negative electrode of the diode DQ31 is connected to the first end of the capacitor CQ33 and the first end of the resistor RQ31, the second end of the capacitor CQ33 and the second end of the resistor RQ31 are connected to the 3-pin FB terminal of the boost chip UQ3, the resistor RQ33 and the resistor RQ342 are connected in parallel between the 3-pin FB terminal of the boost chip UQ3 and the system reference ground, and the resistor RQ35 is connected between the 4-pin EN terminal of the boost chip UQ3 and the 5-pin VS The 4-pin EN terminal of the boost chip UQ3 is connected to the first end of the resistor RQ34 and the first end of the capacitor CQ11 at the same time. The second end of the resistor RQ34 is connected to the switch control terminal CAP'. The second end of the capacitor CQ11 is connected to the system reference ground. The 5-pin VS terminal of the boost chip UQ3 is connected to the power supply +9.6V. The electrolytic capacitor EQ31 and the capacitor CQ34 are connected in parallel between the 5-pin VS terminal of the boost chip UQ3 and the system reference ground. The diode DQ32 and the diode DQ33 are connected in parallel, and the positive electrode is connected to the 5-pin VS terminal of the boost chip UQ3 and the negative electrode is connected to DVDD12V. DVDD12V is connected to the main circuit of the terminal device.
5. The supercapacitor charge and discharge management module based on a temperature monitoring circuit according to claim 1, characterized in that: The device also includes a voltage balancing circuit, which is used to protect the supercapacitor from overvoltage and keep the voltages of multiple supercapacitors consistent.
6. A supercapacitor charge and discharge management module based on a temperature monitoring circuit according to claim 5, characterized in that: The voltage balancing circuit includes a voltage balancing chip D11, a voltage balancing chip D12, a resistor RE1, a resistor RE3, a resistor RE6, a resistor RE8, a MOS transistor QM1, a MOS transistor QM2, a supercapacitor E1 and a supercapacitor E2. The two ends of the supercapacitor E1 are respectively connected to the supercapacitor charging terminal CAP and the 2-pin VSS terminal of the voltage balancing chip D11. The resistor RE1 and the resistor RE3 are connected in parallel between the supercapacitor charging terminal CAP and the drain of the MOS transistor QM1. The source of the MOS transistor QM1 is connected to the 2-pin VSS terminal of the voltage balancing chip D11. The gate of the MOS transistor QM1 is connected to Pin 4 VOUT and pin 5 VDD of the voltage balancing chip D11 are connected to the supercapacitor charging terminal CAP; the first end of the supercapacitor E2 is connected to the supercapacitor E1, and the second end is connected to the system reference ground. Resistors RE6 and RE7 are connected in parallel between the first end of the supercapacitor E2 and the drain of the MOS transistor QM2. The source of the MOS transistor QM2 is connected to the pin 2 VSS of the voltage balancing chip D12. The gate of the MOS transistor QM2 is connected to the pin 4 VOUT of the voltage balancing chip D12. The pin 5 VDD of the voltage balancing chip D12 is connected to the first end of the supercapacitor E2.
7. A supercapacitor charge and discharge management module based on a temperature monitoring circuit according to claim 6, characterized in that: The voltage balancing circuit further includes a resistor RQ1 and a resistor RQ2. The resistor RQ1 is connected between the supercapacitor charging terminal CAP and the gate of the MOS transistor QM1. The resistor RQ2 is connected between the first terminal of the supercapacitor E2 and the gate of the MOS transistor QM2.