Control circuit for balancing multipath load output

Abstract

The utility model relates to the technical field of large current control, in particular to a control circuit for balancing multipath load output, which comprises a low-dropout linear voltage regulator U4, a low-dropout linear voltage regulator U9, a low-dropout linear voltage regulator U10, resistors R85, R86, R87, R88, R89, R90, R91 and R92, ohmic resistors R93 and R94, sampling resistors R133 and R134, current limiting resistors R135, R136 and R137, output filter capacitors C32, C56, C57, CE2, C33, C34, C35, C30, C31, C60, C28 and C29, input filter capacitors C58, C59, C61, C62 and C63, output filter capacitors C32, C56, C57, CE3, C33, when the whole system of the control circuit for balancing multi-path load output works, the output of each path of small power supply is circularly controlled through the general control end to achieve parallel output of large current, a single path of power supply is controlled not to be overloaded, and the output of each path of power supply is balanced.

Description

Technical Field

[0001] The utility model relates to the technical field of large current control, in particular to a control circuit for balancing multi-channel load outputs. Background Art

[0002] For example, in server cluster applications, in some high-current application scenarios, the general approach is to find power chips that meet the specification requirements. However, there are limitations in chip selection and low redundancy in the circuit application.

[0003] Existing solutions use a PMIC to manage multiple power outputs. The PMIC uniformly outputs a PWM signal and detects the current of each power supply. Current balancing is achieved by distributing different PWM signals. For example, in a prior art multi-output switching power supply circuit, the multi-output switching power supply directly samples the multiple outputs of multiple output rectifier and filter modules. The sampled signals are then weighted and fed back to the output control module, which then adjusts the outputs of the multiple output rectifier modules accordingly. Because the outputs of the multiple output rectifier and filter modules are directly sampled and then weighted and fed back to the output control module, the multi-output switching power supply does not require a feedback winding for output adjustment, resulting in relatively high control accuracy. However, this type of technical solution utilizes a dedicated custom chip, lacks universal applicability, is expensive, and has poor channel controllability. Current redundancy approaches use two or more identical high-current power supplies, which do not fully participate in operation and only intervene when a single node power supply fails, resulting in wasted resources and increased costs. Furthermore, conventional parallel connection methods can lead to uneven workloads among the LDOs. If a single LDO is overloaded, the others will not participate in the power supply, causing damage to the power supply system. Utility Model Content

[0004] The main purpose of the utility model is to provide a control circuit for balanced multi-channel load output, including a low-voltage dropout linear regulator U4, a low-voltage dropout linear regulator U9, a low-voltage dropout linear regulator U10, resistors R85, R86, R87, R88, R89, R90, R91, R92, ohmic resistors R93, R94, sampling resistors R133, R134, current limiting resistors R135, R136, R137, output filter capacitors C32, C56, C57, CE2, C33, C34, C35, C30, C31, C60, C28, C29, input filter capacitors C58, C59, C61, C62, C63;

[0005] Among them, the 3rd pin of the low-voltage difference linear regulator U4 is connected to the input current sampling resistor R133 and the input filter capacitor C58, the 3rd pin of the low-voltage difference linear regulator U9 is connected to the sampling resistor 134 and the input filter capacitor C61, and the 1st pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R137.

[0006] Preferably, the 1st Pin of the low-voltage difference linear regulator U4 is connected to the resistor R85, the 2nd Pin of the low-voltage difference linear regulator U4 is connected to the resistor R88, the other end of the input filter capacitor C58 is grounded, the 4th Pin of the low-voltage difference linear regulator U4 is connected to the input filter capacitor C59, and the other end of the input filter capacitor C58 is grounded.

[0007] Preferably, the 6th pin of the low-voltage difference linear regulator U4 is connected to the 6th pin of the low-voltage difference linear regulator U9, and the ohmic resistors R93 and R94 are connected between the two. One end of the output filter capacitors C32, C56, C57, and C28 is connected to the 6th pin of the low-voltage difference linear regulator U4, and the other end is grounded. One end of the output filter capacitors C30, C31, C60, and C29 is connected to the 6th pin of the low-voltage difference linear regulator U9, and the other end is grounded. The low-voltage difference linear regulator U4 and the low-voltage difference linear regulator U9 are connected in parallel and connected to the output filter capacitors CE2, C33, C34, and C35, and the 5th, 8th, and 9th pins of the low-voltage difference linear regulator U4 are grounded.

[0008] Preferably, the 1st Pin of the low-voltage difference linear regulator U9 is connected to the resistor R86, the 2nd Pin of the low-voltage difference linear regulator U9 is connected to the resistor R87, the other end of the input filter capacitor C61 is grounded, the 4th Pin of the low-voltage difference linear regulator U9 is connected to the input filter capacitor C62, the resistors R91 and R92 are connected in parallel to the 7th Pin of the low-voltage difference linear regulator U9, and the 5th, 8th and 9th Pins of the low-voltage difference linear regulator U9 are grounded.

[0009] Preferably, the 2nd pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R136, the 3rd pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R135, the 4th pin of the low-voltage difference linear regulator U10 is grounded, and the 8th pin of the low-voltage difference linear regulator U10 is connected to the input filter capacitor C63.

[0010] Preferably, the sampling signal INPUT SENSE1 is connected to the 2nd Pin inverting input terminal of the low-voltage difference linear regulator U10 through the current limiting resistor R136, and the 7th Pin output feedback point FLOW CTRL of the low-voltage difference linear regulator U4 is connected to the 1st Pin output terminal of the low-voltage difference linear regulator U10 through the current limiting resistor R137.

[0011] Preferably, the sampling signal INPUT SENSE2 is connected to the 3rd Pin non-inverting input terminal of the low voltage drop linear regulator U10 through the current limiting resistor R135.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] In the present invention, when the low-voltage difference linear regulator is fully loaded, the current of the sampling resistor increases, the low-voltage difference linear regulator is in a low-load state, the current of the sampling resistor is smaller than the current, and since INPUT SENSE2 is connected to the in-phase control end of the low-voltage difference linear regulator, and INPUT SENSE1 is connected to the inverting control end of the low-voltage difference linear regulator, the output of the low-voltage difference linear regulator is high at this time, and the FLOW CTRL signal is transmitted through the current limiting resistor to raise the output of the low-voltage difference linear regulator, so that the low-voltage difference linear regulator participates in the power supply to the system load through the ohmic resistor. When the low-voltage difference linear regulator reaches the full-load state, the current of the sampling resistor is greater than, and at this time, the INPUTSENSE1 on the low-voltage difference linear regulator is greater than INPUT SENSE2, the output of the low-voltage difference linear regulator is low, and the output of the low-voltage difference linear regulator is pulled down through the current limiting resistor. At this time, the low-voltage difference linear regulator participates in the power supply to the system load through the ohmic resistor. The power supply of the load is cycled back and forth to balance the output of each LDO. When the entire system is working, the universal control terminal controls the output of each small power supply in a cycle to achieve parallel output of large current and control the single power supply to prevent overload, thereby balancing the output of each power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is one of the partial circuit diagrams of the utility model;

[0015] Figure 2 This is the second partial circuit diagram of the present utility model. DETAILED DESCRIPTION

[0016] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the utility model, the following is a detailed description of the specific implementation method, structure, characteristics and effects of the present invention in combination with the accompanying drawings and preferred embodiments.

[0017] See also Figure 1 and Figure 2This embodiment provides a control circuit for balancing multiple load outputs, including a low-voltage dropout linear regulator U4, a low-voltage dropout linear regulator U9, a low-voltage dropout linear regulator U10, resistors R85, R86, R87, R88, R89, R90, R91, R92, ohmic resistors R93, R94, sampling resistors R133, R134, current limiting resistors R135, R136, R137, output filter capacitors C32, C56, C57, CE2, C33, C34, C35, C30, C31, C60, C28, C29, and input filter capacitors C58, C59, C61, C62, and C63.

[0018] Preferably, Pin 1 of the low-voltage difference linear regulator U4 is the LDO power POWER GOOD signal, indicating that the current LDO output meets the circuit settings, Pin 2 is the LDO power Enable signal, which enables the chip to work, Pin 3 is the LDO power supply, providing power input, Pin 4 is the internal control pin of the LDO, Pin 5 is the NC pin, which is used internally and not externally, Pin 6 is the output pin of the LDO, which is supplied to the system 1oad, Pin 7 is the output feedback pin of the LDO, raising it will increase the LDO output, and pulling it down will reduce the LDO output, and Pins 8 and 9 are ground pins.

[0019] The 1st pin of the low-voltage dropout linear regulator U4 is connected to the resistor R85, the 2nd pin of the low-voltage dropout linear regulator U4 is connected to the resistor R88, the 3rd pin of the low-voltage dropout linear regulator U4 is connected to the input current sampling resistor R133 and the input filter capacitor C58, the other end of the input filter capacitor C58 is grounded, and the 4th pin of the low-voltage dropout linear regulator U4 is connected to the input filter capacitor C59, and the other end of the input filter capacitor C58 is grounded.

[0020] Preferably, the 6th pin of the low-voltage difference linear regulator U4 and the 6th pin of the low-voltage difference linear regulator U9 are connected, and the ohmic resistors R93 and R94 are connected between the two. One end of the output filter capacitors C32, C56, C57, and C28 are connected to the 6th pin of the low-voltage difference linear regulator U4, and the other end is grounded. One end of the output filter capacitors C30, C31, C60, and C29 are connected to the 6th pin of the low-voltage difference linear regulator U9, and the other end is grounded. After the low-voltage difference linear regulator U4 and the low-voltage difference linear regulator U9 are connected in parallel, they are connected to the output filter capacitors CE2, C33, C34, and C35, and the 5th, 8th, and 9th pins of the low-voltage difference linear regulator U4 are grounded.

[0021] Preferably, the 1st Pin of the low-voltage difference linear regulator U9 is connected to the resistor R86, the 2nd Pin of the low-voltage difference linear regulator U9 is connected to the resistor R87, the 3rd Pin of the low-voltage difference linear regulator U9 is connected to the sampling resistor 134 and the input filter capacitor C61, the other end of the input filter capacitor C61 is grounded, the 4th Pin of the low-voltage difference linear regulator U9 is connected to the input filter capacitor C62, the resistors R91 and R92 are connected in parallel to the 7th Pin of the low-voltage difference linear regulator U9, and the 5th, 8th and 9th Pins of the low-voltage difference linear regulator U9 are grounded.

[0022] Preferably, the 1st pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R137, the 2nd pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R136, the 3rd pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R135, the 4th pin of the low-voltage difference linear regulator U10 is grounded, and the 8th pin of the low-voltage difference linear regulator U10 is connected to the input filter capacitor C63.

[0023] Preferably, the sampling signal INPUT SENSE1 is connected to the 2nd Pin inverting input terminal of the low-voltage difference linear regulator U10 through the current limiting resistor R136, the 7th Pin output feedback point FLOW CTRL of the low-voltage difference linear regulator U4 is connected to the 1st Pin output terminal of the low-voltage difference linear regulator U10 through the current limiting resistor R137, and the sampling signal INPUT SENSE2 is connected to the 3rd Pin non-inverting input terminal of the low-voltage difference linear regulator U10 through the current limiting resistor R135.

[0024] Add a general control end low-voltage difference linear regulator U10, set the input current sampling resistor R133 at the 3rd Pin VIN of the low-voltage difference linear regulator U4, use a high-precision resistor 0.1R at the current sampling point, and connect the sampling signal INPUT SENSE1 to the 2nd Pin inverting input terminal of the low-voltage difference linear regulator U10 through the current limiting resistor R136, and pull the 7th Pin output feedback point FLOW CTRL of the low-voltage difference linear regulator U4 to the 1st Pin output terminal of the low-voltage difference linear regulator U10 through the current limiting resistor R137.

[0025] The 3rd pin VIN of the second low-voltage dropout linear regulator U9 is set to the input current sampling resistor R134. The current sampling point uses a high-precision resistor 0.1R. The sampling signal INPUT SENSE2 is connected to the 3rd pin non-inverting input terminal of the low-voltage dropout linear regulator U10 through the R135 current limiting resistor;

[0026] When the low-voltage dropout linear regulator U9 is fully loaded, the current of the sampling resistor R134 increases, the low-voltage dropout linear regulator U4 is in a low-load state, and the current of the sampling resistor R133 is smaller than the current of R134. Since INPUT SENSE2 is connected to the non-inverting control terminal of the low-voltage dropout linear regulator U10, and INPUT SENSE1 is connected to the inverting control terminal of the low-voltage dropout linear regulator U10, the output of the low-voltage dropout linear regulator U10 is high, and the FLOW CTRL signal is transmitted through the current limiting resistor R137, thereby raising the output of the low-voltage dropout linear regulator U4, so that the low-voltage dropout linear regulator U4 participates in the power supply to the system load through the ohmic resistor R930;

[0027] When LDO U4 reaches full load, the current flowing through sampling resistor R133 exceeds that flowing through R134. Input Sense 1 on LDO U10 exceeds Input Sense 2, causing the output of LDO U10 to drop. Current-limiting resistor R137 pulls down the output of LDO U4. LDO U9 then participates in supplying power to the system load through ohmic resistor R94. C32, C56, C57, CE2, C33, C34, C35, C30, C31, C60, C28, and C29 are output filter capacitors, ensuring stable power output. C58, C59, C61, and C62 are LDO input filter capacitors, ensuring stable power input.

[0028] This cycle is repeated to balance the outputs of each LDO. When the entire system is working, the universal control terminal cyclically controls the output of each small power supply to achieve parallel output of large current and control the single power supply to prevent overload, balancing the output of each power supply. If a larger current supply is required, only LDOs need to be added and a universal control terminal with multiple inputs and outputs is selected.

[0029] It should be noted that LDO is a low dropout linear regulator.

[0030] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A control circuit for balancing multiple load outputs, characterized in that: Including low-voltage dropout linear regulator U4, low-voltage dropout linear regulator U9, low-voltage dropout linear regulator U10, resistors R85, R86, R87, R88, R89, R90, R91, R92, ohmic resistors R93, R94, sampling resistors R133, R134, current limiting resistors R135, R136, R137, output filter capacitors C32, C56, C57, CE2, C33, C34, C35, C30, C31, C60, C28, C29, input filter capacitors C58, C59, C61, C62, C63; Among them, the 3rd pin of the low-voltage difference linear regulator U4 is connected to the input current sampling resistor R133 and the input filter capacitor C58, the 3rd pin of the low-voltage difference linear regulator U9 is connected to the sampling resistor 134 and the input filter capacitor C61, and the 1st pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R137; The first pin of the low-voltage dropout linear regulator U4 is connected to the resistor R85, the second pin of the low-voltage dropout linear regulator U4 is connected to the resistor R88, the other end of the input filter capacitor C58 is grounded, the fourth pin of the low-voltage dropout linear regulator U4 is connected to the input filter capacitor C59, and the other end of the input filter capacitor C58 is grounded; The 6th pin of the low-voltage difference linear regulator U4 is connected to the 6th pin of the low-voltage difference linear regulator U9, and ohmic resistors R93 and R94 are connected between the two. One end of the output filter capacitors C32, C56, C57, and C28 is connected to the 6th pin of the low-voltage difference linear regulator U4, and the other end is grounded. One end of the output filter capacitors C30, C31, C60, and C29 is connected to the 6th pin of the low-voltage difference linear regulator U9, and the other end is grounded. The low-voltage difference linear regulator U4 and the low-voltage difference linear regulator U9 are connected in parallel and connected to the output filter capacitors CE2, C33, C34, and C35. The 5th, 8th, and 9th pins of the low-voltage difference linear regulator U4 are grounded. The first pin of the low-voltage dropout linear regulator U9 is connected to the resistor R86, the second pin of the low-voltage dropout linear regulator U9 is connected to the resistor R87, the other end of the input filter capacitor C61 is grounded, the fourth pin of the low-voltage dropout linear regulator U9 is connected to the input filter capacitor C62, the resistors R91 and R92 are connected in parallel to the seventh pin of the low-voltage dropout linear regulator U9, and the fifth, eighth, and ninth pins of the low-voltage dropout linear regulator U9 are grounded; The 2nd pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R136, the 3rd pin of the low-voltage difference linear regulator U10 is connected to the sampling resistor R135, the 4th pin of the low-voltage difference linear regulator U10 is grounded, and the 8th pin of the low-voltage difference linear regulator U10 is connected to the input filter capacitor C63; The sampling signal INPUT_SENSE1 is connected to the 2nd pin inverting input terminal of the low-voltage dropout linear regulator U10 through the current-limiting resistor R136, and the 7th pin output feedback point FLOW_CTRL of the low-voltage dropout linear regulator U4 is connected to the 1st pin output terminal of the low-voltage dropout linear regulator U10 through the current-limiting resistor R137; The sampling signal INPUT_SENSE2 is connected to the 3rd pin non-inverting input terminal of the low-dropout linear regulator U10 through the current-limiting resistor R135.

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