Ethernet circuit board and electronic equipment

Abstract

The utility model relates to the technical field of circuit boards, in particular to an Ethernet circuit board and electronic equipment, and the Ethernet circuit board comprises an Ethernet chip, a main control chip, a transmitting line, a receiving line, a first resistor and a second resistor. The transmitting line and the receiving line are respectively connected with the Ethernet chip and the main control chip, the transmitting line is used for transmitting a signal from the Ethernet chip to the main control chip, and the receiving line is used for transmitting the signal from the main control chip to the Ethernet chip. The first resistor is connected in series with one end, close to the Ethernet chip, of the transmitting line, and the second resistor is connected in series with one end, close to the main control chip, of the receiving line. According to the Ethernet circuit board and the electronic equipment provided by the invention, the signals of both the transmitting line and the receiving line are difficult to reflect from the signal transmitting end, so that the interference of the reflected signals on both the transmitting line and the receiving line is effectively reduced, and the system stability of data transmission is further improved.

Description

Technical Field

[0001] The present application relates to the technical field of circuit boards, and in particular to an Ethernet circuit board and electronic equipment. Background Art

[0002] With the development of technology, the intelligence level of automobiles continues to increase, the number and frequency of automotive sensors are increasing, and the amount of communication data between sensors and ECUs is increasing dramatically. This has led to higher requirements for the bandwidth and data transmission efficiency of in-vehicle Ethernet circuit boards in today's automobiles.

[0003] However, the current in-vehicle Ethernet RGMII bus is typically wired on the surface of the circuit board using the main control chip's 4*TX, TX_CLK, TX_CTL; 4*RX, RX_CLK, RX_CTL surface traces to achieve physical connection with the Ethernet chip. Although this method is simple to connect and easy to debug later, it is difficult to adjust the impedance of the above connection method, and signal reflection is very likely to occur during signal transmission, which greatly affects the stability of signal transmission. Utility Model Content

[0004] The purpose of this application is to provide an Ethernet circuit board and electronic equipment to solve, to a certain extent, the technical problems existing in the prior art that the connection method of the current in-vehicle Ethernet RGMII bus is difficult to adjust the impedance, signal reflection is very likely to occur during signal transmission, and the stability of signal transmission is greatly affected.

[0005] According to a first aspect of the present application, an Ethernet circuit board is provided, comprising an Ethernet chip, a main control chip, a transmitting circuit, a receiving circuit, a first resistor, and a second resistor, wherein the transmitting circuit and the receiving circuit are respectively connected to the Ethernet chip and the main control chip, the transmitting circuit is used to transmit a signal from the Ethernet chip to the main control chip, and the receiving circuit is used to transmit a signal from the main control chip to the Ethernet chip;

[0006] The first resistor is connected in series to an end of the transmission line close to the Ethernet chip;

[0007] The second resistor is connected in series to an end of the receiving line close to the main control chip.

[0008] Preferably, it also includes a surface layer, a first routing layer and a second routing layer, the Ethernet chip, the main control chip, the first resistor and the second resistor are all arranged on the surface layer, part of the transmitting line is arranged on the first routing layer, and part of the receiving line is arranged on the second routing layer.

[0009] Preferably, a plurality of ground shielding layers are further included, and the ground shielding layers are provided on both sides of the first routing layer and the second routing layer.

[0010] Preferably, the receiving circuit includes a first clock line, a first control line, and a plurality of first data transmission lines, the first clock line, the first control line, and the plurality of first data transmission lines are all connected in parallel between the Ethernet chip and the main control chip, and the first clock line, the first control line, and each of the first data transmission lines are provided with the first resistor;

[0011] The sending line includes a second clock line, a second control line and multiple second data transmission lines. The second clock line, the second control line and multiple second data transmission lines are all connected in parallel between the Ethernet chip and the main control chip, and the second clock line, the second control line and each of the second data transmission lines are provided with the second resistor.

[0012] Preferably, the first clock line, the first control line and the first data transmission line are of equal length.

[0013] Preferably, the second clock line, the second control line and the second data transmission line are of equal length.

[0014] Preferably, the first routing layer is provided with a first ground wire, the first ground wire is provided with a first ground via, the first ground via is connected to the ground shielding layers on both sides of the first routing layer, the first ground wire is arranged to form a first shielding ring, and the part of the receiving line arranged in the first routing layer is surrounded by the first shielding ring.

[0015] Preferably, the second routing layer is provided with a second ground wire, the second ground wire is provided with a second ground via, the second ground via is connected to the ground shielding layer on both sides of the second routing layer, the second ground wire is arranged to form a second shielding ring, and the part of the transmitting line arranged in the second routing layer is surrounded by the second shielding ring.

[0016] Preferably, the first ground line includes a first loop line and a first dividing line, the first loop line is arranged to form the first shielding ring, and the two ends of the first dividing line are respectively connected to the first loop line to separate the first shielding ring into a first ring portion and a second ring portion, the portion of the first clock line arranged in the first routing layer is surrounded by the first loop portion, and the portions of both the first control line and the first data transmission line arranged in the first routing layer are surrounded by the second loop portion.

[0017] Preferably, the second ground line includes a second loop line and a second dividing line, the second loop line is arranged to form the second shielding ring, and the two ends of the second dividing line are respectively connected to the second loop line to separate the second shielding ring into a third ring portion and a fourth ring portion, the part of the second clock line arranged in the second routing layer is surrounded by the third loop portion, and the parts of both the second control line and the second data transmission line arranged in the second routing layer are surrounded by the fourth loop portion.

[0018] According to a second aspect of the present application, an electronic device is provided, comprising the Ethernet circuit board described in any of the above technical solutions, and thus having all the beneficial technical effects of the Ethernet circuit board, which will not be described in detail here.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] The Ethernet circuit board provided by the present application is configured such that a first resistor is connected in series with one end of the transmitting line close to the Ethernet chip, and a second resistor is connected in series with one end of the receiving line close to the main control chip. In other words, the first resistor is connected in series with the signal transmitting end of the transmitting signal, and the second resistor is connected in series with the signal generating end of the receiving signal. The impedance of the transmitting line and the receiving line are then adjusted respectively by the first resistor and the second resistor, so that the signals of both the transmitting line and the receiving line are difficult to be reflected from the signal transmitting end, thereby effectively reducing the interference of the reflected signals on both the generating line and the receiving line, thereby improving the system stability of data transmission.

[0021] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 A schematic diagram of the layered structure of an Ethernet circuit board provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the wiring of the transmission line of the Ethernet circuit board provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of the wiring of the receiving line of the Ethernet circuit board provided in an embodiment of the present application;

[0026] Figure 4 A schematic diagram of the structure of the first routing layer (second routing layer) of the Ethernet circuit board provided in an embodiment of the present application;

[0027] Figure 5 A schematic structural diagram of another first routing layer (second routing layer) of the Ethernet circuit board provided in an embodiment of the present application.

[0028] Reference numerals:

[0029] 11-first routing layer; 12-second routing layer; 13-ground shielding layer; 14-surface layer; 15-bottom layer; 2-Ethernet chip; 3-main control chip; 41-first resistor; 42-second resistor; 5-transmitting line; 51-second clock line; 52-second control line; 53-second data transmission line; 6-receiving line; 61-first clock line; 62-first control line; 63-first data transmission line; 71-first ground line; 711-first loop line; 712-first dividing line; 713-first ground via; 72-second ground line; 721-second loop line; 722-second dividing line; 723-second ground via. DETAILED DESCRIPTION

[0030] The technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0031] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application.

[0032] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0033] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0035] Refer to the following Figures 1 to 5 The present invention describes an Ethernet circuit board and an electronic device according to some embodiments of the present application.

[0036] See also Figures 1 to 5 As shown, an embodiment of the first aspect of the present application provides an Ethernet circuit board, which includes an Ethernet chip 2, a main control chip 3, a transmission line 5, a receiving line 6, a first resistor 41, and a second resistor 42. The transmission line 5 and the receiving line 6 are respectively connected to the Ethernet chip 2 and the main control chip 3. The transmission line 5 is used to transmit signals from the Ethernet chip 2 to the main control chip 3, and the receiving line 6 is used to transmit signals from the main control chip 3 to the Ethernet chip 2. The first resistor 41 is connected in series to the end of the transmission line 5 close to the Ethernet chip 2, and the second resistor 42 is connected in series to the end of the receiving line 6 close to the main control chip 3.

[0037] The Ethernet circuit board provided according to the above technical features is configured such that the first resistor 41 is connected in series to one end of the transmitting line 5 close to the Ethernet chip 2, and the second resistor 42 is connected in series to one end of the receiving line 6 close to the main control chip 3. In other words, the first resistor 41 is connected in series to the signal sending end of the transmitting signal, and the second resistor 42 is connected in series to the signal generating end of the receiving signal. Then, the impedance of the transmitting line 5 and the receiving line 6 are adjusted respectively by the first resistor 41 and the second resistor 42, so that the signals of both the transmitting line 5 and the receiving line 6 are difficult to be reflected from the signal sending end, thereby effectively reducing the interference of the reflected signals on both the generating line and the receiving line 6, thereby improving the system stability of data transmission.

[0038] Preferably, the distance between the first resistor 41 and the Ethernet chip 2 may be less than 5 mm, so as to further reduce the probability of signal reflection occurring in the transmission line 5 .

[0039] Similarly, the distance between the second resistor 42 and the main control chip 3 may be less than 5 mm, so as to further reduce the probability of signal reflection occurring in the receiving circuit 6 .

[0040] Preferably, the signal line impedance of the transmitting line 5 can be 50Ω. It should be noted that the signal line impedance of the transmitting line 5 can be understood as the sum of the resistances between a certain connecting wire of the transmitting line 5 (for example, the first clock line 61, the first control line 62 or each first data transmission line 63 described below) and the first resistor 41 on the corresponding connecting wire.

[0041] Similarly, the signal line impedance of the receiving line 6 can also be 50Ω. It should be noted that the signal line impedance of the receiving line 6 can be understood as the sum of the resistances between a certain connecting wire of the receiving line 6 (for example, the second clock line 51, the second control line 52 or each second data transmission line 53 described below) and the second resistor 42 on the corresponding connecting wire.

[0042] Preferably, if Figures 1 to 3 As shown, the Ethernet circuit board may further include a surface layer 14, a first routing layer 11, and a second routing layer 12. The Ethernet chip 2, the main control chip 3, the first resistor 41, and the second resistor 42 may all be disposed on the surface layer 14. A portion of the transmission line 5 may be disposed on the first routing layer 11, and a portion of the reception line 6 may be disposed on the second routing layer 12. In this manner, the Ethernet circuit board implements routing of the transmission line 5 and the reception line 6 via the first routing layer 11 and the second routing layer 12 disposed on the inner layer, thereby improving the anti-interference capability of the signal transmission process of both the transmission line 5 and the reception line 6, enhancing the stability of signal transmission, and preventing electromagnetic interference with other components.

[0043] Optionally, the Ethernet circuit board may be further provided with a first connection via, through which the portion of the transmission line 5 provided on the surface layer 14 and the portion of the transmission line 5 provided on the first routing layer 11 are connected.

[0044] Similarly, the Ethernet circuit board may also be provided with a second connection via, through which the portion of the receiving line 6 provided on the surface layer 14 and the portion of the receiving line 6 provided on the second routing layer 12 are connected.

[0045] It should be noted that connecting circuits between different layers of a circuit board through a via structure (eg, a first connecting via and a second connecting via) is a prior art in the art and will not be described in detail here.

[0046] Preferably, if Figure 1 As shown, the Ethernet chip 2 may further include a plurality of ground shielding layers 13, and the ground shielding layers 13 are provided on both sides of the first routing layer 11 and both sides of the second routing layer 12 to further prevent interference between the signals of the receiving line 6 and the signals of the transmitting line 5.

[0047] Alternatively, as Figures 1 to 3 As shown, the Ethernet chip 2 may further include a bottom layer 15 , which may be disposed on a side of the Ethernet chip 2 facing away from the surface layer 14 to ensure the stability of the internal structure of the Ethernet chip 2 .

[0048] like Figure 3 、 Figure 4 and Figure 5 As shown in the figure, an example of the above-mentioned receiving circuit 6 is shown, and the following will refer to Figure 3 、 Figure 4 and Figure 5 The content shown describes the specific structure of the receiving line 6 and the second routing layer 12 in detail.

[0049] Preferably, if Figure 3 As shown, the receiving line 6 may include a first clock line 61, a first control line 62, and a plurality of first data transmission lines 63. The first clock line 61, the first control line 62, and the plurality of first data transmission lines 63 are all connected in parallel between the Ethernet chip 2 and the main control chip 3, and the first resistor 41 is provided on the first clock line 61, the first control line 62, and each of the first data transmission lines 63 to enable different types of signal transmission on the receiving line 6.

[0050] Preferably, if Figure 3 As shown, the first clock line 61, the first control line 62 and the first data transmission line 63 are of equal length, so that the data received / sent in the same group of signals remain consistent, which not only reduces the packet loss rate and improves the communication quality, but also greatly improves the delay problem of signal transmission and reduces the probability of communication errors.

[0051] Alternatively, as Figure 3 As shown, the first clock line 61 , the first control line 62 and the first data transmission line 63 can be wound in an arc so that the first clock line 61 , the first control line 62 and the first data transmission line 63 have the same length.

[0052] Preferably, the length errors among the first clock line 61 , the first control line 62 and the first data transmission line 63 are within ±10 mil.

[0053] Preferably, if Figure 4 and Figure 5As shown, the first routing layer 11 can be provided with a first ground wire 71, and the first ground wire 71 is provided with a first ground via 713. The first ground via 713 connects the ground shielding layer 13 on both sides of the first routing layer 11. The first ground wire 71 is surrounded to form a first shielding ring. The portion of the above-mentioned receiving line 6 arranged in the first routing layer 11 can be surrounded by the first shielding ring to shield the receiving line 6, thereby preventing electromagnetic interference problems caused by electromagnetic wave radiation, thereby eliminating the need for a shielding cover and reducing the use of power supply filter components, saving the layout space and material costs of the circuit board, and also reducing the manpower, material resources and time investment in the subsequent electromagnetic compatibility rectification. Due to the inner layer wiring of the signal, on the one hand, the signal quality is greatly improved, ensuring the stability of the system; on the other hand, the information security level is also guaranteed, effectively preventing plagiarism and tampering by others.

[0054] It should be noted that the first ground via hole mentioned above can be understood as a grounding via hole of the circuit board.

[0055] Preferably, the line width of the first ground line 71 may be no less than 1 mm to ensure the signal shielding effectiveness of the first ground line 71 .

[0056] Preferably, if Figure 4 As shown, the first ground vias 713 can be arranged at intervals along the first ground line 71 , and the distance between two adjacent first ground vias 713 is 4 mm to 6 mm to ensure the signal anti-interference capability of the first ground line 71 .

[0057] Preferably, if Figure 5 As shown, the above-mentioned first ground line 71 may include a first loop line 711 and a first separation line 712. The first loop line 711 is arranged to form a first shielding ring. The two ends of the first separation line 712 are respectively connected to the first loop line 711 to separate the first shielding ring into a first ring portion and a second ring portion. The portion of the first clock line 61 arranged on the first routing layer 11 is surrounded by the first loop portion, and the portions of the first control line 62 and the first data transmission line 63 arranged on the first routing layer 11 are surrounded by the second loop portion to prevent the signals of the first clock line 61, the first control line 62 and the first data transmission line 63 from interfering with each other.

[0058] Similarly, if Figure 2 、 Figure 4 and Figure 5 As shown in the figure, an example of the above-mentioned transmission line 5 is shown, and the following will refer to Figure 2 、 Figure 4 and Figure 5 The content shown describes the specific structure of the transmission line 5 and the first routing layer 11 in detail.

[0059] Preferably, if Figure 2As shown, the transmission line 5 may include a second clock line 51, a second control line 52, and a plurality of second data transmission lines 53. The second clock line 51, the second control line 52, and the plurality of second data transmission lines 53 are all connected in parallel between the Ethernet chip 2 and the main control chip 3, and the second clock line 51, the second control line 52, and each second data transmission line 53 are provided with the second resistor 42, so as to enable different types of signals to be transmitted on the transmission line 5.

[0060] Similarly, if Figure 2 As shown, the second clock line 51, the second control line 52 and the second data transmission line 53 are of equal length, so that the data received / sent by the same group of signals remain consistent, which not only reduces the packet loss rate and improves the communication quality, but also greatly improves the delay problem of signal transmission and reduces the probability of communication errors.

[0061] Alternatively, as Figure 3 As shown, the second clock line 51 , the second control line 52 and the second data transmission line 53 can be wound in an arc so that the lengths of the second clock line 51 , the second control line 52 and the second data transmission line 53 are equal.

[0062] Preferably, the length errors among the second clock line 51 , the second control line 52 and the second data transmission line 53 are within ±10 mil.

[0063] Similarly, if Figure 4 and Figure 5 As shown, the second routing layer 12 can be provided with a second ground wire 72, and the second ground wire 72 is provided with a second ground via 723. The second ground via 723 connects the ground shielding layer 13 on both sides of the second routing layer 12. The second ground wire 72 is formed to form a second shielding ring. The part of the transmitting line 5 arranged in the second routing layer 12 is surrounded by the second shielding ring to shield the receiving line 6, thereby preventing electromagnetic interference problems caused by electromagnetic wave radiation, thereby eliminating the need for a shielding cover and reducing the use of power supply filter components, saving the layout space and material costs of the circuit board, and also reducing the manpower, material resources and time investment in the subsequent electromagnetic compatibility rectification. Due to the inner layer wiring of the signal, on the one hand, the signal quality is greatly improved, ensuring the stability of the system; on the other hand, the information security level is also guaranteed, effectively preventing plagiarism and tampering by others.

[0064] It should be noted that, similar to the first ground via, the second ground via can also be understood as a grounding via of the circuit board.

[0065] Preferably, the width of the second ground line 72 may be no less than 1 mm to ensure the signal shielding effectiveness of the second ground line 72 .

[0066] Preferably, if Figure 4 As shown, the second ground vias 723 can be arranged at intervals along the second ground line 72 , and the distance between two adjacent second ground vias 723 is 4 mm to 6 mm to ensure the signal anti-interference capability of the second ground line 72 .

[0067] Preferably, if Figure 5 As shown, the above-mentioned second ground line 72 may include a second loop line 721 and a second separation line 722. The second loop line 721 is arranged to form a second shielding ring. The two ends of the second separation line 722 are respectively connected to the second loop line 721 to separate the second shielding ring into a third loop portion and a fourth loop portion. The portion of the second clock line 51 arranged on the second routing layer 12 is surrounded by the third loop portion, and the portions of the second control line 52 and the second data transmission line 53 arranged on the second routing layer 12 are surrounded by the fourth loop portion to prevent the signals of the second clock line 51, the second control line 52 and the second data transmission line 53 from interfering with each other.

[0068] An embodiment of the second aspect of the present application further provides an electronic device, comprising the Ethernet circuit board described in any of the above embodiments, and thus having all the beneficial technical effects of the Ethernet circuit board, which will not be repeated here.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An Ethernet circuit board, characterized in that: The invention comprises an Ethernet chip (2), a main control chip (3), a transmission line (5), a receiving line (6), a first resistor (41) and a second resistor (42), wherein the transmission line (5) and the receiving line (6) are respectively connected to the Ethernet chip (2) and the main control chip (3), the transmission line (5) is used to transmit a signal from the Ethernet chip (2) to the main control chip (3), and the receiving line (6) is used to transmit a signal from the main control chip (3) to the Ethernet chip (2); The first resistor (41) is connected in series to an end of the transmission line (5) close to the Ethernet chip (2); The second resistor (42) is connected in series to an end of the receiving circuit (6) close to the main control chip (3).

2. The Ethernet circuit board according to claim 1, wherein: The device further comprises a surface layer (14), a first wiring layer (11) and a second wiring layer (12); the Ethernet chip (2), the main control chip (3), the first resistor (41) and the second resistor (42) are all arranged on the surface layer (14); a portion of the transmitting line (5) is arranged on the first wiring layer (11); and a portion of the receiving line (6) is arranged on the second wiring layer (12).

3. The Ethernet circuit board according to claim 2, wherein: It also includes a plurality of ground shielding layers (13), and the ground shielding layers (13) are provided on both sides of the first wiring layer (11) and the second wiring layer (12).

4. The Ethernet circuit board according to claim 3, wherein: The receiving circuit (6) comprises a first clock line (61), a first control line (62) and a plurality of first data transmission lines (63); the first clock line (61), the first control line (62) and the plurality of first data transmission lines (63) are all connected in parallel between the Ethernet chip (2) and the main control chip (3); and the first resistor (41) is provided on the first clock line (61), the first control line (62) and each of the first data transmission lines (63); The transmission line (5) comprises a second clock line (51), a second control line (52) and a plurality of second data transmission lines (53); the second clock line (51), the second control line (52) and the plurality of second data transmission lines (53) are all connected in parallel between the Ethernet chip (2) and the main control chip (3); and the second resistor (42) is provided on the second clock line (51), the second control line (52) and each of the second data transmission lines (53).

5. The Ethernet circuit board according to claim 4, characterized in that: The first clock line (61), the first control line (62) and the first data transmission line (63) are of equal length.

6. The Ethernet circuit board according to claim 4, wherein: The second clock line (51), the second control line (52) and the second data transmission line (53) are of equal length.

7. The Ethernet circuit board according to claim 5, characterized in that: The first routing layer (11) is provided with a first grounding wire (71), the first grounding wire (71) is provided with a first ground via (713), the first ground via (713) is connected to the grounding shielding layers (13) on both sides of the first routing layer (11), the first grounding wire (71) is surrounded to form a first shielding ring, and the portion of the receiving circuit (6) arranged in the first routing layer (11) is surrounded by the first shielding ring.

8. The Ethernet circuit board according to claim 6, wherein: The second routing layer (12) is provided with a second ground wire (72), the second ground wire (72) is provided with a second ground via (723), the second ground via (723) is connected to the ground shielding layer (13) on both sides of the second routing layer (12), the second ground wire (72) is surrounded to form a second shielding ring, and the part of the transmission line (5) arranged in the second routing layer (12) is surrounded by the second shielding ring.

9. The Ethernet circuit board according to claim 7, wherein: The first grounding line (71) comprises a first loop line (711) and a first separation line (712); the first loop line (711) is arranged to form the first shielding ring; both ends of the first separation line (712) are respectively connected to the first loop line (711) to separate the first shielding ring into a first loop portion and a second loop portion; the portion of the first clock line (61) arranged on the first wiring layer (11) is surrounded by the first loop portion; and the portions of both the first control line (62) and the first data transmission line (63) arranged on the first wiring layer (11) are surrounded by the second loop portion.

10. The Ethernet circuit board according to claim 8, wherein: The second grounding line (72) includes a second loop line (721) and a second separation line (722). The second loop line (721) is arranged to form the second shielding ring. The two ends of the second separation line (722) are respectively connected to the second loop line (721) to separate the second shielding ring into a third loop portion and a fourth loop portion. The portion of the second clock line (51) arranged on the second routing layer (12) is surrounded by the third loop portion, and the portions of the second control line (52) and the second data transmission line (53) arranged on the second routing layer (12) are surrounded by the fourth loop portion.

11. An electronic device, characterized in that: The Ethernet circuit board comprises the Ethernet circuit board according to any one of claims 1 to 10.

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