Chip embedded type printed circuit board

Abstract

The utility model discloses a chip embedded type printed circuit board, which comprises a target circuit board, at least one chip unit, a heat dissipation device and a plastic package layer, and is characterized in that the chip unit is fixedly mounted in a mounting groove of the target circuit board and comprises at least one metal substrate and at least one chip; the chips and the corresponding metal substrates are fixedly arranged, and the chips are connected with the metal substrates; the heat dissipation device is attached to the second side of the target circuit board, and the heat dissipation device comprises an insulating plate and a radiator; wherein the target circuit board is provided with a plurality of connection networks, the connection networks comprise a plurality of first connection networks and a plurality of second connection networks, and the minimum distance between each second connection network and other connection networks is larger than 0.3 mm. Through the above mode, the electric aging insulation failure risk of the chip embedded type printed circuit board can be reduced.

Description

Technical Field

[0001] The utility model is applied to the technical field of printed circuit boards, in particular to chip-embedded printed circuit boards. Background Art

[0002] With the continuous advancement of the global energy structure transformation, electricity has become an increasingly important form of energy; power chips have the characteristics of high conversion efficiency, but the current packaging method has too large parasitic parameters, which affects the switching frequency of power chips.

[0003] Embedding power chips into printed circuit boards has become one of the best solutions to reduce integration parameters.

[0004] However, after the power chip is embedded in the printed circuit board, electrical breakdown or leakage problems are likely to occur. Utility Model Content

[0005] The utility model provides a chip embedded printed circuit board to solve the problem of electrical insulation of the printed circuit board.

[0006] To solve the above technical problems, the present invention provides a chip-embedded printed circuit board, comprising: a target circuit board, at least one chip unit, a heat sink, and a plastic encapsulation layer. At least one mounting groove is formed on a first side of the target circuit board, and the chip unit is fixedly mounted in the corresponding mounting groove. The chip unit comprises at least one metal substrate and at least one chip. The chip is fixedly arranged on the corresponding metal substrate and connected to the metal substrate. The heat sink is bonded to the second side of the target circuit board, and the second side of the target circuit board is opposite to the first side of the target circuit board. The heat sink comprises an insulating plate and a radiator. The insulating plate is fixedly and bonded to the second side of the target circuit board, and the radiator is fixedly and bonded to a side of the insulating plate away from the target circuit board. The plastic encapsulation layer is bonded to the first side of the target circuit board and fills the gap between the target circuit board, the at least one chip unit, and the heat sink for plastic encapsulation. The target circuit board is provided with a plurality of connection networks, and the connection networks include a plurality of first connection networks and a plurality of second connection networks. The minimum spacing between each second connection network and the other connection networks is greater than 0.3 mm.

[0007] Among them, the minimum spacing between different second connection networks is greater than 0.6 mm, the minimum spacing between the second connection network and the first connection network is greater than 0.3 mm, and the minimum length of the side connection path between the metal substrate and the heat sink is greater than 0.3 mm.

[0008] Among them, the chip-embedded printed circuit board also includes: a first connector, a second connector and a third connector; a gate and a transmission electrode are provided on the first side of the chip, and another transmission electrode is provided on the second side of the chip; the first connector is connected to the gate of the chip, and the first connector belongs to a first connection network; the second connector is connected to a transmission electrode on the first side of the chip, and the second connector belongs to a second connection network; the metal substrate is connected to another transmission electrode on the second side of the chip, and the side of the metal substrate away from the heat sink is also connected to the third connector, and the metal substrate and the third connector both belong to another second connection network.

[0009] Among them, at least one groove is formed on the first side of the metal substrate, and the chip is installed in the corresponding groove; the insulating plate includes a first metal layer, an insulating layer and a second metal layer stacked and bonded in sequence, the first metal layer is also bonded to the second side of the metal substrate, and the second metal layer is also bonded to the side of the heat sink close to the metal substrate.

[0010] The second side of the metal substrate is flush with the second side of the target circuit board; the first metal layer is bonded to the second side of the target circuit board and the second side of the metal substrate; and the length of the side connection path between the side of the first metal layer and the heat sink is greater than 0.3 mm.

[0011] The side of the insulating layer away from the metal substrate is flush with the second side of the target circuit board; the second metal layer is bonded to the second side of the target circuit board and the side of the insulating layer away from the metal substrate; and the length of the side connection path between the side of the first metal layer and the second metal layer is greater than 0.3 mm.

[0012] The projected size of the insulating layer on the target circuit board is smaller than the corresponding size of the target circuit board, and the projected size of the insulating layer on the target circuit board is larger than the projected size of the metal substrate on the target circuit board.

[0013] In which, at least one through-groove is formed on the metal substrate, the chip is installed in the corresponding through-groove, and the second side of the metal substrate is flush with the second side of the chip; the insulating plate includes a first metal layer, an insulating layer, a metal block and a second metal layer that are stacked and bonded in sequence, and the side of the metal block away from the metal substrate is flush with the second side of the target circuit board; the first metal layer is bonded to the second side of the metal substrate and the second side of the chip, the side of the second metal layer close to the metal substrate is bonded to the side of the metal block away from the metal substrate and the second side of the target circuit board, and the side of the second metal layer away from the metal substrate is bonded to the radiator.

[0014] Among them, the first metal layer, the insulating layer and the metal block are arranged in the installation groove; the projection sizes of the first metal layer, the insulating layer and the metal block on the target circuit board are all smaller than the projection size of the installation groove on the target circuit board, and the projection sizes of the first metal layer, the insulating layer and the metal block on the target circuit board are all larger than the projection size of the metal substrate on the target circuit board.

[0015] Wherein, the insulating layer of the insulating plate includes a ceramic layer and / or a resin layer; when the insulating layer is a ceramic layer, the thickness of the ceramic layer is greater than 0.05 mm; when the insulating layer is a resin layer, the thickness of the resin layer is greater than 0.3 mm.

[0016] In order to solve the above technical problems, the chip-embedded printed circuit board of the present invention is provided with a chip on a metal substrate to improve the heat dissipation efficiency of the chip through the metal substrate, and the metal substrate is built into the target circuit board, which can improve the stacking degree of the above structure and improve the integration degree of the entire chip-embedded printed circuit board. In addition, the spacing between different connection networks on the target circuit board is greater than 0.3 mm. By clearly standardizing the minimum spacing between different connection networks in the chip-embedded printed circuit board, the electrical insulation characteristics between the connection networks are ensured, and the risk of electrical aging and insulation failure of the chip-embedded printed circuit board is reduced. The second side of the target circuit board is also provided with a heat dissipation device, which can utilize the combination of the metal substrate and the heat dissipation device to improve the heat dissipation efficiency of the chip, protect the working environment of the chip, and increase the working life of the chip. The heat dissipation device includes an insulating plate, which can also insulate and protect the second side of the target circuit board to prevent the second side of the target circuit board from leaking electricity to the radiator or the outside world, further improving the safety and reliability of the chip-embedded printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a structural diagram of a first embodiment of a chip-embedded printed circuit board provided by the present invention;

[0018] Figure 2 It is a schematic diagram of the minimum spacing between each connected network;

[0019] Figure 3 It is a schematic diagram of the local structure between the metal substrate and the radiator;

[0020] Figure 4 This is a structural diagram of a second embodiment of a chip-embedded printed circuit board provided by the present invention;

[0021] Figure 5 It is a structural schematic diagram of the third embodiment of the chip-embedded printed circuit board provided by the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0023] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0024] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0025] Please read together Figure 1-2 , Figure 1 It is a structural schematic diagram of the first embodiment of the chip-embedded printed circuit board provided by the present invention. Figure 2 This is a schematic diagram of the minimum spacing between each connected network.

[0026] The embedded chip printed circuit board 100 of this embodiment includes a target circuit board 110, at least one chip unit 190, a plastic layer 140, and a heat sink 180. The chip unit 190 includes at least one metal substrate 120 and at least one chip 130. The chip 130 is fixedly mounted on and connected to the corresponding metal substrate 120.

[0027] The target circuit board 110 is a pre-prepared PCB (Printed Circuit Board) that serves as the foundation for embedding the chip 130. The circuitry of the target circuit board 110 is patterned. The target circuit board 110 can be a multilayer board with only through-hole interconnects or an HDI (High Density Interconnector) board with blind via interconnects. The specific structure of the target circuit board 110 is determined based on actual needs.

[0028] At least one mounting groove 113 is formed on the first side 111 of the target circuit board 110, and the chip unit 190 is fixedly installed in the corresponding mounting groove 113. One or more chip units 190 can be installed on a target circuit board 110. The first side 111 of the target circuit board 110 is in the same direction as the first side of the metal substrate 120 and the first side of the chip 130.

[0029] Chip 130 may include a power chip, such as an IGBT (Insulated-Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or other devices, such as diodes, electron tubes, electromechanical components, etc., which are not specifically limited here.

[0030] The material of the metal substrate 120 can be copper, molybdenum copper, tungsten copper, etc., to conduct heat and electricity to the chip 130. Its thermal expansion coefficient (CTE) is 5 to 20 ppm / °C. This thermal expansion coefficient range matches the expansion coefficient of the chip 130, thereby maintaining structural stability between the thermal expansion of the chip 130 and the metal substrate 120, reducing the stress caused by the thermal expansion difference, and improving the connection stability between the chip 130 and the metal substrate 120.

[0031] Molding layer 140 is laminated to the first side of target circuit board 110 and fills the gaps between target circuit board 110, at least one chip unit 190, and heat sink 180 to provide insulation and secure components. Molding layer 140 includes, but is not limited to, one or more insulating materials such as epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), Ajinomoto build film (ABF), FR4 resin, and ceramic-based materials.

[0032] The heat sink 180 is attached to the second side 112 of the target circuit board 110 , which is opposite to the first side 111 . The second side of the metal substrate 120 is co-located with the second side 112 of the target circuit board 110 and the second side of the chip 130 .

[0033] In some embodiments, the heat dissipation device 180 includes an insulating plate 160 and a heat sink 170 ; the insulating plate 160 is fixed and fitted to the second side 112 of the target circuit board 110 , and the heat sink 170 is fixed and fitted to the side of the insulating plate 160 away from the second side 112 .

[0034] The heat dissipation device 180 of this embodiment can be obtained by welding the insulating plate 160 on the heat sink 170, and the welding can include tin reflow soldering, silver sintering, etc. The heat sink 170 includes a metal heat sink, an air-cooled heat sink, or a liquid-cooled heat sink.

[0035] In a specific application scenario, the heat sink 170 may include a protruding heat dissipation structure 172 and a main plate 171. The main plate 171 is fixed and fitted to the side of the insulating plate 160 away from the second side 112. The protruding heat dissipation structure 172 is fixed to the side of the main plate away from the insulating plate 160. The shape of the protruding heat dissipation structure 172 may include, but is not limited to, one or more of a columnar, corrugated, string, fin, etc. The material of the heat sink 170 may include, but is not limited to, copper, aluminum, stainless steel, etc. The heat sink 170 may be a metal heat sink, an air-cooled heat sink, a liquid-cooled heat sink, etc., and the specifics are not limited here.

[0036] By fixing and fitting the insulating plate 160 to the second side 112 of the target circuit board 110, the insulating plate 160 can be used to insulate and protect the second side 112 of the target circuit board 110, preventing the second side 112 of the target circuit board 110 from leaking electricity to the radiator 170 or the outside world.

[0037] See also Figure 2 , Figure 2 The spacing is provided for illustrative purposes only and does not limit the location of the connection network 1003. The target circuit board 110 is provided with multiple connection networks 1003. The connection networks 1003 include multiple first connection networks 1001 and multiple second connection networks 1002. The spacing between each second connection network 1002 and the other connection networks 1003 is greater than 0.3 mm. Specific spacings may include, but are not limited to, 0.3 mm, 0.4 mm, 0.5 mm, 0.8 mm, 1.0 mm, 2.0 mm, or 3.0 mm. The different connection networks 1003 are also filled with a plastic encapsulation layer 140 for insulation and isolation.

[0038] The first connection network 1001 is a low-voltage network in the chip-embedded printed circuit board 100, i.e., a network with a voltage of generally less than 48V. The second connection network 1002 is a high-voltage network in the chip-embedded printed circuit board 100, i.e., a network with a voltage of up to 400V or even 1200V.

[0039] This application clearly specifies the minimum spacing between the second connection network 1002 and other connection networks 1003 in the chip-embedded printed circuit board 100, thereby ensuring the electrical insulation characteristics between the second connection networks 1002 and reducing the risk of electrical aging and insulation failure of the chip-embedded printed circuit board 100.

[0040] Through the above structure, the chip-embedded printed circuit board of this embodiment is configured to improve the heat dissipation efficiency of the chip by placing the chip on a metal substrate, and the metal substrate is built into the target circuit board, which can improve the stacking degree of the above structure and improve the integration of the entire chip-embedded printed circuit board. In addition, the spacing between different connection networks on the target circuit board is greater than 0.3 mm. By clearly standardizing the minimum spacing between different connection networks in the chip-embedded printed circuit board, the electrical insulation characteristics between the connection networks are ensured, reducing the risk of electrical aging and insulation failure of the chip-embedded printed circuit board. The second side of the target circuit board is also provided with a heat dissipation device, which can utilize the combination of the metal substrate and the heat dissipation device to improve the heat dissipation efficiency of the chip, protect the working environment of the chip, and increase the working life of the chip. The heat dissipation device includes an insulating plate, which can also insulate and protect the second side of the target circuit board to prevent the second side of the target circuit board from leaking electricity to the radiator or the outside world, further improving the safety and reliability of the chip-embedded printed circuit board.

[0041] In some embodiments, the minimum spacing H between different second connection networks 1002 is greater than 0.6 mm, and may include but is not limited to 0.6 mm, 0.8 mm, 0.9 mm, 1.0 mm, 2.0 mm, 2.5 mm, 2.8 mm, 3.0 mm, 3.4 mm, 3.6 mm or 4.0 mm, etc.

[0042] The minimum spacing N between the first connection network 1001 and the second connection network 1002 is greater than 0.3 mm, including but not limited to 0.3 mm, 0.35 mm, 0.4 mm, 0.5 mm, 0.8 mm, 1.0 mm, 2.0 mm, 2.4 mm, or 3.0 mm. The minimum length of the side connection path between the metal substrate 120 and the heat sink 170 is greater than 0.3 mm, including but not limited to 0.3 mm, 0.4 mm, 0.5 mm, 0.8 mm, 1.0 mm, 2.0 mm, or 3.0 mm.

[0043] By limiting the minimum spacing between first connection network 1001 and second connection network 1002, the electrical insulation between first connection network 1001 and second connection network 1002 is improved. Since second connection network 1002 is a high-voltage network, the spacing between different second connection networks 1002 is required to be higher to improve the electrical insulation between second connection networks 1002.

[0044] See also Figure 3 , Figure 3 It is a schematic diagram of the local structure between the metal substrate and the heat sink.

[0045] The lateral connection path S between the metal substrate 120 and the heat sink 170 is composed of the sum of the spacing P between the edge of the connection network where the metal substrate 120 is located and the edge of the insulating plate 160, and the thickness X of the insulating plate 160. In other words, S = P + X; this means that the minimum length of the path through which current may break down must be greater than 0.3 mm to prevent electrical breakdown and improve the external insulation of the metal substrate 120.

[0046] When there is no other conductive layer at the bottom of the metal substrate 120, the edge of the connection network where the metal substrate 120 is located is the edge of the metal substrate 120. When there is other conductive layer at the bottom of the metal substrate 120, the edge of the connection network where the metal substrate 120 is located is the edge of the conductive layer.

[0047] In some embodiments, please refer to Figure 1 The embedded chip printed circuit board 100 further includes a first connector 151, a second connector 152, and a third connector 153. These connectors are used to lead signals from the chip 130 and include, but are not limited to, various metals and metal structures. A gate and a transmission electrode are provided on the first side of the chip 130, and another transmission electrode is provided on the second side of the chip 130.

[0048] The first connection member 151 is connected to the gate of the chip 130 , and the first connection member 151 belongs to the first connection network 1001 .

[0049] The second connecting member 152 is connected to a transmission electrode on the first side of the chip 130 and belongs to a second connection network 1002. That is, the distance between the first connecting member 151 and the second connecting member 152 is greater than 0.3 mm.

[0050] The metal substrate 120 is connected to another transmission electrode on the second side of the chip 130. The side of the metal substrate 120 away from the heat sink 170 is also connected to the third connector 153. The metal substrate 120 and the third connector 153 belong to another second connection network 1002. The spacing between the second connector 152 and the metal substrate 120 and the third connector 153 is greater than 0.6 mm.

[0051] The first connector 151, the second connector 152, and the third connector 153 are disposed within the plastic layer 140, and the ends of the first connector 151, the second connector 152, and the third connector 153 away from the chip 130 are exposed outside the plastic layer 140 to lead out signals from the chip 130. The conductive traces in the target circuit board 110 belong to the first connection network 1001.

[0052] The chip 130 includes a power chip such as an insulated gate bipolar transistor (IGBT chip) or a metal-oxide semiconductor field effect transistor (MOS chip).

[0053] Wherein, the transmission electrode (not shown) includes a current input stage and a current output stage. When the chip 130 is an insulated gate bipolar transistor, the transmission electrode can be an emitter or a collector; when the chip 130 is a metal-oxide semiconductor field effect transistor, the transmission electrode can be a source or a drain. Wherein, the specific types of a transmission electrode connected to the second connector 152 and another transmission electrode connected to the metal substrate 120 can be arbitrarily set or exchanged based on the chip type and actual needs, and are not specifically limited here. For example: when the chip 130 is a metal-oxide semiconductor field effect transistor, the electrode connected to the second connector 152 can be a source and the electrode connected to the metal substrate 120 can be a drain; or the electrode connected to the second connector 152 can be a drain and the electrode connected to the metal substrate 120 can be a source.

[0054] In some embodiments, at least one groove 121 is formed on the first side of the metal substrate 120, and the chip 130 is mounted in the corresponding groove 121. Specifically, the transmission electrode on the second side of the chip 130 is fixed to the bottom of the groove 121 by welding.

[0055] The insulating plate 160 includes a first metal layer 161, an insulating layer 163 and a second metal layer 162 which are stacked and bonded in sequence. The first metal layer 161 is also bonded to the second side of the metal substrate 120, and the second metal layer 162 is also bonded to the side of the heat sink 170 close to the metal substrate 120.

[0056] The first metal layer 161 is used to achieve welding fixation between the metal substrate 120 and the insulating layer 163, and the second metal layer 162 is used to achieve welding fixation between the insulating layer 163 and the heat sink 170. The insulating layer 163 and the heat sink 170 are fixed in position by the stacked insulating plates 160.

[0057] The first metal layer 161 and the second metal layer 162 may be attached and fixed by direct bonding or welding.

[0058] The thickness of the first metal layer 161 and the second metal layer 162 both range from 0.01 mm to 1.00 mm, and specifically may be 0.05 mm, 0.11 mm, 0.17 mm, 0.25 mm, 0.3 mm, 0.45 mm, 0.52 mm, 0.63 mm, 0.75 mm, 0.8 mm, 0.95 mm, or 1.00 mm. The first metal layer 161 and the second metal layer 162 may have the same or different thicknesses, and may be made of one or more of copper, aluminum, silver, titanium, tin, molybdenum, and tungsten.

[0059] The projected size of the insulating layer 163 on the target circuit board 110 is much larger than the projected size of the metal substrate 120 on the target circuit board 110 , but not larger than the size of the target circuit board 110 .

[0060] The insulating plate 160 of this embodiment can be prepared in advance and then welded and fixed to the target circuit board 110 to independently achieve high-temperature welding between the first metal layer 161 and the second metal layer 162 and the insulating layer 163, and avoid the high temperature affecting the reliability of the target circuit board 110.

[0061] In some embodiments, the second side of the metal substrate 120 is flush with the second side 112 of the target circuit board 110 .

[0062] The first metal layer 161 is laminated to the second side 112 of the target circuit board 110 and the second side of the metal substrate 120 .

[0063] The length of the side connection path between the side of the first metal layer 161 and the heat sink 170 is greater than 0.3 mm. Since the first metal layer 161 is connected to the metal substrate 120, the first metal layer 161 also belongs to the high-voltage network. Therefore, the length of the side connection path between the side of the first metal layer 161 and the heat sink 170 is limited to greater than 0.3 mm. In other words, the sum of the distance from the side edge of the first metal layer 161 to the side edge of the insulating layer 163 plus the thickness of the insulating layer 163 is at least greater than 0.3 mm. Specifically, this distance limitation can be achieved by shrinking the first metal layer 161. The shrinking area of ​​the first metal layer 161 is filled with the plastic packaging material on the target circuit board 210.

[0064] The structure of the above-mentioned chip-embedded printed circuit board 100 can utilize the first metal layer 161 to achieve fixation between the metal substrate and the insulating layer 163, and utilize the second metal layer 162 to achieve fixation between the insulating layer 163 and the heat sink 170. The setting of the metal substrate 120 can also be utilized to improve the heat dissipation efficiency of the chip-embedded printed circuit board 100.

[0065] In some embodiments, the insulating layer 163 of the insulating plate 160 includes a ceramic layer and / or a resin layer.

[0066] When the insulating layer 163 is a ceramic layer, the thickness of the ceramic layer is greater than 0.05 mm, and specifically can be 0.05 mm, 0.10 mm, 0.16 mm, 0.25 mm, 0.32 mm, 0.45 mm, 0.52 mm, 0.68 mm, 0.71 mm, 0.8 mm, 0.95 mm, or 1.00 mm. Insulating layer 163 within this range can provide insulation protection for the bottom of target circuit board 110.

[0067] The insulating layer 163 can be one or more of aluminum oxide, silicon nitride, aluminum nitride, beryllium oxide, diamond, etc.; the above-mentioned ceramic materials can not only achieve insulation protection, but also ensure the thermal conductivity of the insulating layer 163, so that it can reach 80W / mK or even 1200W / mK, far exceeding materials such as silicone grease and resin, thereby achieving a significant improvement in heat dissipation efficiency.

[0068] In some embodiments, when the insulating layer 163 is a ceramic layer, the first metal layer 161 is welded together with the second side of the metal substrate 120 through a welding layer (not shown); the welding layer may include a solder layer close to the first metal layer 161 and a welding auxiliary metal layer covering the surface of the second side of the metal substrate 120 and the second side 112 of the target circuit board 110.

[0069] When the insulating layer 163 is a resin layer, the thickness of the resin layer is greater than 0.3 mm, and may specifically include but is not limited to 0.3 mm, 0.5 mm, 0.6 mm, 0.8 mm, 1.0 mm, or 1.5 mm.

[0070] The resin layer includes but is not limited to one or more insulating materials such as prepreg, epoxy resin, polyester resin (PET), polyimide, polyimide, polycarbonate (PC), bismaleimide triazine (BT), Ajinomoto build film (ABF), FR4 resin, ceramic base, etc.

[0071] In some implementation cases, when the insulating layer 163 is a resin layer, the first metal layer 161 may not be required, and the insulating layer 163 is directly bonded to the second side of the metal substrate 120 through resin bonding.

[0072] See also Figure 4 , Figure 4 This is a schematic structural diagram of the second embodiment of the chip embedded printed circuit board provided by the present invention. The target circuit board, chip unit, heat sink, metal substrate, connector and plastic packaging layer of this embodiment are the same as those of the previous embodiment and will not be described in detail.

[0073] In some embodiments, a side of the insulating layer 263 away from the metal substrate 220 is flush with the second side 212 of the target circuit board 210 .

[0074] The second metal layer 262 is laminated to the second side 212 of the target circuit board 210 and the side of the insulating layer 263 away from the metal substrate 220 .

[0075] The length of the side connection path between the side surface of the first metal layer 261 and the second metal layer 262 is greater than 0.3 mm.

[0076] Since the first metal layer 261 is connected to the metal substrate 220, the first metal layer 261 also belongs to the high-voltage network. Therefore, the length of the side connection path between the side of the first metal layer 261 and the second metal layer 262 is limited to be greater than 0.3 mm, that is, the sum of the distance from the side edge of the first metal layer 261 to the side edge of the insulating layer 263 plus the thickness of the insulating layer 263 is greater than 0.3 mm. Specifically, the above-mentioned distance limitation can be achieved by shrinking the first metal layer 261 or thickening the insulating layer 263.

[0077] In some embodiments, the insulating layer 263 and the second metal layer 262 are welded together via a welding layer (not shown); the welding layer includes a welding auxiliary metal layer close to the insulating layer 263 and a solder layer close to the second metal layer 262 .

[0078] In some embodiments, the projected size of the insulating layer 263 on the target circuit board 210 is smaller than the projected size of the mounting groove 213 on the target circuit board 210, and the projected size of the insulating layer 263 on the target circuit board 210 is larger than the projected size of the metal substrate 220 on the target circuit board 210; that is, the overlapping portion of the metal substrate 220 and the heat sink 270 must be isolated and insulated by the insulating layer 263 to improve the insulation effect of the metal substrate 220.

[0079] The projection size of the first metal layer 261 on the target circuit board 210 is not smaller than the projection size of the metal substrate 220 on the target circuit board 210 .

[0080] The structure of the above-mentioned chip-embedded printed circuit board directly sets the insulating layer 263 in the mounting groove 213, providing another insulating structure on the second side of the metal substrate 220. The above-mentioned setting can also utilize the first metal layer 261 to achieve fixation between the metal substrate and the insulating layer 263, and utilize the second metal layer 262 to achieve fixation between the insulating layer 263 and the heat sink 270, and can utilize the setting of the metal substrate 220 to improve the heat dissipation efficiency of the chip-embedded printed circuit board.

[0081] See also Figure 5 , Figure 5This is a schematic structural diagram of the third embodiment of the chip embedded printed circuit board provided by the present invention. The target circuit board, chip unit, heat sink, connector and plastic packaging layer of this embodiment are the same as those of the previous embodiment and will not be described in detail.

[0082] The metal substrate 320 is formed with at least one through-groove 321, and the chip 330 is mounted in the corresponding through-groove 321. The second side of the metal substrate 320 and the second side of the chip 330 are flush.

[0083] The insulating plate 360 ​​includes a first metal layer 361 , an insulating layer 363 , a metal block 364 and a second metal layer 362 stacked and bonded together. The side of the metal block 364 away from the metal substrate 320 is flush with the second side 312 of the target circuit board 310 .

[0084] The first metal layer 361 is bonded to the second side of the metal substrate 320 and the second side of the chip 330, the side of the second metal layer 362 close to the metal substrate 320 is bonded to the side of the metal block 364 away from the metal substrate 320 and the second side 312 of the target circuit board 310, and the side of the second metal layer 362 away from the metal substrate 320 is bonded to the heat sink 370.

[0085] In this embodiment, there is no metal substrate 320 between the chip 330 and the heat sink 370, and they are directly separated by the insulating layer 363. The steps in the manufacturing process of the chip 330 embedded in the printed circuit board of this embodiment are relatively simple.

[0086] In some embodiments, the first metal layer 361 , the insulating layer 363 , and the metal block 364 are disposed in the mounting groove 313 .

[0087] The projected dimensions of the first metal layer 361, the insulating layer 363, and the metal block 364 on the target circuit board 310 are all smaller than the projected dimensions of the mounting slot 313 on the target circuit board 310. Furthermore, the projected dimensions of the first metal layer 361, the insulating layer 363, and the metal block 364 on the target circuit board 310 are all larger than the projected dimensions of the metal substrate 320 on the target circuit board 310. In other words, the overlapping portion of the metal substrate 320 and the heat sink 370 must be isolated and insulated by the insulating layer 363 to improve the insulation performance of the metal substrate 320.

[0088] The structure of the above-mentioned chip-embedded printed circuit board directly sets the first metal layer 361, the insulating layer 363 and the metal block 364 in the mounting groove 313, providing another insulating structure on the second side of the metal substrate 320. The above-mentioned setting can also use the first metal layer 361 to achieve fixation between the metal substrate and the insulating layer 363, and use the second metal layer 362 to achieve fixation between the insulating layer 363 and the heat sink 370, and can also use the setting of the metal substrate 320 to improve the heat dissipation efficiency of the chip-embedded printed circuit board.

[0089] Through the above structure, the chip-embedded printed circuit board of this embodiment improves the chip's heat dissipation efficiency by placing the chip on a metal substrate. The metal substrate is embedded in the target circuit board, which can improve the stacking degree of the above structure and enhance the integration of the entire chip-embedded printed circuit board. The minimum spacing between different second connection networks on the target circuit board is greater than 0.6 mm, the minimum spacing between the second connection network and the first connection network is greater than 0.3 mm, and the minimum length of the lateral connection path between the metal substrate and the heat sink is greater than 0.3 mm. By clearly standardizing the minimum spacing between different connection networks in the chip-embedded printed circuit board, the electrical insulation characteristics between the connection networks are ensured, reducing the risk of electrical aging and insulation failure of the chip-embedded printed circuit board. The second side of the target circuit board is also provided with a heat dissipation device. The metal substrate and the heat dissipation device can be combined to improve the heat dissipation efficiency of the chip, protect the working environment of the chip, and extend the service life of the chip. The heat dissipation device includes an insulating plate and can also insulate and protect the second side of the target circuit board, preventing the second side of the target circuit board from leaking to the heat sink or the outside world, further improving the safety and reliability of the chip-embedded printed circuit board.

[0090] The above is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip embedded printed circuit board, characterized in that: The chip embedded printed circuit board comprises: a target circuit board having at least one mounting groove formed on a first side of the target circuit board; At least one chip unit, the chip unit being fixedly mounted in the corresponding mounting slot, the chip unit comprising at least one metal substrate and at least one chip; the chip being fixedly mounted on and connected to the corresponding metal substrate; a heat dissipation device; the heat dissipation device is disposed in contact with a second side of the target circuit board, the second side of the target circuit board being opposite to the first side of the target circuit board; the heat dissipation device includes an insulating plate and a heat sink; the insulating plate is fixed and in contact with the second side of the target circuit board, and the heat sink is fixed and in contact with a side of the insulating plate away from the target circuit board; a plastic sealing layer, the plastic sealing layer being arranged in contact with the first side of the target circuit board and filling gaps between the target circuit board, the at least one chip unit, and the heat sink to perform plastic sealing; The target circuit board is provided with a plurality of connection networks, including a plurality of first connection networks and a plurality of second connection networks, and a minimum spacing between each second connection network and other connection networks is greater than 0.3 mm.

2. The chip embedded printed circuit board according to claim 1, characterized in that: The minimum spacing between different second connection networks is greater than 0.6 mm, the minimum spacing between the second connection network and the first connection network is greater than 0.3 mm, and the minimum length of the side connection path between the metal substrate and the heat sink is greater than 0.3 mm.

3. The chip embedded printed circuit board according to claim 2, characterized in that: The chip embedded printed circuit board further includes: a first connector, a second connector, and a third connector; a gate and a transmission electrode are provided on the first side of the chip, and another transmission electrode is provided on the second side of the chip; The first connecting member is connected to the gate of the chip, and the first connecting member belongs to a first connection network; The second connecting member is connected to a transmission electrode on the first side of the chip, and the second connecting member belongs to a second connection network; The metal substrate is connected to another transmission electrode on the second side of the chip. The side of the metal substrate away from the heat sink is also connected to a third connector. The metal substrate and the third connector both belong to another second connection network.

4. The chip embedded printed circuit board according to any one of claims 1 to 3, characterized in that: At least one groove is formed on the first side of the metal substrate, and the chip is mounted in the corresponding groove; The insulating plate includes a first metal layer, an insulating layer and a second metal layer stacked and bonded in sequence. The first metal layer is also bonded to the second side of the metal substrate, and the second metal layer is also bonded to the side of the radiator close to the metal substrate.

5. The chip embedded printed circuit board according to claim 4, characterized in that: The second side of the metal substrate is flush with the second side of the target circuit board; The first metal layer is laminated to the second side of the target circuit board and the second side of the metal substrate; Wherein, the length of the side connection path between the side surface of the first metal layer and the heat sink is greater than 0.3 mm.

6. The chip embedded printed circuit board according to claim 4, characterized in that: The side of the insulating layer away from the metal substrate is flush with the second side of the target circuit board; The second metal layer is laminated to the second side of the target circuit board and the side of the insulating layer away from the metal substrate; Wherein, the length of the side connection path between the side surface of the first metal layer and the second metal layer is greater than 0.3 mm.

7. The chip embedded printed circuit board according to claim 6, characterized in that: The projected size of the insulating layer on the target circuit board is smaller than the corresponding size of the target circuit board, and the projected size of the insulating layer on the target circuit board is larger than the projected size of the metal substrate on the target circuit board.

8. The chip embedded printed circuit board according to any one of claims 1 to 3, characterized in that: At least one through-groove is formed on the metal substrate, the chip is mounted in the corresponding through-groove, and the second side of the metal substrate is flush with the second side of the chip; The insulating plate comprises a first metal layer, an insulating layer, a metal block and a second metal layer stacked and bonded in sequence, wherein a side of the metal block away from the metal substrate is flush with the second side of the target circuit board; The first metal layer is bonded to the second side of the metal substrate and the second side of the chip, the side of the second metal layer close to the metal substrate is bonded to the side of the metal block away from the metal substrate and the second side of the target circuit board, and the side of the second metal layer away from the metal substrate is bonded to the radiator.

9. The chip embedded printed circuit board according to claim 8, characterized in that: The first metal layer, the insulating layer and the metal block are arranged in the mounting groove; The projection sizes of the first metal layer, the insulating layer and the metal block on the target circuit board are all smaller than the projection size of the mounting groove on the target circuit board, and the projection sizes of the first metal layer, the insulating layer and the metal block on the target circuit board are all larger than the projection size of the metal substrate on the target circuit board.

10. The chip embedded printed circuit board according to claim 1, characterized in that: The insulating layer of the insulating plate comprises a ceramic layer and / or a resin layer; When the insulating layer is a ceramic layer, the thickness of the ceramic layer is greater than 0.05 mm; When the insulating layer is a resin layer, the thickness of the resin layer is greater than 0.3 mm.

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