H-type source follower transistor and image sensor
By designing an H-type source follower transistor and optimizing the current channel distribution, the problems of random noise and random telegraph signal noise in existing image sensors are solved, and the image quality in low-light conditions is improved.
Patent Information
- Application Number
- CN202422805980.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-09-19
- Estimated Expiration
- 2034-11-15
AI Technical Summary
In existing image sensors, random noise RN and random telegraph signal noise RTS are serious problems, especially in low light conditions, affecting image clarity.
An H-type source follower transistor is designed. By forming openings at opposite ends of the gate region, the current channel distribution is optimized, so that the current is reduced in the edge area of the shallow trench isolation region, thereby reducing noise.
The random noise RN and random telegraph signal noise RTS are effectively reduced, improving the imaging quality of the image sensor in low light conditions while maintaining the overall performance of the pixel.
Smart Images
Figure CN223364473U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of image sensors, in particular to an H-type source follower transistor and an image sensor. Background Art
[0002] Semiconductor image sensors are widely used in modern technology, such as smartphone cameras, surveillance equipment, and medical imaging systems. However, noise remains a key factor limiting image quality, especially in low-light conditions. Random noise (RN) and random telegraph signal (RTS) noise are the most common types of noise in image sensors. RTS noise often appears as random white flickering dots in the image, severely affecting image clarity in low light conditions. The source of RTS noise is closely related to the source follower (SF) transistor in the pixel. The primary source of RTS noise is the electron capture and release process in the SF channel. In existing image sensors, many SFs with shallow trench isolation (STI) regions inevitably have on-current flowing at the STI boundary, where there is a high trap density. This is because the STI edge region has a higher electric field strength and more traps. At the junction of the SF channel and the shallow trench isolation (STI) region, electrons are more easily captured and released, thereby generating random noise RN and random telegraph signal noise RTS. Summary of the Invention
[0003] The utility model provides an H-type source follower transistor and an image sensor, which can reduce the flow of current in the edge area of the STI, thereby effectively reducing random noise and random telegraph signal noise.
[0004] In a first aspect, an H-type source follower transistor is provided, comprising a substrate, an isolation region, a source region, a gate region, and a drain region; wherein,
[0005] The gate region is substantially H-shaped, with openings formed at opposite ends of the H-shaped gate region;
[0006] The source region and the drain region are respectively provided at openings at opposite ends of the gate region, and both sides of the openings at opposite ends of the gate region are overlapping regions between the gate region and the active regions of the source region and the active regions of the drain region;
[0007] The isolation region is used to isolate the source region, the gate region, and the drain region, and the isolation region includes a shallow trench isolation structure.
[0008] Optionally, opposite ends of the H-shaped gate region are concave to form openings, and transition surfaces between the concave end surfaces of the two concave ends and the end surface of the overlapping region are perpendicular to the concave end surfaces or the end surface of the overlapping region.
[0009] Optionally, the opposite ends of the H-shaped gate region are concave to form an opening, and a transition surface between the concave end surfaces of the two ends and the end surface of the overlapping region forms an angle that is not 90 degrees with the concave end surface or the end surface of the overlapping region.
[0010] Optionally, the gate region is located in the first layer farthest from the substrate, the source region and the drain region are located in the second layer adjacent to the first layer, the middle of the substrate is raised toward the second layer to isolate the source region from the drain region, and the isolation region is located in the second layer.
[0011] Optionally, the source region, gate region and drain region are arranged on the first side of the substrate, and the isolation region is located in the second layer and covers the first side surface of the substrate to isolate the source region, gate region and drain region.
[0012] Optionally, the first layer further includes an interlayer structure, and the interlayer structure is arranged to surround the gate region.
[0013] Optionally, the interlayer structure is a silicon nitride spacer layer or an insulating oxide layer.
[0014] Optionally, the widths of the source region and the drain region are both greater than the width of the opening.
[0015] Optionally, two opposite ends of the H-shaped gate region are concave to form the opening, and the distance between the end surfaces of the two concave ends is the minimum distance between the source region and the drain region.
[0016] In a second aspect, an image sensor is provided, comprising a photodiode and the H-type source follower transistor as described in the first aspect.
[0017] The above-mentioned H-type source follower transistor includes a substrate, an isolation region, a source region, a gate region and a drain region; the gate region is roughly H-shaped, and openings are formed at the opposite ends of the H-type gate region; the source region and the drain region are respectively arranged at the openings at the opposite ends of the gate region, and the two sides of the openings at the opposite ends of the gate region are respectively the overlapping regions between the gate region and the active regions of the source region and the active regions of the drain region; the isolation region is used to isolate the source region, the gate region and the drain region, and the isolation region includes a shallow trench isolation structure. By adopting an H-type gate region, the current channel in the H-type source follower transistor is optimized, and the current is no longer uniformly distributed in the current channel, but will be reduced in the edge area of the shallow trench isolation area, so that the current can stay away from the edge area of the shallow trench isolation structure when passing through the channel. By reducing the current flowing in the edge area of the shallow trench isolation area, the random noise RN and the random telegraph signal noise RTS can be effectively reduced; for image sensors adopting the above-mentioned structure, it is possible to improve imaging quality under low light conditions while maintaining pixel performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0019] Figure 1 It is a three-dimensional schematic diagram of an existing source follower transistor;
[0020] Figure 2 is a schematic top view of an existing source follower transistor;
[0021] Figure 3 This is a schematic diagram demonstrating the current flow of an existing source follower transistor;
[0022] Figure 4 This is a schematic diagram illustrating the current channel of an existing source follower transistor;
[0023] Figure 5 It is a three-dimensional schematic diagram of an H-type source follower transistor of the present utility model;
[0024] Figure 6 It is a cross-sectional view of an H-type source follower transistor of the present utility model;
[0025] Figure 7 This is a schematic diagram demonstrating the current flow of an H-type source follower transistor of the present invention;
[0026] Figure 8 This is a schematic diagram demonstrating the current channel of an H-type source follower transistor of the present invention.
[0027] Figure 9 It is a three-dimensional schematic diagram of another H-type source follower transistor of the present invention;
[0028] Figure 10 It is a schematic top view of another H-type source follower transistor of the present invention. DETAILED DESCRIPTION
[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0030] like Figures 1-4 As shown in FIG. 1 , a conventional source follower transistor is shown. The source follower transistor includes a substrate 105, an isolation region 104, a source region 103, a gate region 102, and a drain region 101. For example, the substrate 105 is a p-type doped silicon wafer, each of the drain region 101 and the source region 103 is a corresponding n-type doped region of the substrate 105, and the gate region 102 is a polysilicon structure deposited on the substrate 105. Applying a gate voltage to the gate region 102 can cause a current channel to form, and current flows between the drain region 101 and the source region 103 in the direction of the arrow. The gate region 102 is a traditional planar design, such as Figure 3-Figure 4 As shown, Figure 3 The direction of the arrow in the figure is the direction of the current in the current channel. Figure 4 In the current channel 106 , current flows uniformly. In the source follower transistor, current flows uniformly through the entire width of the SF current channel 106 . Especially in the STI edge region, the current density is relatively high, resulting in increased noise.
[0031] Therefore, the present application provides an H-type source follower transistor, in which the current is no longer evenly distributed in the current channel, but is reduced in the edge area of the shallow trench isolation area. By reducing the current flow in the edge area of the shallow trench isolation area, the random noise RN and random telegraph signal noise RTS can be effectively reduced.
[0032] Example 1
[0033] See also Figure 5-Figure 8, an H-type source follower transistor and image sensor provided by an embodiment of the present invention can reduce the flow of current in the STI edge area, thereby effectively reducing random noise RN and random telegraph signal noise RTS.
[0034] The present application provides an H-type source follower transistor 01, comprising a substrate 50, an isolation region 40, a source region 30, a gate region 10 and a drain region 20; wherein,
[0035] The gate region 10 is substantially H-shaped, with openings formed at opposite ends of the H-shaped gate region 10;
[0036] The source region 30 and the drain region 20 are respectively provided at the openings at opposite ends of the gate region 10 , and both sides of the openings at opposite ends of the gate region are overlapping regions between the gate region 10 and the active regions of the source region 30 and the active regions of the drain region 20 ;
[0037] The isolation region 40 is used to isolate the source region 30 , the gate region 10 , and the drain region 20 . The isolation region 40 includes a shallow trench isolation structure.
[0038] Among them, applying a gate voltage to the gate region 10 can cause a current channel to be formed, and the current flows between the drain region 20 and the source region 30 in the direction of the arrow. By adopting an H-type gate region, the current channel in the H-type source follower transistor is optimized, as shown in FIG. Figure 6 As shown, Figure 6 for Figure 5 In the cross-sectional view corresponding to the C2 cross-sectional view, the width of the overlapping area between the gate region and the active area of the source region can be represented by a dimension, and the width of the overlapping area between the gate region and the active area of the drain region can also be represented by the dimension. In this overlapping area, the current flow direction is no longer always parallel to the channel direction, and the current is no longer uniformly distributed in the current channel, but will be reduced in the edge area of the shallow trench isolation area, so that the current can stay away from the edge area of the shallow trench isolation structure when passing through the channel. By reducing the current flow in the edge area of the shallow trench isolation area, the random noise RN and the random telegraph signal noise RTS can be effectively reduced.
[0039] like Figure 5-Figure 6 As shown, the opposite ends of the H-shaped gate region are concave to form openings, and the transition surface between the concave end surfaces of the two ends and the end surface of the overlapping region is perpendicular to the concave end surface or the end surface of the overlapping region.
[0040] like Figure 5-Figure 6As shown, the gate region is located in the first layer farthest from the substrate, the source region and the drain region are located in the second layer adjacent to the first layer, the middle of the substrate is raised toward the second layer to isolate the source region from the drain region, and the isolation region is located in the second layer.
[0041] like Figure 5-Figure 6 As shown, the source region 30, the gate region 10 and the drain region 20 are arranged on the first side of the substrate 50, and the isolation region 40 is arranged on the first side of the substrate 50; the isolation region 40 is located in the second layer and covers the first side surface of the substrate to isolate the source region 30, the gate region 10 and the drain region 20.
[0042] like Figure 5-Figure 6 As shown, the first layer further includes an interlayer structure 70 , which surrounds the gate region and is a silicon nitride spacer layer or an insulating oxide layer, to isolate the source region 30 , the gate region 10 , and the drain region 20 .
[0043] like Figure 5 As shown, the two opposite ends of the H-shaped gate region are concave to form the opening, and the distance between the end surfaces of the two concave ends is the minimum distance between the source region and the drain region.
[0044] By recessing the opposite ends of the gate region to form the opening, the current is no longer evenly distributed in the current channel, but is reduced at the edge of the shallow trench isolation region.
[0045] like Figure 5-Figure 6 As shown, the widths of the source region 30 and the drain region 20 are both greater than the width of the opening, so that overlapping regions exist between the gate region 10 and the source region 30 , and between the gate region 10 and the drain region 20 .
[0046] like Figure 6 As shown, Figure 6 for Figure 5 In the cross-sectional view corresponding to the C2 cross-sectional view, the width of the overlapping area between the gate region and the active area of the source region can be represented by a dimension, and the width of the overlapping area between the gate region and the active area of the drain region can also be represented by the dimension. In this overlapping area, the current flow direction is no longer always parallel to the channel direction. At the same time, the closer to the edge of the isolation region, the lower the density of the current path. Near the overlapping area, the current distribution will be reduced in the edge area of the shallow trench isolation area, thereby reducing the current flow in the edge area of the shallow trench isolation area, which can effectively reduce the random noise RN and the random telegraph signal noise RTS.
[0047] Example 2
[0048] like Figure 9-10 As shown, another embodiment of the H-type source follower transistor provided by the present application, the H-type source follower transistor 01, includes a substrate 50, an isolation region 40, a source region 30, a gate region 10 and a drain region 20; wherein,
[0049] The gate region 10 is substantially H-shaped, with openings formed at opposite ends of the H-shaped gate region 10;
[0050] The source region 30 and the drain region 20 are respectively disposed at openings at opposite ends of the gate region 10 , and the widths of the source region 30 and the drain region 20 are both greater than the widths of the openings, so that there is overlap between the gate region 10 and the source region 30 , and between the gate region 10 and the drain region 20 ;
[0051] The source region 30, the gate region 10 and the drain region 20 are arranged on the first side of the substrate 50, and the isolation region 40 is arranged on the first side of the substrate 50 and is used to isolate the source region 30, the gate region 10 and the drain region 20. The isolation region 40 includes a shallow trench isolation structure.
[0052] Among them, the H-type source follower transistor provided in this embodiment Figure 5-Figure 8 The other features are basically the same, except that: the opposite ends of the H-shaped gate region are concave to form an opening, and the transition surface between the concave end surfaces of the two ends and the end surface of the overlapping region forms an angle that is not 90 degrees with the concave end surface or the end surface of the overlapping region.
[0053] Through the above structural design, the current will not be evenly distributed in the current channel, but will be reduced in the edge area of the shallow trench isolation area. By reducing the current flow in the edge area of the shallow trench isolation area, the random noise RN and random telegraph signal noise RTS can be effectively reduced.
[0054] like Figure 10 As shown, L1 represents the width of the overlapping area of the gate region and the source region active area, or represents the width of the overlapping area of the gate region and the drain region active area; L2 represents the width of the source region or the width of the drain region at the point where the distance between the source region and the drain region is the smallest. In this overlapping area, the current flow direction is no longer always parallel to the channel direction. At the same time, the closer to the edge of the isolation region, the lower the density of the current path. Near the overlapping area, the current distribution will be reduced in the edge area of the shallow trench isolation area, thereby reducing the current flow in the edge area of the shallow trench isolation area, which can effectively reduce the random noise RN and the random telegraph signal noise RTS.
[0055] Example 3
[0056] The present application also provides an image sensor, comprising a photodiode and the H-type source follower transistor as described in the first aspect.
[0057] By adopting H-type source follower transistors, although the current density in the STI edge region is reduced, the total current and transconductance remain unchanged, thereby reducing noise while ensuring that the overall performance of the pixel is not affected. The image sensor of this solution has a simple structure, does not require additional process steps and complex manufacturing processes, and has a low implementation cost.
[0058] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.
[0059] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.
Claims
1. An H-type source follower transistor, characterized in that including a substrate, an isolation region, a source region, a gate region and a drain region; wherein, The gate region is substantially H-shaped, with openings formed at opposite ends of the H-shaped gate region; The source region and the drain region are respectively provided at openings at opposite ends of the gate region, and both sides of the openings at opposite ends of the gate region are overlapping regions between the gate region and the active regions of the source region and the active regions of the drain region; The isolation region is used to isolate the source region, the gate region, and the drain region, and the isolation region includes a shallow trench isolation structure.
2. The transistor according to claim 1, wherein The opposite ends of the H-shaped gate region are concave to form openings, and the transition surface between the concave end surfaces of the two concave ends and the end surface of the overlapping region is perpendicular to the concave end surface or the end surface of the overlapping region.
3. The transistor according to claim 1, wherein The opposite ends of the H-shaped gate region are concave to form an opening, and a transition surface between the concave end surfaces of the two concave ends and the end surface of the overlapping region forms an angle that is not 90 degrees with the concave end surface or the end surface of the overlapping region.
4. The transistor according to any one of claims 1 to 3, characterized in that The gate region is located in the first layer farthest from the substrate, the source region and the drain region are located in the second layer adjacent to the first layer, the middle of the substrate is raised toward the second layer to isolate the source region from the drain region, and the isolation region is located in the second layer.
5. The transistor according to claim 4, wherein: The source region, gate region and drain region are arranged on the first side of the substrate, and the isolation region is located in the second layer and covers the first side surface of the substrate to isolate the source region, gate region and drain region.
6. The transistor according to claim 4, wherein: The first layer further includes an interlayer structure, and the interlayer structure is arranged to surround the gate region.
7. The transistor according to claim 6, wherein: The interlayer structure is a silicon nitride spacer layer or an insulating oxide layer.
8. The transistor according to any one of claims 1 to 3, characterized in that: The widths of the source region and the drain region are both greater than the width of the opening.
9. The transistor according to any one of claims 1 to 3, characterized in that: Two opposite ends of the H-shaped gate region are concave to form the opening, and the distance between the end surfaces of the two concave ends is the minimum distance between the source region and the drain region.
10. An image sensor, characterized in that: A photodiode and an H-type source follower transistor as claimed in any one of claims 1 to 9.