Array substrate and display device

Abstract

The utility model provides an array substrate and a display device, the array substrate comprises a substrate, a pore area formed on the substrate and a plurality of bonding areas arranged adjacent to the pore area, each bonding area comprises a protruding area located in the middle and an edge area arranged around the protruding area, the bonding area comprises a gate insulating layer arranged on the substrate, a metal conducting layer arranged on the gate insulating layer and a conducting thin film layer arranged on the metal conducting layer, and a heightening layer is arranged in the protruding area so that the height of the protruding area can be larger than the height of the edge area and the height of the pore area. According to the array substrate and the display device provided by the utility model, the height of the convex area is increased and the height of the gap between the convex area and the IC pad is reduced by arranging the heightening layer, so that after the particles are filled, the deformation is large, the indentation is clear, the conductivity is good, and the phenomenon of poor bonding can be effectively improved on the basis of not increasing a photomask and the cost.

Description

Technical Field

[0001] The utility model relates to an array substrate and a display device. Background Art

[0002] Despite continuous technological advancements in integrated circuit (IC) design and manufacturing, a key issue in the IC packaging process persists: surface unevenness of the IC bumps. This problem stems from a variety of factors, including but not limited to precision limitations in the manufacturing process, variations in material properties, and the accumulation of small errors in subsequent processing steps. Specifically, the IC bump surface is uneven, with a typical step difference of approximately 1.8 microns, a significant value.

[0003] This surface unevenness triggers a chain reaction during the subsequent bonding process. Bonding is a critical step in semiconductor manufacturing, involving the physical or chemical bonding of the IC chip to the array substrate or other electronic components to ensure accurate transmission of electrical signals. However, when the IC bump surface has unevenness, the pressure applied during the bonding process is difficult to evenly distribute across the entire contact surface, resulting in uncertain indentation formation—either too faint to be discerned or no effective indentation at all in some areas.

[0004] Unclear or absent indentations directly impact electrical connectivity reliability. Ideally, the IC bump and corresponding conductive structure on the array substrate should form tight and uniform contact to ensure unimpeded current and signal flow. However, in reality, poor contact due to step differences can prevent effective electrical connections in some areas, leading to increased resistance, signal attenuation, and even open circuits—all significant contributors to product failure.

[0005] Specifically, regarding the existing array substrate 10 design, Figure 1 and Figure 2 As shown, the gate insulation layer is perforated to form vias, through which the conductive film layer is connected to the metal conductive layer. This design was originally intended to achieve electrical connection between different layers, but problems emerged during the bonding process. Due to the height difference between the recessed area of ​​the IC bump 20 and the bonding area of ​​the array substrate 10, when particles 30 are used to fill the gap between the two, these particles 30 are often unable to fully adapt to this height difference due to their limited deformation ability, thus failing to achieve the ideal filling and indentation effect. This not only affects the quality of conductivity but can also lead to long-term reliability issues due to stress concentration.

[0006] In summary, the shortcomings of existing IC designs in terms of bump surface flatness, coupled with limitations in the array substrate bonding area design, pose significant challenges to electrical connectivity and product quality. Therefore, exploring and improving these aspects to reduce step differences and optimize the bonding process are key to improving semiconductor packaging technology and product yield.

[0007] In view of this, it is necessary to improve the existing array substrate to solve the above problems. Utility Model Content

[0008] The purpose of the present invention is to provide an array substrate to solve the problem of poor bonding caused by step difference.

[0009] To achieve the above-mentioned purpose, the present invention provides an array substrate, which includes a substrate, a pore area formed on the substrate, and multiple bonding areas arranged adjacent to the pore areas, each of the bonding areas includes a raised area located in the middle and an edge area arranged around the raised area, the bonding area includes a gate insulation layer arranged on the substrate, a metal conductive layer arranged on the gate insulation layer, and a conductive film layer arranged on the metal conductive layer, and a padding layer is provided in the raised area so that the height of the raised area is greater than the height of the edge area and the pore area.

[0010] As a further improvement of the present invention, the gate insulation layer includes a first gate insulation layer and a second gate insulation layer, wherein the first gate insulation layer is arranged on a side close to the substrate, and the cushioning layer is arranged between the substrate and the first gate insulation layer and / or between the first gate insulation layer and the second gate insulation layer.

[0011] As a further improvement of the present invention, the padding layer includes a first padding layer arranged between the substrate and the first gate insulating layer and a second padding layer arranged between the first gate insulating layer and the second gate insulating layer.

[0012] As a further improvement of the present invention, the first cushioning layer and the second cushioning layer are both metal laminated structures.

[0013] As a further improvement of the present invention, the material of the first padding layer is aluminum-molybdenum or molybdenum-aluminum-molybdenum, the material of the second padding layer is molybdenum-aluminum-molybdenum, and the material of the first padding layer away from the substrate is molybdenum.

[0014] As a further improvement of the present invention, the thickness of the cushioning layer is between 1800-3500 angstroms.

[0015] As a further improvement of the present invention, the projection of the raising layer on the substrate is located within the projection of the raised area on the substrate.

[0016] As a further improvement of the present invention, the aperture region includes a gate insulating layer provided on the substrate and an insulating layer provided on the gate insulating layer, and the gate insulating layer in the aperture region and the gate insulating layer in the bonding region are the same layer.

[0017] As a further improvement of the present invention, the cross-sectional profile of the portion of the raised area that is higher than the edge area is trapezoidal.

[0018] The present invention also provides a display device, which includes the array substrate as described above.

[0019] The beneficial effects of the present invention are as follows: the array substrate and display device of the present invention increase the height of the raised area by setting a cushioning layer, reduce the gap height between the raised area and the IC pad, so that after the particles are filled, the deformation becomes larger, the indentation is clear, and the conductivity is good. The phenomenon of poor bonding can be effectively improved without increasing the mask and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 is a schematic cross-sectional structural diagram of a display device in the prior art;

[0022] Figure 2 yes Figure 1 Schematic diagram of a local enlarged structure;

[0023] Figure 3 It is a schematic cross-sectional structural diagram of the display device of the present utility model;

[0024] Figure 4 yes Figure 3 Schematic diagram of a local enlarged structure;

[0025] Figure 5 It is a schematic cross-sectional structural diagram of the array substrate of the present utility model. DETAILED DESCRIPTION

[0026] The following is a clear and complete description of the technical solution of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0027] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating positions or relationships, are based on the positions or relationships shown in the accompanying drawings and are intended solely to facilitate the description of this utility model and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internal communication between two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] The terms "about," "substantially," or "approximately" are generally interpreted as within 10% of a given value or range, or within 5%, 3%, 2%, 1% or 0.5% of a given value or range.

[0030] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify elements. They do not in themselves imply or represent any previous ordinal number of the (or those) elements, nor do they represent the order of one element to another, or the order in the manufacturing method. The use of such ordinal numbers is only used to clearly distinguish an element with a certain name from another element with the same name.

[0031] It should be noted that the following embodiments may be implemented by replacing, recombining, or combining features from several different embodiments to create other embodiments without departing from the spirit of the present disclosure. Features from various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

[0032] like Figures 3 to 5 As shown, the display device of the present invention includes an array substrate 100 and an IC pad 200 .

[0033] The array substrate 100 includes a substrate 1 , a void region 2 formed on the substrate 1 , and a plurality of bonding regions 3 adjacent to the void region 2 .

[0034] The material of the substrate 1 may be glass, plastic, or a combination thereof. For example, the material of the substrate 1 may include quartz, sapphire, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), silicon germanium (SiGe), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), or other suitable materials or combinations thereof, but the present disclosure is not limited thereto. In this embodiment, the substrate 1 is a thin film transistor (TFT).

[0035] The aperture region 2 includes a gate insulating layer 21 disposed on the substrate 1 and an insulating layer 22 disposed on the gate insulating layer 21 .

[0036] The gate insulating layer 21 may be made of an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack of at least two of these materials), but the present disclosure is not limited thereto. In some embodiments, the gate insulating layer 21 may have a single-layer structure or a multi-layer structure, but the present disclosure is not limited thereto. In this embodiment, the gate insulating layer 21 has a double-layer structure. The gate insulating layer 21 serves as an insulator, preventing short circuits between the various circuits within the array substrate 100.

[0037] In some embodiments, the material of the insulating layer 22 may be silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but the present disclosure is not limited thereto.

[0038] The bonding area 3 is used to conduct to the IC pad 200 .

[0039] Each bonding region 3 includes a centrally located raised region 31 and an edge region 32 surrounding the raised region 31. The bonding region 3 comprises a gate insulating layer 21 disposed on the substrate 1, a metal conductive layer 33 disposed on the gate insulating layer 21, and an ITO conductive film layer 34 disposed on the metal conductive layer 33. A raised layer is provided within the raised region 31 to ensure that the raised region 31 is higher than the edge region 32. The height of the raised region 31 is also higher than that of the aperture region 2. The height of the edge region 32 relative to the aperture region 2 is not limited; generally, the heights of the edge region 32 are preferably comparable.

[0040] The bonding process can be completed only after the conductive film layer ITO 34 is manufactured.

[0041] In an embodiment, the array substrate 100 includes a display area and a non-display area, the pore area 2 and the bonding area 3 are both arranged in the non-display area, the metal signal lines of the first padding layer 35 in the display area are completed by the same photomask process, the gate and scanning lines of the second padding layer 36 in the display area are completed by the same photomask process, the source, drain and data lines of the metal conductive layer 33 in the display area are completed by the same photomask process, and the ITO transparent conductive layer of the conductive film layer ITO 34 in the display area is completed by the same photomask process. The ITO transparent conductive layer can be a pixel electrode or a common electrode.

[0042] In this embodiment, a padding layer is provided to increase the height of the raised area 31 and reduce the gap height between the raised area 31 and the IC pad 200. This allows the particles 300 to have a larger deformation, a clearer indentation, and better conductivity after filling. This effectively improves the bonding problem without increasing the mask and cost.

[0043] The gate insulation layer 21 includes a first gate insulation layer 211 and a second gate insulation layer 212, wherein the first gate insulation layer 211 is arranged on a side close to the substrate 1, and the spacer layer is arranged between the substrate 1 and the first gate insulation layer 211 and / or between the first gate insulation layer 211 and the second gate insulation layer 212.

[0044] In this embodiment, the raising layer includes a first raising layer 35 disposed between the substrate 1 and the first gate insulating layer 211 and a second raising layer 36 disposed between the first gate insulating layer 211 and the second gate insulating layer 212 .

[0045] The first raising layer 35 and the second raising layer 36 both have a metal laminated structure.

[0046] In this embodiment, the material of the first padding layer 35 is aluminum-molybdenum or molybdenum-aluminum-molybdenum, the material of the second padding layer 36 is molybdenum-aluminum-molybdenum, and the material of the first padding layer 35 on the side away from the substrate 1 is molybdenum. Molybdenum can effectively resist corrosion from some metal etching solutions, thereby increasing the lifespan of the first padding layer 35 and the second padding layer 36.

[0047] However, the material selection for the spacer layer is not limited thereto. In some embodiments, the spacer layer may include a low-resistance material such as copper (Cu), titanium (Ti), silver (Ag), gold (Au), tin (Sn), nickel (Ni), or a combination thereof. However, the spacer layer may also be made of other suitable materials or combinations thereof, and the present disclosure is not limited thereto.

[0048] The thickness of the cushioning layer is between 1800 and 3500 angstroms. At this thickness, the cushioning layer provides good support and is easy to manufacture. In some embodiments, if the height difference is large and one or two cushioning layers are still insufficient, the number of cushioning layers can be increased, so that the cushioning layers have a stacked structure.

[0049] The projection of the elevating layer on the substrate 1 is within the projection of the raised area 31 on the substrate 1. The projection here refers to the projection in the direction perpendicular to the substrate 1, that is, in this embodiment, the size of the elevating layer is smaller than that of the raised area 31.

[0050] The gate insulating layer 21 in the aperture region 2 is the same layer as the gate insulating layer 21 in the bonding region 3. In other words, in this embodiment, the gate insulating layer 21 in the bonding region 3 does not need to be perforated, and the gate insulating layer 21 can also play a certain lifting effect in the bonding region 3.

[0051] The cross-sectional profile of the portion of the raised area 31 that is higher than the edge area 32 is trapezoidal.

[0052] In this embodiment, the thickness of the first cushioning layer 35 and the second cushioning layer 36 are both 2500 angstroms, while the thickness of the first gate insulating layer 211 and the second gate insulating layer 212 are 3000 angstroms and 3500 angstroms respectively. It can be seen that the bonding area is increased by 11500 angstroms, i.e. 1.15 microns, which greatly reduces the step difference.

[0053] The array substrate 100 and display device of the present invention increase the height of the raised area 31 by providing a spacer layer, thereby reducing the gap between the raised area 31 and the IC pad 200. This allows the particles 300 to have a larger deformation, a clearer indentation, and better conductivity after being filled. This effectively improves the problem of poor bonding without increasing the number of masks or costs.

[0054] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] The above-described embodiments merely represent several implementation methods of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the concept of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate includes a substrate, a pore area formed on the substrate, and multiple bonding areas arranged adjacent to the pore areas. Each bonding area includes a raised area located in the middle and an edge area arranged around the raised area. The bonding area includes a gate insulation layer arranged on the substrate, a metal conductive layer arranged on the gate insulation layer, and a conductive film layer arranged on the metal conductive layer. A padding layer is provided in the raised area so that the height of the raised area is greater than the height of the edge area and the pore area.

2. The array substrate according to claim 1, wherein: The gate insulation layer includes a first gate insulation layer and a second gate insulation layer, wherein the first gate insulation side is arranged on a side close to the substrate, and the raising layer is arranged between the substrate and the first gate insulation layer and / or between the first gate insulation layer and the second gate insulation layer.

3. The array substrate according to claim 2, wherein: The raising layer includes a first raising layer disposed between the substrate and the first gate insulating layer and a second raising layer disposed between the first gate insulating layer and the second gate insulating layer.

4. The array substrate according to claim 3, wherein: The first padding layer and the second padding layer both have metal laminated structures.

5. The array substrate according to claim 4, wherein: The material of the first padding layer is aluminum-molybdenum or molybdenum-aluminum-molybdenum, the material of the second padding layer is molybdenum-aluminum-molybdenum, and the material of the first padding layer away from the substrate is molybdenum.

6. The array substrate according to claim 1, wherein: The thickness of the cushioning layer is between 1800 and 3500 angstroms.

7. The array substrate according to claim 1, wherein: The projection of the raising layer on the substrate is located within the projection of the raised area on the substrate.

8. The array substrate according to claim 1, wherein: The pore region includes a gate insulating layer arranged on the substrate and an insulating layer arranged on the gate insulating layer. The gate insulating layer in the pore region and the gate insulating layer in the bonding region are the same layer.

9. The array substrate according to claim 1, wherein: The cross-sectional profile of a portion of the raised area that is higher than the edge area is trapezoidal.

10. A display device, characterized in that: The display device includes the array substrate according to any one of claims 1 to 9.

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