Solar cell and photovoltaic module

Abstract

The utility model belongs to the technical field of photovoltaic power generation, and provides a solar cell and a photovoltaic module. The solar cell comprises a photoelectric conversion layer, a tunneling oxide layer, a doped polycrystalline silicon layer and a barrier regulation and control layer, and the photoelectric conversion layer comprises a first surface and a second surface which are opposite to each other; the tunneling oxide layer, the doped polycrystalline silicon layer and the barrier regulation and control layer are sequentially stacked on the first surface and / or the second surface in the direction away from the photoelectric conversion layer. According to the solar cell provided by the invention, the potential barrier regulation and control layer is arranged on the surface of the solar cell, so that the potential barrier during carrier transmission can be reduced.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic power generation technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells can convert light energy into electrical energy.

[0003] Among them, tunnel oxide passivated contact (TOPCon) solar cells have a high conversion efficiency. TOPCon solar cells include a silicon substrate, a tunnel oxide layer, a doped polysilicon layer, and electrodes. Sunlight irradiates the silicon substrate, generating carriers. The carriers pass through the tunnel oxide layer and the doped polysilicon layer into the external circuit to provide electrical energy. By providing a tunnel oxide layer and a doped polysilicon layer on the silicon substrate, the surface recombination and metal contact recombination of the solar cell can be reduced, thereby improving the photoelectric conversion efficiency.

[0004] However, the potential barrier for carriers to transmit in the doped polysilicon layer is relatively large. Utility Model Content

[0005] The present application provides a solar cell and a photovoltaic module, which can reduce the potential barrier during carrier transmission by providing a potential barrier control layer on the surface of the solar cell.

[0006] The present application provides a solar cell, comprising: a photoelectric conversion layer, a tunneling oxide layer, a doped polysilicon layer, and a barrier regulation layer, wherein the photoelectric conversion layer comprises a first surface and a second surface opposite to each other; the tunneling oxide layer, the doped polysilicon layer, and the barrier regulation layer are sequentially stacked on the first surface and / or the second surface in a direction away from the photoelectric conversion layer.

[0007] In a possible embodiment, the solar cell provided in the present application further includes a protective layer, the barrier regulation layer is located between the doped polysilicon layer and the protective layer, and the barrier regulation layer is used to isolate the protective layer and the doped polysilicon layer.

[0008] In a possible embodiment, the solar cell provided in the present application further includes a first electrode layer, and the first electrode layer is arranged on a side of the protective layer away from the barrier regulation layer.

[0009] In one possible embodiment, in the solar cell provided by the present application, the tunneling oxide layer, the doped polysilicon layer, the barrier control layer and the protective layer are located on the second surface of the photoelectric conversion layer; the solar cell also includes a first passivation layer and an anti-reflection layer, and the first passivation layer and the anti-reflection layer are stacked in sequence on the first surface in a direction away from the photoelectric conversion layer, and a first electrode layer is provided on the anti-reflection layer.

[0010] In one possible embodiment, the solar cell provided by the present application comprises a tunneling oxide layer, a doped polysilicon layer, and a protective layer stacked in sequence on the first and second surfaces of the photoelectric conversion layer and on the emission layer, and a barrier control layer is provided between the doped polysilicon layer on the first surface and the protective layer;

[0011] And / or, a barrier regulating layer is provided between the doped polysilicon layer and the protective layer on the second surface.

[0012] In one possible embodiment, the solar cell provided in the present application, the doped polysilicon layer includes a metal contact area and a non-metal contact area, and a barrier control layer is provided on both the metal contact area and the non-metal contact area, and the barrier control layer is used to make the metal contact area and the non-metal contact area conductive.

[0013] In a possible embodiment, the solar cell provided in the present application further includes a second electrode layer, where the second electrode layer is disposed on the metal contact region and is electrically connected to the barrier control layer.

[0014] In a possible embodiment, in the solar cell provided by the present application, the thickness of the doped polysilicon layer is less than or equal to 80 nm; and / or the thickness of the barrier control layer is less than or equal to 15 nm.

[0015] In one possible embodiment, in the solar cell provided in the present application, the thickness of the doped polysilicon layer is less than or equal to 30 nm and greater than or equal to 10 nm; and / or the thickness of the barrier control layer is less than or equal to 10 nm and greater than or equal to 0.1 nm.

[0016] In a possible embodiment, in the solar cell provided by the present application, the barrier regulation layer includes a conductive carbon material layer.

[0017] In a possible embodiment, in the solar cell provided in the present application, the barrier regulation layer includes a conductive carbon material layer and a second passivation layer, and the conductive carbon material layer is disposed between the doped polysilicon layer and the second passivation layer.

[0018] In a possible implementation, in the solar cell provided in the present application, the photoelectric conversion layer includes a silicon substrate and an emission layer, the emission layer faces the first surface, and the silicon substrate faces the second surface.

[0019] The present application also provides a photovoltaic assembly comprising at least one of the above-mentioned solar cells, wherein the solar cell is used to convert sunlight energy into electrical energy.

[0020] The present application also provides a method for preparing a solar cell, comprising:

[0021] Providing a silicon substrate, and forming an emission layer on a first surface of the silicon substrate;

[0022] A tunneling oxide layer, a doped polysilicon layer and a barrier regulating layer are formed on the second surface of the silicon substrate; or a tunneling oxide layer, a doped polysilicon layer and a barrier regulating layer are formed on both the emitter layer and the second surface of the silicon substrate.

[0023] In a possible embodiment, the solar cell preparation method provided in the present application further includes: forming a protective layer on the barrier regulation layer.

[0024] In a possible embodiment, the solar cell manufacturing method provided in the present application further includes: forming a metal contact region and a non-metallic contact region on the doped polysilicon layer before forming the barrier control layer.

[0025] The solar cell provided in the present application is provided with a photoelectric conversion layer, a tunneling oxide layer, a doped polysilicon layer and a barrier control layer. The photoelectric conversion layer includes a first surface and a second surface relative to each other; the tunneling oxide layer, the doped polysilicon layer and the barrier control layer are sequentially stacked on the first surface and / or the second surface in a direction away from the photoelectric conversion layer. By providing the barrier control layer, the barrier control layer can reduce the carrier transmission barrier because it can prevent the formation of a silicon dioxide intermediate layer on the surface of the doped polysilicon layer; or the barrier control layer can improve the carrier collection efficiency, thereby reducing the carrier transmission barrier. Therefore, by providing the barrier control layer, the carrier transmission barrier in various solar cells can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1a A schematic diagram of the structure of a solar cell in related art 1;

[0028] Figure 1b Schematic diagram of another structure of a solar cell in related art 1;

[0029] Figure 2 It is a structural diagram of a solar cell in related technology 2;

[0030] Figure 3 Schematic diagram 1 of the structure of the solar cell provided in the embodiment of the present application;

[0031] Figure 4 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 2 ;

[0032] Figure 5 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 3 ;

[0033] Figure 6 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 4 ;

[0034] Figure 7 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 5 ;

[0035] Figure 8 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 6 ;

[0036] Figure 9 Flowchart 1 of the solar cell manufacturing method provided in an embodiment of the present application;

[0037] Figure 10 The solar cell manufacturing method provided in the embodiment of the present application Figure 2 ;

[0038] Figure 11 The solar cell manufacturing method provided in the embodiment of the present application Figure 3 .

[0039] Description of reference numerals:

[0040] 10-silicon substrate; 11-tunneling oxide layer; 12-doped polysilicon layer; 13-electrode layer;

[0041] 20-silicon substrate; 21-tunneling oxide layer; 22-doped polysilicon layer; 23-electrode layer; 24-antireflection layer;

[0042] 100-solar cell; 100a-photovoltaic conversion layer;

[0043] 110 - silicon substrate; 111 - first surface; 112 - second surface;

[0044] 120-emission layer;

[0045] 130- tunneling oxide layer;

[0046] 140 - doped polysilicon layer; 141 - metal contact region; 142 - non-metal contact region;

[0047] 150-barrier control layer; 151-conductive carbon material layer; 152-second passivation layer;

[0048] 160-protective layer;

[0049] 171 - first electrode layer; 172 - second electrode layer;

[0050] 180-first passivation layer;

[0051] 190-Anti-reflection layer. DETAILED DESCRIPTION

[0052] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0053] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to a fixed connection, an indirect connection via an intermediate medium, internal communication between two components, or an interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0054] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0055] The terms "first," "second," and "third" (if any) in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the application described herein can, for example, be implemented in orders other than those illustrated or described herein.

[0056] In addition, the terms "comprises" and "having" and any variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or service tool that includes a series of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, product or service tool.

[0057] Solar cells can convert light energy into electrical energy.

[0058] Among them, tunnel oxide passivated contact (TOPCon) solar cells have a high conversion efficiency. TOPCon solar cells include a silicon substrate, a tunnel oxide layer, a doped polysilicon layer, and electrodes. Sunlight irradiates the silicon substrate to generate carriers, which pass through the tunnel oxide layer and the doped polysilicon layer into the external circuit to provide electrical energy. By arranging a tunnel oxide layer and a doped polysilicon layer on the silicon substrate, the tunnel oxide layer and the doped polysilicon layer form a passivation contact structure. The passivation contact structure can reduce surface recombination and metal contact recombination of the solar cell, thereby improving the photoelectric conversion efficiency.

[0059] Figure 1a A schematic diagram of the structure of a solar cell in related art 1; Figure 1b This is another structural schematic diagram of a solar cell in related technology 1.

[0060] See also Figure 1a and Figure 1b As shown, the solar cell includes a silicon substrate 10, a tunneling oxide layer 11, and a doped polysilicon layer 12, on which an electrode layer 13 is disposed. Silicon dioxide is generated on the surface of the doped polysilicon layer 12 away from the tunneling oxide layer, which increases the electron transmission barrier.

[0061] Figure 2 It is a structural diagram of a solar cell in related technology 2.

[0062] See also Figure 2 As shown, the solar cell includes a silicon substrate 20, a tunneling oxide layer 21, and a doped polysilicon layer 22. An electrode layer 23 is disposed on the doped polysilicon layer 22. In areas where the electrode layer 23 is not disposed, the doped polysilicon layer 22 is etched away to reduce parasitic absorption. Furthermore, an anti-reflection layer 24 may be disposed on the doped polysilicon layer 22. If the electrode layer 23 experiences a gate break or poor contact, electrons in the etched area are less likely to converge on the electrode layer 23, thereby increasing the carrier barrier.

[0063] Based on this, the embodiments of the present application provide a solar cell and a photovoltaic module, which can reduce the potential barrier during carrier transmission by providing a barrier control layer on the surface of the solar cell.

[0064] Figure 3 Schematic diagram 1 of the structure of the solar cell provided in the embodiment of the present application; Figure 4 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 2 ; Figure 5 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 3The solar cell provided in the embodiment of the present application is shown as 100, and the stacked structure in the solar cell is also shown as a three-digit number to distinguish it from the solar cell in the related art.

[0065] See also Figures 3 to 5 As shown, the solar cell 100 provided by the present application includes a photoelectric conversion layer 100a, a tunneling oxide layer 130, a doped polysilicon layer 140, and a barrier control layer 150. The photoelectric conversion layer 100a includes a first surface 111 and a second surface 112 opposite to each other. The emission layer 120 is provided on the first surface 111 of the silicon substrate 110. The tunneling oxide layer 130, the doped polysilicon layer 140, and the barrier control layer 150 are stacked in sequence on the first surface 111 and the second surface 112 in a direction away from the photoelectric conversion layer 100a.

[0066] Specifically, the photoelectric conversion layer 100a has a first surface 111 and a second surface 112 opposite to each other along the thickness direction of the solar cell 100 . The photoelectric conversion layer 100a includes a silicon substrate 110 and an emission layer 120 . The emission layer 120 faces the first surface 111 , and the silicon substrate 110 faces the second surface 112 .

[0067] The silicon substrate 110 can be an N-type silicon substrate. Boron is diffused at high temperature on the side of the silicon substrate 110 facing the first surface 111 to form a P-type emitter layer 120. A PN junction can be formed between the silicon substrate 110 and the emitter layer 120. When a solar cell is deployed, the first surface 111 faces sunlight. When sunlight strikes the PN junction, photogenerated carriers are generated. These carriers can be transmitted to an external circuit, converting light energy into electrical energy.

[0068] The tunneling oxide layer 130, the doped polysilicon layer 140 and the barrier control layer 150 are stacked in sequence in a direction away from the photoelectric conversion layer 100a. Figure 3 In the embodiment shown, the tunneling oxide layer 130, the doped polysilicon layer 140 and the barrier control layer 150 may be located on one side of the second surface 112. Figure 4 and Figure 5 In the illustrated embodiment, a tunneling oxide layer 130 , a doped polysilicon layer 140 and a barrier control layer 150 are sequentially stacked on both the first surface 111 and the second surface 112 .

[0069] Next, the barrier control layer 150 can be reduced Figure 3 and Figure 4 The principle of the transport barrier for carriers in the solar cell 100 shown will be described.

[0070] Please continue to see Figure 3 and Figure 4As shown, the solar cell 100 further includes a protective layer 160 . The barrier control layer 150 is located between the doped polysilicon layer 140 and the protective layer 160 . The barrier control layer 150 is used to isolate the protective layer 160 from the doped polysilicon layer 140 .

[0071] Please continue to see Figure 3 and Figure 4 As shown, the solar cell 100 further includes a first electrode layer 171, which is disposed on the side of the protective layer 160 facing away from the barrier control layer 150. After passing through the tunneling oxide layer 130 and the doped polysilicon layer 140, carriers are transmitted to the external circuit through the first electrode layer 171. The first electrode layer 171 can be a conductive layer formed of a conductive metal (e.g., silver) or a conductive layer formed of other conductive materials.

[0072] The tunneling oxide layer 130 may be silicon oxide, and the doped polysilicon layer 140 may be a P-type doped polysilicon layer 140 formed by doping intrinsic silicon with boron at a relatively high concentration. The doped polysilicon layer 140 may also be an N-type doped polysilicon layer 140 formed by doping intrinsic silicon with phosphorus at a relatively high concentration. The tunneling oxide layer 130 and the doped polysilicon layer 140 may form a passivation contact structure.

[0073] When the doped polysilicon layer 140 is thick, it absorbs more sunlight, resulting in less solar energy reaching the PN junction. Consequently, parasitic absorption is more severe when the doped polysilicon layer is thicker. When the doped polysilicon layer 140 is thinner, during the subsequent preparation of the first electrode layer 171, metal substrate particles forming the first electrode layer 171 may penetrate the doped polysilicon layer 140 and enter the tunneling oxide layer 130 and silicon substrate 110, increasing carrier metal-contact recombination.

[0074] The protective layer 160 can be a thin layer of conductive oxide (Transparent Conductive Oxide, abbreviated as TCO). Therefore, by providing the protective layer 160, metal substrate particles can be blocked from entering the tunneling oxide layer 130 and the silicon substrate 110, thereby reducing the thickness of the doped polysilicon layer 140. However, the protective layer 160 will damage the doped polysilicon layer 140 during the preparation process. A silicon dioxide intermediate layer will also be formed at the interface between the protective layer 160 and the doped polysilicon layer 140. In the path where carriers pass through the tunneling oxide layer 130, the doped polysilicon layer 140 and the protective layer 160 from the silicon substrate 110 to the first electrode layer 171, the silicon dioxide intermediate layer will increase the transmission barrier of the carriers.

[0075] In an embodiment of the present application, before forming the protective layer 160, a barrier control layer 150 may be provided on the side of the doped polysilicon layer 140 facing away from the tunneling oxide layer 130. The barrier control layer 150 not only prevents damage to the doped polysilicon layer 140 during the preparation of the protective layer 160, but also prevents the formation of a silicon dioxide intermediate layer at the interface between the protective layer 160 and the doped polysilicon layer 140, thereby reducing the carrier transmission barrier.

[0076] Next, the barrier control layer 150 can be reduced Figure 5 The principle of the transport barrier for carriers in the solar cell 100 shown will be described.

[0077] Please continue to see Figure 5 As shown, the doped polysilicon layer 140 includes a metal contact area 141 and a non-metal contact area 142. A barrier control layer 150 is provided on both the metal contact area 141 and the non-metal contact area 142. The barrier control layer 150 is used to make the metal contact area 141 and the non-metal contact area 142 conductive.

[0078] Please continue to see Figure 5 As shown, the solar cell 100 further includes a second electrode layer 172, which is disposed on the metal contact region 141 and is electrically connected to the barrier control layer 150. The second electrode layer 172 can be a conductive layer formed of a conductive metal (e.g., silver) or other conductive materials.

[0079] Specifically, the doped polysilicon layer 140 can be divided into a metal contact region 141 and a non-metal contact region 142. The metal contact region 141 is used to set the second electrode layer 172. At the position where the second electrode layer 172 is not set, the doped polysilicon layer 140 can be thinned by etching or the like, or the doped polysilicon layer 140 at the position where the second electrode layer 172 is not set can be completely etched away to reduce the parasitic absorption of the doped polysilicon layer 140. The region where the doped polysilicon layer 140 is thinned or completely etched is the non-metal contact region 142. This structure is called a finger structure. Both sides of the solar cell 100 can be a finger structure (for example Figure 5 As shown), the solar cell 100 may also have a finger structure on one side. When one side has a finger structure, the structure of the other side is the same as Figure 3 The structure of the first surface 111 of the solar cell 100 is similar and will not be described in detail here.

[0080] When carriers travel from the silicon substrate 110 through the tunneling oxide layer 130 and the doped polysilicon layer 140 to reach the second electrode layer 172, the carriers in the tunneling oxide layer 130 corresponding to the non-metallic contact region 142 need to move through the tunneling oxide layer 130 to the position of the tunneling oxide layer 130 corresponding to the metal contact region 141, and then enter the second electrode layer 172 through the metal contact region 141. If the second electrode layer 172 has a broken gate and poor contact with the metal contact region 141, the carrier collection efficiency is low, thereby increasing the carrier barrier.

[0081] By providing a barrier control layer 150 on the doped polysilicon layer 140, the transmission barrier of carriers can be reduced. Specifically, the barrier control layer 150 is provided on both the metal contact region 141 and the non-metal contact region 142. Carriers in the tunneling oxide layer 130 corresponding to the non-metal contact region 142 enter the barrier control layer 150 and are transmitted to the second electrode layer 172 through the barrier control layer 150. Carriers in the tunneling oxide layer 130 corresponding to the metal contact region 141 flow through the metal contact region 141 and enter the second electrode layer 172.

[0082] The solar cell 100 provided in an embodiment of the present application is provided with a photoelectric conversion layer 100a, a tunneling oxide layer 130, a doped polysilicon layer 140, and a barrier control layer 150. The photoelectric conversion layer 100a includes a first surface 111 and a second surface 112 opposite each other; the tunneling oxide layer 130, the doped polysilicon layer 140, and the barrier control layer 150 are sequentially stacked on the first surface 111 and / or the second surface 112 in a direction away from the photoelectric conversion layer 100a. By providing the barrier control layer 150, the barrier control layer 150 can prevent the formation of a silicon dioxide intermediate layer on the surface of the doped polysilicon layer 140, thereby reducing the carrier transmission barrier; or the barrier control layer 150 can improve the carrier collection efficiency, thereby reducing the carrier transmission barrier. Therefore, by providing the barrier control layer 150, the carrier transmission barrier in various solar cells 100 can be reduced.

[0083] Next, Figure 3 The stacked structure of the solar cell 100 in the illustrated embodiment will be described in detail.

[0084] Please continue to see Figure 3As shown, the tunneling oxide layer 130, the doped polysilicon layer 140, the barrier control layer 150, and the protective layer 160 are located on the second surface 112 of the photoelectric conversion layer (100a). The solar cell 100 further includes a first passivation layer 180 and an anti-reflection layer 190. The first passivation layer 180 and the anti-reflection layer 190 are sequentially stacked on the first surface (111) in a direction away from the photoelectric conversion layer 100a. The first electrode layer 171 is provided on the anti-reflection layer 190. At this time, the first electrode layer 171 passes through the anti-reflection layer 190 and contacts the first passivation layer 180.

[0085] The first passivation layer 180 may be aluminum oxide, and the anti-reflection layer 190 may be silicon nitride. When sunlight is incident from the first surface 111, the anti-reflection layer 190 can reduce reflection of the sunlight. The first passivation layer 180 and the emission layer 120 can also form a passivation contact structure to reduce carrier recombination in the emission layer 120 and the first passivation layer 180. Parasitic absorption in the first passivation layer 180 is also low, thereby improving the utilization rate of sunlight.

[0086] The tunneling oxide layer 130, doped polysilicon layer 140, barrier control layer 150, and protective layer 160 are located on the second surface 112. Less sunlight enters the silicon substrate 110 through the second surface 112, and the passivation effect of the tunneling oxide layer 130 and doped polysilicon layer 140 is superior to that of the first passivation layer 180. Therefore, by reducing light absorption on the first surface 111 side and improving passivation on the second surface 112 side, the efficiency of the solar cell 100 can be maximized.

[0087] Figure 6 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 4 ; Figure 7 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 5 Next, Figure 4 The stacked structure of the solar cell 100 in the illustrated embodiment will be described in detail.

[0088] See also Figure 4 、 Figure 6 and Figure 7 As shown, a tunneling oxide layer 130, a doped polysilicon layer 140, and a protective layer 160 are sequentially stacked on both the first side 111 and the second side 112 of the photoelectric conversion layer 100a. A barrier control layer 150 is disposed between the doped polysilicon layer 140 and the protective layer 160 on the first side 111; and / or a barrier control layer 150 is disposed between the doped polysilicon layer 140 and the protective layer 160 on the second side 112.

[0089] Next, Figure 4The stacked structure of the solar cell 100 in the embodiment shown is described in detail. Figure 4 As shown, when the tunneling oxide layer 130, the doped polysilicon layer 140, the barrier control layer 150, and the protective layer 160 are provided on one side of the first surface 111, the barrier control layer 150 can reduce the thickness of the doped polysilicon layer 140, thereby reducing parasitic absorption in the doped polysilicon layer 140. By providing the barrier control layer 150, the good passivation effect of the doped polysilicon layer 140 and the tunneling oxide layer 130 can be utilized while reducing parasitic absorption in the doped polysilicon layer 140.

[0090] Please continue to see Figure 4 As shown, the doped polysilicon layer 140 disposed on one side of the emitter layer 120 is a P-type doped polysilicon layer 140, and the doped polysilicon layer 140 disposed on the second surface 112 is an N-type doped polysilicon layer 140. This arrangement can facilitate the migration of carriers toward the first electrode layers 171 on both sides.

[0091] In addition, the barrier control layer 150 ( Figure 6 ), or a barrier control layer 150 is provided only between the doped polysilicon layer 140 and the protective layer 160 on the first surface 111 (see Figure 7 The barrier regulating layer 150 may be provided according to the actual use requirements of the solar cell 100, so that the structure of the solar cell 100 is more diversified.

[0092] In one possible embodiment, the thickness of the doped polysilicon layer 140 is less than or equal to 80 nm. By providing the barrier control layer 150, the thickness of the doped polysilicon layer 140 can be set smaller to reduce parasitic absorption as much as possible. Preferably, the thickness of the doped polysilicon layer 140 can be less than or equal to 30 nm. For example, the thickness of the doped polysilicon layer 140 can be 20 nm. It should be noted that when the thickness of the doped polysilicon layer 140 is too thin, the effect of reducing surface recombination and metal contact recombination is limited. Therefore, the thickness of the doped polysilicon layer 140 can be greater than or equal to 10 nm.

[0093] If the barrier control layer 150 is too thick, it will reduce the absorption rate of sunlight. Therefore, under the premise of satisfying barrier control, the thickness of the barrier control layer 150 can be set to be smaller. The thickness of the barrier control layer 150 can be less than or equal to 15nm. Preferably, the thickness of the barrier control layer 150 can be less than or equal to 10nm. If the thickness of the barrier control layer 150 is too small, it will not be able to protect the doped polysilicon layer 140. Therefore, the thickness of the barrier control layer 150 can be greater than or equal to 0.1nm.

[0094] Please continue to see Figures 3 to 5 As shown, the barrier control layer 150 includes a conductive carbon material layer 151. The conductive carbon material layer can be a conductive carbon material layer such as C60 or graphene. The conductive carbon material layer 151 has a large energy band, thereby facilitating carrier migration. The conductive carbon material layer 151 does not absorb light, so adding the barrier control layer 150 does not increase parasitic absorption.

[0095] Figure 8 Schematic diagram of the structure of the solar cell provided in the embodiment of the present application Figure 6 .

[0096] See also Figure 8 As shown, the barrier regulating layer 150 includes a conductive carbon material layer 151 and a second passivation layer 152 , and the conductive carbon material layer 151 is disposed between the doped polysilicon layer 140 and the second passivation layer 152 .

[0097] The second passivation layer 152 may also be TCO, which can reduce surface recombination and metal contact recombination of the solar cell 100. In addition, the conductive carbon material layer 151 can also reduce damage to the doped polysilicon layer 140 during the preparation of the second passivation layer 152.

[0098] The embodiment of the present application further provides a photovoltaic assembly, which includes a plurality of solar cells 100 provided in the above embodiment.

[0099] The structure of the solar cell 100 has been described in detail in the above embodiments and will not be repeated here. The solar cell 100 can convert light energy into electrical energy. Multiple solar cells 100 can be connected in series or in parallel through electrode layers to transmit electrical energy to an external circuit.

[0100] Figure 9 Flowchart 1 of the solar cell manufacturing method provided in an embodiment of the present application.

[0101] See also Figure 9 As shown, the embodiment of the present application also provides a method for preparing a solar cell, comprising:

[0102] S101 , providing a silicon substrate 110 , and forming an emission layer 120 on a first surface 111 of the silicon substrate 110 .

[0103] An N-type silicon substrate 110 is provided. A pyramid texture is formed on the first surface 111 of the silicon substrate 110. Boron is diffused at high temperature on the first surface 111 to form a P-type emitter layer 120. Before proceeding to the next step, the boron-silicon mixture formed on the second surface 112 needs to be removed. A textured structure can also be formed on the second surface 112.

[0104] S102, forming a tunneling oxide layer 130, a doped polysilicon layer 140 and a barrier control layer 150 on the second surface 112 of the silicon substrate 110; or forming a tunneling oxide layer 130, a doped polysilicon layer 140 and a barrier control layer 150 on both the emission layer 120 and the second surface 112 of the silicon substrate 110.

[0105] First, yes Figure 3 The preparation process of the tunneling oxide layer 130, the doped polysilicon layer 140 and the barrier control layer 150 in the solar cell 100 is described below.

[0106] A tunnel oxide layer 130 is formed on the second surface 112 by methods such as plasma enhanced atomic layer deposition (PEALD), thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), and hot wire assisted chemical vapor deposition (HWCVD). The thickness of the tunnel oxide layer 130 can be 0.5-2 nm.

[0107] N-type doped amorphous silicon is then formed on the tunneling oxide layer 130. The thickness of the N-type amorphous silicon can be 5-250 nm. A mask layer is then formed on the N-type amorphous silicon. The N-type amorphous silicon is then annealed in a high temperature environment (greater than 800°C) to form a doped polysilicon layer 140. Cleaning is performed again to remove the mask layer and the boron-silicon mixture on the first surface 111 and the second surface 112 of the doped polysilicon layer 140. A first passivation layer 180 is then formed on the emitter layer 120. The thickness of the first passivation layer 180 can be 1-10 nm. Cleaning is performed again to remove the first passivation layer 180 on the second surface 112. An anti-reflection layer 190 is then formed on the first passivation layer 180. The thickness of the anti-reflection layer 190 can be 5-250 nm.

[0108] A barrier regulating layer 150 is formed on the doped polysilicon layer 140 .

[0109] By alternately forming a stacked structure on the first surface 111 and the second surface 112, a solar cell 100 can be formed, comprising a tunneling oxide layer 130, a doped polysilicon layer 140, and a barrier control layer 150 on the second surface 112 of the silicon substrate 110; and a first passivation layer 180 and an anti-reflection layer 190 on the emitter layer 120. Barrier control layer 150 is located outside doped polysilicon layer 140, effectively preventing the formation of silicon dioxide on the surface of doped polysilicon layer 140.

[0110] Next, Figure 4 The preparation process of the tunneling oxide layer 130, the doped polysilicon layer 140 and the barrier control layer 150 in the solar cell 100 is described below.

[0111] The tunnel oxide layer 130 is formed on both the emitter layer 120 and the second surface 112 by using methods such as PEALD, thermal oxidation, PECVD, and HWCVD. The thickness of the tunnel oxide layer 130 can be 0.5-2 nm.

[0112] P-type amorphous silicon is formed on the tunneling oxide layer 130 on the side of the emitter layer 120, and N-type amorphous silicon is formed on the tunneling oxide layer 130 on the side of the second surface 112. The thickness of the P-type amorphous silicon and the N-type amorphous silicon can be 5-250 nm. The P-type amorphous silicon and the N-type amorphous silicon are annealed in a high temperature environment (greater than 800°C) to form a P-type doped polysilicon layer 140 and an N-type doped polysilicon layer 140, respectively. Cleaning is performed to remove the oxide layer formed on the doped polysilicon layer 140. A barrier control layer 150 is formed on the doped polysilicon layer 140.

[0113] It can be seen that when tunneling oxide layer 130, doped polysilicon layer 140, and barrier control layer 150 are provided on both emitter layer 120 and second surface 112 of silicon substrate 110, the stacked structures on emitter layer 120 and second surface 112 of silicon substrate 110 can be fabricated simultaneously. Barrier control layer 150 is located outside doped polysilicon layer 140, effectively preventing the formation of silicon dioxide on the surface of doped polysilicon layer 140.

[0114] Next, Figure 5 and Figure 8 The preparation process of the tunneling oxide layer 130, the doped polysilicon layer 140 and the barrier control layer 150 in the solar cell 100 is described below.

[0115] The tunnel oxide layer 130 is formed on both the emitter layer 120 and the second surface 112 by using methods such as PEALD, thermal oxidation, PECVD, and HWCVD. The thickness of the tunnel oxide layer 130 can be 0.5-2 nm.

[0116] P-type amorphous silicon is prepared on the tunneling oxide layer 130 on one side of the emitter layer 120, and doped N-type amorphous silicon is prepared on the tunneling oxide layer 130 on the second side 112. The thickness of the P-type amorphous silicon and the N-type amorphous silicon can be 5-250nm. The P-type amorphous silicon and the N-type amorphous silicon are annealed in a high temperature environment (greater than 800°C) to form a P-type doped polysilicon layer 140 and an N-type doped polysilicon layer 140, respectively. Cleaning is performed to remove the oxide layer formed on the doped polysilicon layer 140. Metal contact areas 141 and non-metal contact areas 142 are formed on the doped polysilicon layer 140 by etching. A barrier control layer 150 is formed on the metal contact areas 141 and the non-metal contact areas 142.

[0117] The barrier control layer 150 can collect carriers in the metal contact area 141 and the non-metal contact area 142. The resistance of the barrier control layer 150 is smaller than that of electrons tunneling through the oxide layer 130. Therefore, the collection efficiency of carriers in the barrier control layer 150 is higher and the potential barrier during transmission is smaller.

[0118] When one side of the solar cell 100 is a finger structure, the preparation method of the other side is the same as Figure 3 The manufacturing method of the solar cell 100 is similar and will not be described in detail here.

[0119] Figure 10 The solar cell manufacturing method provided in the embodiment of the present application Figure 2 .

[0120] See also Figure 10 As shown, in Figure 3 and Figure 4 In the illustrated embodiment, the solar cell manufacturing method further includes: S103 , forming a protective layer 160 on the barrier control layer 150 .

[0121] A protective layer 160 is formed on the barrier control layer 150. The thickness of the protective layer 160 is 0.1-200 nm. Figure 3 In the embodiment shown, the first electrode layer 171 can be formed on the protective layer 160 and the anti-reflection layer 190 by screen printing. Figure 4 In the illustrated embodiment, the first electrode layer 171 is formed on both the protective layer 160 on the side facing the first surface 111 and the protective layer 160 on the side facing the second surface 112 .

[0122] Figure 11 The solar cell manufacturing method provided in the embodiment of the present application Figure 3 .

[0123] See also Figure 11 As shown, in Figure 5 and Figure 8In the illustrated embodiment, before forming the barrier control layer 150 , the process further includes: S104 , forming a metal contact region 141 and a non-metal contact region 142 on the doped polysilicon layer 140 .

[0124] When forming the barrier control layer 150 , the doped polysilicon layer 140 where the second electrode layer 172 is not required can be etched away by mask etching to form a metal contact region 141 and a non-metal contact region 142 on the doped polysilicon layer 140 .

[0125] exist Figure 5 In the illustrated embodiment, the conductive carbon material layer 151 is formed on both the metal contact region 141 and the non-metal contact region 142 , and then the second electrode layer 172 is formed on the metal contact region 141 by screen printing.

[0126] exist Figure 8 In the illustrated embodiment, a conductive carbon material layer 151 is prepared on both the metal contact area 141 and the non-metal contact area 142 , a second passivation layer 152 is prepared on the conductive carbon material layer 151 , and then a second electrode layer 172 is prepared on the metal contact area 141 by screen printing.

[0127] The performance of the solar cell in the related art and the solar cell 100 provided in the embodiment of the present application were tested under the following test conditions: the air quality was 1.5, the light intensity was 1000W / m 2 , the temperature is 25℃. The open circuit voltage, short circuit current, fill factor and conversion efficiency are tested respectively.

[0128] Table 1 Figure 1a The solar cell shown in Figure 3 The performance comparison table of solar cells shown in Figure 1 is as follows. Figure 1a The parameters of the solar cell in Experiment 2 are Figure 3 Parameters of the solar cell 100 shown in FIG.

[0129] Table 1

[0130]

[0131] It can be seen that Figure 3 The open circuit voltage, fill factor and conversion efficiency of the solar cell 100 are higher than Figure 1a The solar cell shown, wherein Figure 3 The short-circuit current and Figure 1a The short-circuit current of the solar cell shown is flat.

[0132] Table 2 is Figure 1b The solar cell shown in Figure 4The performance comparison table of solar cells shown in Figure 2 is shown in Figure 3. Figure 1b The parameters of the solar cell in experiment 4 are Figure 4 Parameters of the solar cell 100 shown in FIG.

[0133] Table 2

[0134]

[0135] It can be seen that Figure 4 The open circuit voltage, fill factor and conversion efficiency of the solar cell 100 are higher than Figure 1b The solar cell shown, wherein Figure 4 The short-circuit current and Figure 1b The short-circuit current of the solar cell shown is flat.

[0136] Table 3 is Figure 2 The solar cell shown in Figure 8 The comparison table of solar cells shown in Figure 1 shows the comparison table of solar cells shown in Figure 2. Figure 2 The parameters of the solar cell in experiment six are Figure 8 Parameters of the solar cell 100 shown in FIG.

[0137] Table 3

[0138]

[0139] It can be seen that Figure 8 The open circuit voltage, fill factor and conversion efficiency of the solar cell 100 are higher than Figure 2 The solar cell shown, wherein Figure 5 The short-circuit current and Figure 2 The short-circuit current of the solar cell shown is flat.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A solar cell, characterized in that: include: A photoelectric conversion layer (100a), the photoelectric conversion layer (100a) comprising a first surface (111) and a second surface (112) opposite to each other; A tunneling oxide layer (130), a doped polysilicon layer (140) and a barrier control layer (150), wherein the tunneling oxide layer (130), the doped polysilicon layer (140) and the barrier control layer (150) are sequentially stacked on the first surface (111) and / or the second surface (112) in a direction away from the photoelectric conversion layer (100a).

2. The solar cell according to claim 1, wherein The solar cell (100) further comprises a protective layer (160), the barrier control layer (150) is located between the doped polysilicon layer (140) and the protective layer (160), and the barrier control layer (150) is used to isolate the protective layer (160) from the doped polysilicon layer (140).

3. The solar cell according to claim 2, wherein The solar cell (100) further comprises a first electrode layer (171), wherein the first electrode layer (171) is arranged on a side of the protective layer (160) facing away from the barrier control layer (150).

4. The solar cell according to claim 3, characterized in that The tunneling oxide layer (130), the doped polysilicon layer (140), the barrier control layer (150) and the protective layer (160) are located on the second surface (112) of the photoelectric conversion layer (100a); The solar cell (100) further comprises a first passivation layer (180) and an anti-reflection layer (190), wherein the first passivation layer (180) and the anti-reflection layer (190) are sequentially stacked on the first surface (111) in a direction away from the photoelectric conversion layer (100a), and the first electrode layer (171) is arranged on the anti-reflection layer (190).

5. The solar cell according to claim 3, wherein The tunneling oxide layer (130), the doped polysilicon layer (140) and the protective layer (160) are sequentially stacked on the first surface (111) and the second surface (112) of the photoelectric conversion layer (100a); and the barrier control layer (150) is provided between the doped polysilicon layer (140) and the protective layer (160) on the first surface (111); And / or, the barrier control layer (150) is provided between the doped polysilicon layer (140) and the protective layer (160) on the second surface (112).

6. The solar cell according to claim 1, wherein The doped polysilicon layer (140) comprises a metal contact region (141) and a non-metal contact region (142); a barrier control layer (150) is provided on each of the metal contact region (141) and the non-metal contact region (142); the barrier control layer (150) is used to enable conduction between the metal contact region (141) and the non-metal contact region (142).

7. The solar cell according to claim 6, characterized in that The invention also includes a second electrode layer (172), wherein the second electrode layer (172) is arranged on the metal contact area (141), and the second electrode layer (172) is electrically connected to the barrier control layer (150).

8. The solar cell according to any one of claims 1 to 7, characterized in that The thickness of the doped polysilicon layer (140) is less than or equal to 80 nm; And / or, the thickness of the barrier control layer (150) is less than or equal to 15 nm.

9. The solar cell according to claim 8, characterized in that The thickness of the doped polysilicon layer (140) is less than or equal to 30 nm and greater than or equal to 10 nm; And / or, the thickness of the barrier control layer (150) is less than or equal to 10 nm and greater than or equal to 0.1 nm.

10. The solar cell according to any one of claims 1 to 7, characterized in that The barrier regulating layer (150) includes a conductive carbon material layer (151).

11. The solar cell according to claim 6 or 7, characterized in that The barrier control layer (150) comprises a conductive carbon material layer (151) and a second passivation layer (152); the conductive carbon material layer (151) is arranged between the doped polysilicon layer (140) and the second passivation layer (152).

12. The solar cell according to claim 1, wherein The photoelectric conversion layer (100a) comprises a silicon substrate (110) and an emission layer (120), wherein the emission layer (120) faces the first surface (111), and the silicon substrate (110) faces the second surface (112).

13. A photovoltaic module, characterized in that: The invention comprises at least one solar cell (100) according to any one of claims 1 to 12, wherein the solar cell (100) is used for converting light energy of sunlight into electrical energy.

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