Solar cell and photovoltaic module

Abstract

The utility model relates to a solar cell and a photovoltaic module. The solar cell comprises a silicon substrate, a tunneling layer, a polycrystalline silicon layer, an insulating layer, a first conductive film layer, a first electrode, a second conductive film layer and a second electrode. The tunneling layer is arranged on the back surface of the silicon substrate; the polycrystalline silicon layer is arranged on the back surface of the tunneling layer, the polycrystalline silicon layer comprises a P-type doped region and an N-type doped region, the P-type doped region and the N-type doped region are arranged at an interval, an insulating groove is formed between the P-type doped region and the N-type doped region, and the insulating groove extends to the back surface of the silicon substrate from the back surface of the polycrystalline silicon layer; the insulating layer is arranged in the insulating groove; the first conductive film layer covers the back surface of the P-type doped region; the first electrode is arranged on the back of the first conductive film layer; the second conductive film layer covers the back surface of the N-type doped region; the second electrode is arranged on the back of the second conductive film layer. The insulating layer is arranged to realize electrical isolation of the P-type doped region and the N-type doped region, the first conductive film layer and the second conductive film layer are arranged to improve the filling factor and reduce the series resistance, and the efficiency of the solar cell is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Photovoltaic power generation is currently one of the primary ways to utilize solar energy. Due to its cleanliness, safety, convenience, and efficiency, solar photovoltaics are becoming the mainstream form of future new energy. As the industry chain continues to improve, the photovoltaic industry's biggest challenge is how to improve solar cell conversion efficiency while reducing manufacturing costs.

[0003] At present, TBC batteries with full back-electrode structures (Tunneling oxide passivated back contact batteries) are prone to short circuit leakage between the positive and negative electrodes. In addition, the full back-electrode structure batteries have gate lines arranged on one surface, which reduces the metal contact area. The series resistance caused by the direct contact of the metal gate lines with the polysilicon is large, resulting in low efficiency. Utility Model Content

[0004] Based on this, it is necessary to provide a solar cell and a photovoltaic module to solve at least one of the above problems.

[0005] The present application provides a solar cell, comprising:

[0006] Silicon substrate;

[0007] a tunneling layer, the tunneling layer being disposed on the back side of the silicon substrate;

[0008] a polysilicon layer, the polysilicon layer being disposed on a back side of the tunneling layer, the polysilicon layer comprising a P-type doping region and an N-type doping region, the P-type doping region and the N-type doping region being spaced apart, an insulating trench being formed between the P-type doping region and the N-type doping region, the insulating trench extending from a back side of the polysilicon layer to a back side of the silicon substrate;

[0009] an insulating layer, the insulating layer being disposed in the insulating groove;

[0010] a first conductive film layer, wherein the first conductive film layer covers the back surface of the P-type doped region;

[0011] a first electrode, the first electrode being disposed on the back side of the first conductive film layer;

[0012] a second conductive film layer, the second conductive film layer covering the back surface of the N-type doped region; and

[0013] The second electrode is arranged on the back side of the second conductive film layer.

[0014] In one embodiment, both the P-type doping region and the N-type doping region are doped with carbon.

[0015] In one embodiment, both the first conductive film layer and the second conductive film layer are TCO conductive films.

[0016] In one embodiment, the width of the insulating trench is 20 μm to 40 μm, and the insulating layer fills the insulating trench.

[0017] In one embodiment, the insulating groove is formed by a laser grooving process.

[0018] In one embodiment, the insulating layer is made of silicon oxide or silicon oxynitride.

[0019] In one embodiment, the tunneling layer is made of silicon oxide.

[0020] In one embodiment, one or more passivation layers are provided on the front surface of the silicon substrate.

[0021] In one embodiment, any one of the passivation layers is an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer.

[0022] In one embodiment, a direction in which one side of the back surface of the silicon substrate extends is defined as a first direction, and a direction perpendicular to the first direction on the back surface of the silicon substrate is defined as a second direction.

[0023] The first electrode includes a first horizontal gate line and a plurality of first vertical gate lines, wherein the first horizontal gate line extends along the first direction, the plurality of first vertical gate lines are arranged in a row along the first direction, and each of the first vertical gate lines extends along the second direction and has one end connected to the first horizontal gate line.

[0024] The second electrode includes a second horizontal gate line and a plurality of second vertical gate lines, wherein the second horizontal gate line extends along the second direction and is spaced apart from the first horizontal gate line. The plurality of second vertical gate lines are arranged in a row along the second direction, and each second vertical gate line extends along the second direction and has one end connected to the second horizontal gate line.

[0025] The plurality of first vertical grid lines and the plurality of second vertical grid lines are alternately and spaced apart in sequence along the second direction.

[0026] The present application also provides a photovoltaic assembly, comprising the above-mentioned solar cell.

[0027] Compared with the prior art, the solar cell and photovoltaic module provided by the present application can achieve electrical isolation of the P-type doped region and the N-type doped region by providing an insulating groove and an insulating layer within the insulating groove. At the same time, the first electrode can achieve ohmic contact with the P-type doped region through the first conductive film layer, and the second electrode can achieve ohmic contact with the N-type doped region through the second conductive film layer. Because the first conductive film layer can easily form good contact with the slurry used to prepare the first electrode, and the second conductive film layer can easily form good contact with the slurry used to prepare the second electrode, the fill factor of the solar cell can be improved and the series resistance can be reduced, thereby improving the efficiency of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic cross-sectional view of a solar cell according to an embodiment of the present application;

[0030] Figure 2 FIG. 1 is a schematic diagram of the back structure of a solar cell according to an embodiment of the present application.

[0031] Figure numerals: 10, silicon substrate; 11, first passivation layer; 12, second passivation layer; 20, tunneling layer; 30, polysilicon layer; 31, P-type doping region; 32, N-type doping region; 33, insulating groove; 50, insulating layer; 61, first conductive film layer; 62, second conductive film layer; 81, first electrode; 811, first horizontal gate line; 812, first vertical gate line; 82, second electrode; 821, second horizontal gate line; 822, second vertical gate line. DETAILED DESCRIPTION

[0032] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0033] It should be noted that when a component is referred to as being "fixed to" or "disposed on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may be a central component at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in the specification of this application are for illustrative purposes only and do not represent the only implementation method.

[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0035] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it can mean that the first feature is directly in contact with the second feature, or the first feature and the second feature are indirectly in contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it can mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is higher in level than the second feature. When a first feature is "below," "below," or "below" a second feature, it can mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is lower in level than the second feature.

[0036] Unless otherwise defined, all technical and scientific terms used in the specification of this application have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in the specification of this application includes any and all combinations of one or more of the relevant listed items.

[0037] See Figure 1The present application provides a solar cell, comprising: a silicon substrate 10, a tunneling layer 20, a polysilicon layer 30, an insulating layer 50, a first conductive film layer 61, a first electrode 81, a second conductive film layer 62, and a second electrode 82. The tunneling layer 20 is disposed on the back side of the silicon substrate 10. The polysilicon layer 30 is disposed on the back side of the tunneling layer 20. The polysilicon layer 30 includes a P-type doped region 31 and an N-type doped region 32. The P-type doped region 31 and the N-type doped region 32 are spaced apart, with an insulating trench 33 formed between the P-type doped region 31 and the N-type doped region 32. The insulating trench 33 extends from the back side of the polysilicon layer 30 to the back side of the silicon substrate 10; that is, the insulating trench 33 penetrates the polysilicon layer 30 and the tunneling layer 20. The insulating layer 50 is disposed within the insulating trench 33, thereby electrically isolating the P-type doped region 31 from the N-type doped region 32. The first conductive film layer 61 covers the back side of the P-type doped region 31. The first electrode 81 is disposed on the back side of the first conductive film layer 61. The second conductive film layer 62 covers the back side of the N-type doped region 32. The second electrode 82 is disposed on the back side of the second conductive film layer 62. Thus, by providing the insulating trench 33 and disposing the insulating layer 50 within the insulating trench 33, electrical isolation between the P-type doped region 31 and the N-type doped region 32 can be achieved. At the same time, the first electrode 81 can achieve ohmic contact with the P-type doped region 31 through the first conductive film layer 61, and the second electrode 82 can achieve ohmic contact with the N-type doped region 32 through the second conductive film layer 62. Because the first conductive film layer 61 easily forms good contact with the slurry used to prepare the first electrode 81, and the second conductive film layer 62 easily forms good contact with the slurry used to prepare the second electrode 82, the fill factor (FF) of the solar cell can be improved and the series resistance (Rs) can be reduced, thereby improving the efficiency of the solar cell. It can be understood that the first electrode 81 is a positive electrode and the second electrode 82 is a negative electrode.

[0038] It is understood that a solar cell has a front side and a back side, and when the solar cell is in operation, the front side faces the sun. The silicon substrate 10 is made of an N-type silicon wafer substrate. The tunneling layer 20 is made of silicon oxide. One or more passivation layers are provided on the front side of the silicon substrate 10. Any passivation layer is an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer. In this embodiment, two passivation layers are provided on the front side of the silicon substrate 10, namely a first passivation layer 11 and a second passivation layer 12, wherein the first passivation layer 11 is an aluminum oxide layer, and the second passivation layer 12 is a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer.

[0039] Furthermore, both the P-type doping region 31 and the N-type doping region 32 are doped with carbon. The presence of carbon can effectively suppress the crystallization fraction of the polysilicon layer 30, reduce stress accumulation during the crystallization process, and thus reduce parasitic absorption. In addition, by doping carbon, H can be essentially suppressed by forming C-H bonds. +The escape of carbon can also promote chemical passivation and enhance the passivation effect. In addition, doping with carbon elements can not only effectively eliminate film blistering, but also promote interface passivation and enhance the absorption of sunlight in the 300nm-700nm band (light absorption in the infrared band is significantly improved), achieving a 0.31mA / cm 2 The addition of carbon elements into the P-type doping region 31 and the N-type doping region 32 can also enhance the absorption of the long-wave 800nm-1200nm band and reduce the parasitic current on the back side, while avoiding insufficient stress and H + Overflow causes film bursting. Carbon doping can be accomplished by using a PECVD device with tubular doping, or by using a PVD device to introduce methane or other gases into the PAID chamber.

[0040] Metal electrodes are sintered on polysilicon, and the series resistance of the ohmic contacts formed between metal gate lines and between polysilicon and metal gate lines will be relatively large, and the composite resistance will also be slightly higher. This application covers the back of the P-type doped region 31 with a first conductive film layer 61, and covers the back of the N-type doped region 32 with a second conductive film layer 62. Furthermore, a first electrode 81 is provided on the back of the first conductive film layer 61, and a second electrode 82 is provided on the back of the second conductive film layer 62. The first conductive film layer 61 and the second conductive film layer 62 can collect carriers onto the first electrode 81 and the second electrode 82, thereby significantly reducing the series resistance.

[0041] Furthermore, the first conductive film layer 61 and the second conductive film layer 62 are both TCO conductive films. The TCO conductive film has good lateral resistivity, low absorption coefficient, and excellent thermal stability, which greatly helps in collecting current and conducting charges. Parasitic absorption can be further reduced by providing a TCO conductive film on the back of the polysilicon layer 30. Furthermore, the TCO conductive film can be a metal conductive film or an oxide film, such as indium tin oxide (ITO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), etc., and can also be a conductive polymer material, such as polythiophene and its derivatives, PEDOT-PSS (poly 3,4-ethylenedioxythiophene-polystyrene sulfonate), etc.

[0042] Furthermore, the width of the insulating trench 33 is 20 μm to 40 μm, and the insulating layer 50 completely fills the insulating trench 33. This ensures that the P-type doping region 31 and the N-type doping region 32 do not come into contact, thereby achieving electrical isolation between the P-type doping region 31 and the N-type doping region 32 while maximizing the utilization of the back surface of the silicon substrate 10, thereby improving the efficiency of the solar cell. Preferably, the width of the insulating trench 33 is 30 μm.

[0043] Furthermore, the insulating groove 33 is formed by a laser grooving process. The laser grooving process can accurately control the depth of the groove, so that the insulating groove 33 can be opened at a preset position without damaging the silicon substrate 10. Compared with the method of using alkali to corrode the silicon substrate 10 to obtain a velvet surface as an insulating spacer, this embodiment can avoid damage to the silicon substrate 10, thereby not affecting the mechanical load of the silicon substrate 10, and improving the product yield of the solar cell. At the same time, by providing an insulating layer 50 in the insulating groove 33, leakage is avoided, and insulation between the P-type doping region 31 and the N-type doping region 32 is ensured. Furthermore, the material of the insulating layer 50 is silicon oxide or silicon oxynitride, which has a good insulating effect.

[0044] See Figure 2 , defining the direction in which one side of the back surface of the silicon substrate 10 extends as a first direction A, and defining the direction perpendicular to the first direction on the back surface of the silicon substrate 10 as a second direction B. The first electrode 81 includes a first horizontal gate line 811 and a plurality of first vertical gate lines 812. The first horizontal gate line 811 extends along the first direction. The plurality of first vertical gate lines 812 are arranged in a row along the first direction. Each first vertical gate line 812 extends along the second direction and has one end connected to the first horizontal gate line 811. The second electrode 82 includes a second horizontal gate line 821 and a plurality of second vertical gate lines 822. The second horizontal gate line 821 extends along the second direction and is spaced apart from the first horizontal gate line 811. The plurality of second vertical gate lines 822 are arranged in a row along the second direction. Each second vertical gate line 822 extends along the second direction and has one end connected to the second horizontal gate line 821. The plurality of first vertical gate lines 812 and the plurality of second vertical gate lines 822 are alternately and spaced apart along the second direction. In this way, the carriers collected by the first conductive film layer 61 are transferred to the first horizontal grid line 811 and the plurality of first vertical grid lines 812. The plurality of first vertical grid lines 812 then collect the carriers to the first horizontal grid line 811, which then outputs the carriers. Similarly, the carriers collected by the second conductive film layer 62 are transferred to the second horizontal grid line 821 and the plurality of second vertical grid lines 822. The plurality of second vertical grid lines 822 then collect the carriers to the second horizontal grid line 821, which then outputs the carriers. This arrangement of the first and second electrodes 81, 82 fully utilizes the space on the back side of the silicon substrate 10, thereby improving the efficiency of the solar cell.

[0045] Please combine Figure 1 The solar cell processing method of the present application comprises the following steps:

[0046] S1: Using a texturing machine, the original silicon wafer is cleaned and impurities are removed, and texturing is performed to form a double-sided pyramid structure, thereby obtaining a silicon substrate 10.

[0047] S2: polishing one side of the silicon substrate 10 to form a tower base, which serves as the back side of the silicon substrate 10.

[0048] S3: A tunneling layer 20 is formed on the back side of the silicon substrate 10 by using a tube-type or plate-type machine. The material of the tunneling layer 20 is silicon oxide. Then, silane, hydrogen, and methane are used to produce an intrinsic silicon layer.

[0049] S4: Using a laser, the structure on the back of the intrinsic silicon layer is patterned to create an isolation region, serving as an insulation trench 33 separating the P-type doped region 31 from the N-type doped region 32. Specifically, the back of the intrinsic silicon layer is completely protected with paraffin wax. Lasers are then used to penetrate the intrinsic silicon layer and tunneling layer 20 to the back of the silicon substrate 10, forming insulation trench 33. Silane and nitrous oxide are then introduced into insulation trench 33 to form silicon oxide or silicon oxynitride, serving as the insulation layer 50.

[0050] S5: sequentially preparing a first passivation layer 11 and a second passivation layer 12 on the front surface of the silicon substrate 10, wherein the first passivation layer 11 is an aluminum oxide layer, and the second passivation layer 12 is a silicon nitride layer, a silicon oxynitride layer, or a silicon oxide layer.

[0051] S6: Use wet equipment to clean the paraffin on the back of the intrinsic silicon layer to restore the intrinsic silicon layer structure, and then use a printing machine to cross-print boron-containing coatings and phosphorus-containing coatings on the laser-grooved pattern.

[0052] S7: Entering the annealing equipment to activate the amorphous silicon of the intrinsic silicon layer to the polysilicon state, so that the area printed with the boron-containing coating forms a P-type doping area 31, and the area printed with the phosphorus-containing coating forms an N-type doping area 32.

[0053] S8: Covering the P-type doping region 31 with a first conductive film layer 61 and covering the N-type doping region 32 with a second conductive film layer 62. Both the first conductive film layer 61 and the second conductive film layer 62 are TCO conductive films, and no film is formed on the insulating layer 50.

[0054] S9 : printing a positive electrode paste on the first conductive film layer 61 to form a first electrode 81 , and printing a negative electrode paste on the second conductive film layer 62 to form a second electrode 82 .

[0055] The present application also provides a photovoltaic assembly, comprising the above-mentioned solar cell.

[0056] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0057] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of patent protection for the present application shall be determined by the appended claims.

Claims

1. A solar cell, characterized in that: include: Silicon substrate; a tunneling layer, the tunneling layer being disposed on the back side of the silicon substrate; a polysilicon layer, the polysilicon layer being disposed on a back side of the tunneling layer, the polysilicon layer comprising a P-type doping region and an N-type doping region, the P-type doping region and the N-type doping region being spaced apart, an insulating trench being formed between the P-type doping region and the N-type doping region, the insulating trench extending from a back side of the polysilicon layer to a back side of the silicon substrate; an insulating layer, the insulating layer being disposed in the insulating groove; a first conductive film layer, wherein the first conductive film layer covers the back surface of the P-type doped region; a first electrode, the first electrode being disposed on the back side of the first conductive film layer; a second conductive film layer, wherein the second conductive film layer covers the back surface of the N-type doped region; as well as The second electrode is arranged on the back side of the second conductive film layer.

2. The solar cell according to claim 1, wherein The P-type doping region and the N-type doping region are both doped with carbon elements.

3. The solar cell according to claim 1, wherein The first conductive film layer and the second conductive film layer are both TCO conductive films.

4. The solar cell according to claim 1, wherein The width of the insulating groove is 20 μm to 40 μm, and the insulating layer fills the insulating groove.

5. The solar cell according to claim 1, wherein The insulating groove is formed by laser grooving process.

6. The solar cell according to claim 1, wherein The insulating layer is made of silicon oxide or silicon oxynitride.

7. The solar cell according to claim 1, wherein The tunneling layer is made of silicon oxide.

8. The solar cell according to claim 1, wherein The front surface of the silicon substrate is provided with one or more passivation layers.

9. The solar cell according to claim 8, characterized in that Any of the passivation layers is an aluminum oxide layer, a silicon nitride layer, a silicon oxynitride layer or a silicon oxide layer.

10. The solar cell according to claim 1, wherein The direction in which one side of the back surface of the silicon substrate extends is defined as a first direction, and the direction perpendicular to the first direction on the back surface of the silicon substrate is defined as a second direction. The first electrode includes a first horizontal gate line and a plurality of first vertical gate lines, wherein the first horizontal gate line extends along the first direction, the plurality of first vertical gate lines are arranged in a row along the first direction, and each of the first vertical gate lines extends along the second direction and has one end connected to the first horizontal gate line. The second electrode includes a second horizontal gate line and a plurality of second vertical gate lines, wherein the second horizontal gate line extends along the second direction and is spaced apart from the first horizontal gate line. The plurality of second vertical gate lines are arranged in a row along the second direction, and each second vertical gate line extends along the second direction and has one end connected to the second horizontal gate line. The plurality of first vertical grid lines and the plurality of second vertical grid lines are alternately and spaced apart in sequence along the second direction.

11. A photovoltaic module, characterized in that: The solar cell comprises the solar cell according to any one of claims 1 to 10.

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