Air conditioner
Patent Information
- Application Number
- CN202422326613.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2034-09-23
Smart Images
Figure CN223376016U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of air conditioners, and in particular relates to an air conditioner. Background Art
[0002] The transmission signal in digital signal transmission is also called the AMI (Alternate Mark Inversion) coded signal (hereinafter referred to as the AMI signal). The AMI signal is used and output in the HBS (Home-Bus System). It is composed of three values: zero, positive, and negative. It passes through the positive signal line and the negative signal line, forming a set of detection signals between the two signal lines, which is the AMI bus communication signal.
[0003] In the communication method using the above signal, a logic "1" is assigned to zero level, and a logic "0" is assigned to alternating positive or negative levels. Currently, the HBS communication protocol is primarily used for communication between indoor and outdoor units and wired controllers in multi-split air conditioning systems. It offers advantages such as polarity-neutral transmission, long transmission distances, and strong anti-interference capabilities. The HBS communication chip used in this protocol is the MM1192 communication chip manufactured by Sanmei Electrode.
[0004] The HBS interface of the MM1192 communication chip transmits a communication signal with a 50% duty cycle, but the main chip can only receive communication signals with a 100% duty cycle. As a result, when the MM1192 communication chip communicates with the main chip, the main chip cannot correctly recognize the communication signal with a 50% duty cycle, resulting in communication failure. Therefore, how to ensure the communication between the MM1192 communication chip and the main chip is crucial to the normal communication of the multi-split air conditioning system.
[0005] The above information disclosed in this background technology is only used to increase the understanding of the background technology of this application. Therefore, it may contain information that does not constitute the prior art known to ordinary technicians in this field. Utility Model Content
[0006] By setting up a modulation circuit, the present application does not require the internal program processing of the main chip to send a logical signal of the AMI coding rule that the communication chip can recognize, so that the communication signal sent by the main chip can be normally recognized by the communication chip.
[0007] The present application provides an air conditioner, which includes:
[0008] A main chip, which is used to output a binary signal;
[0009] A communication chip for receiving an alternately inverted signal;
[0010] The modulation circuit is located between the main chip and the communication chip. The modulation circuit is used to convert the binary signal into an alternating inverted signal. The modulation circuit includes:
[0011] A first switch control circuit, whose control terminal is connected to the first output terminal of the main chip, for controlling the on and off of the first switch control circuit;
[0012] A second switch control circuit, whose control end is connected to the second output end of the main chip, for controlling the on and off of the second switch control circuit;
[0013] a charge and discharge circuit, wherein an input end thereof is connected to an output end of the first switch control circuit and an output end of the second switch control circuit;
[0014] The third switch control circuit has a control end connected to the output end of the charge and discharge circuit, the output end of the first switch control circuit, and the output end of the second switch control circuit to control the on and off of the third switch control circuit. The output end of the third switch control circuit is connected to the input end of the communication chip.
[0015] In the above embodiment, the signals output from the first output terminal and the second output terminal of the main chip are synthesized by the debugging circuit through logical sum operation of the communication clock SCK sent by the main chip and the communication data TXD signal sent, thereby generating an output signal in which the communication chip can recognize that the logic "0" is a signal with a duty cycle of 50% alternating between 0 and 1 and a logic "1" can be recognized as a 100% high level. The output signals are input into the receiving port of the communication chip to realize normal communication between the main chip and the MM1192 chip.
[0016] In some embodiments, the charge-discharge circuit further includes a first resistor and a first capacitor, wherein a first end of the first resistor is connected to a power supply, and a second end of the first resistor is connected to an output end of the first switch control circuit; a first end of the first capacitor is connected to the output end of the first switch control circuit, and a second end of the first capacitor is grounded.
[0017] In the above embodiment, the first resistor can also serve as a pull-up resistor for the first switch control circuit and the second switch control circuit.
[0018] In some embodiments, the modulation circuit further includes a filtering circuit, which is disposed between the output end of the third switch control circuit and the input end of the communication chip, and is used to filter the electrical signal output by the third switch control circuit and output it to the communication chip.
[0019] In some embodiments, the filter circuit is configured as an RC filter circuit, specifically including a second resistor and a second capacitor, the second resistor and the second capacitor being connected in series. A first end of the second resistor is connected to an output terminal of the third switch control circuit, and a second end of the second resistor is connected to an input terminal of the communication chip. A first end of the second capacitor is connected to a second end of the second resistor, and the second end of the second capacitor is grounded.
[0020] In some embodiments, the modulation circuit further includes a pull-up resistor, a first end of the pull-up resistor is connected to a power supply, and a second end of the pull-up resistor is connected to an output end of the third switch control circuit.
[0021] In some embodiments, the first switch control circuit includes a first transistor, whose base is connected to the first output terminal of the main chip, whose emitter is grounded, and whose collector is connected to the control terminal of the third switch control circuit.
[0022] In some embodiments, the second switch control circuit includes a second transistor, whose base is connected to the second output terminal of the main chip, whose emitter is grounded, and whose collector is connected to the control terminal of the third switch control circuit.
[0023] In some embodiments, the third switch control circuit includes a third transistor, whose base is connected to the output terminal of the charge and discharge circuit, the collector of the first transistor, and the collector of the second transistor, whose emitter is grounded, and whose collector is connected to the input terminal of the communication chip.
[0024] In some embodiments, the power supply provides DC power to the charging and discharging circuit, the first switch control circuit, the second switch control circuit, and the third switch control circuit respectively.
[0025] In this application, a modulation circuit is also proposed for converting the binary signal output by the receiving main chip and outputting it to the communication chip. The modulation circuit includes:
[0026] A first switch control circuit, whose control terminal is connected to the first output terminal of the main chip, for controlling the on and off of the first switch control circuit;
[0027] A second switch control circuit, whose control end is connected to the second output end of the main chip, for controlling the on and off of the second switch control circuit;
[0028] a charge and discharge circuit, wherein an input end thereof is connected to an output end of the first switch control circuit and an output end of the second switch control circuit;
[0029] The third switch control circuit has a control end connected to the output end of the charge and discharge circuit, the output end of the first switch control circuit, and the output end of the second switch control circuit to control the on and off of the third switch control circuit. The output end of the third switch control circuit is connected to the input end of the communication chip.
[0030] Compared to related technologies, the modulation circuit in this embodiment receives a binary signal output by the main chip, converts it into a signal with a 50% duty cycle, alternating between 0s and 1s, and a 100% duty cycle, and transmits it to the communication chip. The communication chip then converts this signal into an AMI signal for transmission on the bus. This ensures that the binary signal from the main chip is correctly transmitted from the main chip to the communication chip, where it is converted into an AMI signal and transmitted on the bus. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0032] Figure 1 is a hardware configuration diagram of an air conditioner in one embodiment of the present disclosure;
[0033] Figure 2 This is a schematic diagram of the connections among the modulation circuit, the main chip, and the communication chip in one embodiment of the present disclosure;
[0034] Figure 3 is a hardware configuration diagram of a modulation circuit in one embodiment of the present disclosure;
[0035] Figure 4 is a circuit diagram of a modulation circuit in one embodiment of the present disclosure;
[0036] Figure 5 is another hardware configuration diagram of a modulation circuit in one embodiment of the present disclosure;
[0037] Figure 6 is another circuit diagram of a modulation circuit in one embodiment of the present disclosure;
[0038] Figure 7 The waveforms of the data signal sent by the main chip, the clock signal sent by the main chip, the signal waveform received by the communication chip after the modulated signal, and the AMI signal on the communication chip bus in one embodiment of the present disclosure are shown below:
[0039] Figure 8 is a signal transmission schematic diagram of a modulation circuit in one embodiment of the present disclosure;
[0040] In the above picture:
[0041] Wire controller 1; controller 2; main chip 21; communication chip 22; modulation circuit 23; bus 25;
[0042] First switch control circuit 231; second switch control circuit 232; charge and discharge circuit 233;
[0043] The third switch control circuit 234; the first resistor R1; the first capacitor C1; the filter circuit 24; the pull-up resistor R2;
[0044] A second resistor R3; a second capacitor C2; a first transistor Q1; a second transistor Q2;
[0045] The third transistor Q3. DETAILED DESCRIPTION
[0046] The following will be combined with the accompanying drawings of the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.
[0047] In the description of the present invention, it should be understood that the terms "center", "lateral", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0048] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this utility model based on the specific circumstances.
[0049] This application proposes an air conditioner. The air conditioner includes an indoor unit. The indoor unit includes an indoor housing. The indoor housing is used to form the outer contour of the indoor unit and accommodate internal components of the indoor unit.
[0050] An air conditioner includes an outdoor unit. The outdoor unit is installed outdoors and includes an outdoor housing. The outdoor housing forms the exterior of the outdoor unit and houses its internal components.
[0051] The outdoor unit and the indoor unit are connected by pipes for the flow of refrigerant.
[0052] In some embodiments, the indoor unit and the outdoor unit are connected wirelessly. For example, the indoor unit and the outdoor unit use radio frequency communication or infrared communication.
[0053] In some embodiments, the indoor and outdoor units communicate via a wired connection. In some embodiments, the indoor and outdoor units communicate via an RS485 bus. In some embodiments, the indoor and outdoor units communicate using an HBS bus to achieve stable and efficient data transmission between the indoor and outdoor units.
[0054] The indoor unit includes an electrical box. The electrical box is arranged on one side of the indoor housing. In some embodiments, the electrical box is arranged on one side of the outdoor housing.
[0055] The air conditioner includes a control board, which is responsible for processing the used commands and the air conditioner control logic operations.
[0056] In some embodiments, the control board is mounted in an electrical box.
[0057] Reference Figure 1 The air conditioner includes a wired controller. The wired controller receives user commands and sends them to the air conditioner's control panel via a specific protocol. The control panel then controls the various components.
[0058] In some embodiments, the air conditioner includes a main chip. The main chip can output a binary signal. It should be noted that the binary signal means that logic "0" is 100% zero level and logic "1" is 100% high level.
[0059] In some embodiments, the main chip includes a first output terminal configured to output a communication data TXD signal.
[0060] In some embodiments, the master chip includes a second output terminal configured to output a communication clock SCK signal.
[0061] An example of a digital signal transmission signal is the AMI (Alternate Mark Inversion) coded signal (hereinafter referred to as the AMI signal). When used and output in a home-bus system (HBS), the AMI signal is composed of three values: zero, positive, and negative. These values pass through both the positive and negative signal lines, forming a differential signal between the two lines. This differential signal is known as the AMI bus communication signal.
[0062] In the communication method using this signal, a logic "1" is assigned to a zero level, and a logic "0" is assigned to alternating positive or negative levels. In this disclosure, the HBS communication protocol is primarily used for communication between indoor and outdoor units and wired controllers in an air conditioning system. This protocol offers advantages such as polarity-neutral transmission, long transmission distance, and strong anti-interference capabilities.
[0063] In some embodiments of the present disclosure, the HBS communication protocol uses an HBS communication chip, which is the MM1192 communication chip produced by Mitsumi Electric.
[0064] In some embodiments, the communication chip cannot directly recognize the signal output by the main chip. The communication chip can recognize an alternating inverted signal. In some embodiments, the communication chip can recognize a signal with a duty cycle of 50% alternating between 0 and 1.
[0065] In some embodiments, the communication chip can recognize a 100% high level output signal.
[0066] In order to ensure that the output signal of the main chip can be correctly recognized by the communication chip. Figure 2 The present disclosure relates to a modulation circuit, which is located between a main chip and a communication chip.
[0067] The modulation circuit receives the binary signal output by the main chip and converts it into a corresponding alternating inverted signal or a 100% high-level signal, and transmits the converted signal to the communication chip.
[0068] The modulation circuit may further include a power supply, which is used to provide power to each circuit in the modulation circuit.
[0069] In some embodiments, reference Figure 3 The modulation circuit includes a first switch control circuit. The control terminal of the first switch control circuit is connected to the first output terminal of the main chip. The control circuit receives an output signal from the first output terminal to control the on / off state of the first switch control circuit. The on / off state of the first switch control circuit is controlled by receiving a TXD signal output from the first output terminal.
[0070] In some embodiments, the modulation circuit includes a second switch control circuit. The control terminal of the second switch control circuit is connected to the second output terminal of the master chip. The output signal of the second output terminal is received to control the on / off of the second switch control circuit. The on / off of the second switch control circuit is controlled by receiving the SCK signal output by the second output terminal.
[0071] In some embodiments, the modulation circuit includes a charge-discharge circuit, wherein an input terminal of the charge-discharge circuit is connected to an output terminal of the first switch control circuit and an output terminal of the second switch control circuit.
[0072] The main function of the charge and discharge circuit is to control the amplitude change of the signal, thereby realizing the modulation process of the signal.
[0073] In some embodiments, the modulation circuit includes a third switch control circuit. The control end of the third switch control circuit is connected to the output end of the charge and discharge circuit, the output end of the first switch control circuit, and the output end of the second switch control circuit. The control end receives three signals for controlling the on and off of the third switch control circuit. The output end of the third switch control circuit is connected to the input end of the communication chip.
[0074] The third switch control circuit is controlled to be on and off by the composite signal output by the first switch control circuit, the second switch control circuit and the charge and discharge circuit. The signal output by the output end of the third switch control circuit is a signal that can be recognized by the communication chip.
[0075] In the above embodiment, the signals output from the first output terminal and the second output terminal of the main chip are synthesized by the debugging circuit through logical sum operation of the communication clock SCK sent by the main chip and the communication data TXD signal sent, thereby generating an output signal in which the communication chip can recognize that the logic "0" is a signal with a duty cycle of 50% alternating between 0 and 1 and a logic "1" can be recognized as a 100% high level. The output signals are input into the receiving port of the communication chip to realize normal communication between the main chip and the MM1192 chip.
[0076] After receiving the converted signal, the communication chip converts it into an AMI signal and transmits it on the bus. This is the process of correctly transmitting the binary signal from the main chip to the communication chip, converting it into an AMI signal, and transmitting it on the bus.
[0077] In this application, there is no need for the internal program processing of the main chip to send out a logic signal of the AMI coding rule that can be recognized by the communication chip, so that the communication signal sent by the main chip can be correctly recognized by the communication chip.
[0078] The main chip in the present disclosure can be provided in an indoor unit. A communication chip can be provided in the indoor unit. Signals are transmitted between the main chip and the communication chip to enable the main chip to send instructions to other components via the communication chip. For example, the main chip sends instructions to sensors via the communication chip.
[0079] It should be noted that the modulation circuit in this application can be used in the signal transmission process between the control board and the sensor in the indoor unit, and can also be used in the signal transmission process between the indoor unit and the outdoor unit. It can also be used in the signal transmission process between the control board and the sensor in the outdoor unit.
[0080] In some embodiments, the power supply provides DC power to the charge and discharge circuit, the first switch control circuit, the second switch control circuit, and the third switch control circuit. In some embodiments, the DC power supply is set to 5V.
[0081] In some embodiments, reference Figure 4The charge-discharge circuit further includes a first resistor and a first capacitor. A first end of the first resistor is connected to the power supply, and a second end of the first resistor is connected to the output of the first switch control circuit. A first end of the first capacitor is connected to the output of the first switch control circuit, and a second end of the first capacitor is grounded.
[0082] The role of the charge and discharge circuit in the modulation circuit is to indirectly affect the amplitude, frequency or phase of the carrier signal by controlling the charging and discharging process of the capacitor, thereby realizing information modulation.
[0083] In the above embodiment, the first resistor can also serve as a pull-up resistor for the first and second switch control circuits to ensure the stability of the emitter output signal, reduce voltage variations caused by power supply fluctuations or circuit noise, and thus improve the circuit's anti-interference capability.
[0084] In some embodiments, reference Figure 5 The modulation circuit also includes a filter circuit, disposed between the output of the third switch control circuit and the input of the communication chip, for filtering the electrical signal output by the third switch control circuit before outputting it to the communication chip. The filter circuit stabilizes the DC operating point of the transistor and suppresses high-frequency noise.
[0085] In some embodiments, reference Figure 6 , the filter circuit is configured as an RC filter circuit, specifically comprising a second resistor and a second capacitor, the second resistor and the second capacitor being connected in series. The first end of the second resistor is connected to the output end of the third switch control circuit, and the second end of the second resistor is connected to the input end of the communication chip. The first end of the second capacitor is connected to the second end of the second resistor, and the second end of the second capacitor is grounded. In some embodiments, referring to Figure 6 , the input end of the communication chip is set as the sixth pin signal receiving port.
[0086] In some embodiments, reference Figure 6 The modulation circuit further includes a pull-up resistor, a first end of which is connected to a power supply, and a second end of which is connected to the output terminal of the third switch control circuit. This ensures the stability of the output signal of the third switch control circuit and reduces voltage variations caused by power supply fluctuations or circuit noise, thereby improving the circuit's anti-interference capability.
[0087] In some embodiments, reference Figure 4 The first switch control circuit includes a first transistor, whose base is connected to the first output terminal of the main chip, whose emitter is grounded, and whose collector is connected to the control terminal of the third switch control circuit.
[0088] In some embodiments, the first transistor is configured as an NPN transistor.
[0089] In some embodiments, the second switch control circuit includes a second transistor, whose base is connected to the second output terminal of the main chip, whose emitter is grounded, and whose collector is connected to the control terminal of the third switch control circuit.
[0090] In some embodiments, the second transistor is configured as an NPN transistor.
[0091] In some embodiments, the third switch control circuit includes a third transistor. Its base is connected to the output of the charge-discharge circuit, the collector of the first transistor, and the collector of the second transistor. Its emitter is grounded, and its collector is connected to the input of the communication chip. In some embodiments, the third transistor is an NPN transistor.
[0092] In some embodiments, the logical operation relationship between the first transistor and the second transistor is: (communication clock)*(communication data), and then the third transistor is used to implement logical NOT.
[0093] According to Demo The root theorem is valid for the following operation: (communication clock) * (communication data) = (communication clock) + (communication data)
[0094] R1 is the pull-up resistor for Q1 and Q2, and R2 is the pull-up resistor for Q3. When the collectors of Q1 and Q2 become high, the base potential of Q3 becomes high.
[0095] In some embodiments, the power supply provides DC power to the charging and discharging circuit, the first switch control circuit, the second switch control circuit, and the third switch control circuit respectively.
[0096] The modulation circuit realizes the signal conversion function, and the communication data TXD signal and the communication clock SCK signal output from the main chip realize logical sum operation through the combination of transistors.
[0097] Reference Figure 7 When the communication data TXD signal is at level "0", when the communication clock signal is at level "1", the converted signal has a high pulse width of 50%. When the communication data TXD signal is at level "1", it is not affected by the communication clock SCK signal.
[0098] In the present application, a modulation circuit is also proposed for converting the binary signal output by the receiving main chip and outputting it to the communication chip.
[0099] The modulation circuit includes a first switch control circuit, a control end of which is connected to the first output end of the main chip, and is used to control the on and off of the first switch control circuit by receiving an output signal from the first output end;
[0100] In some embodiments, the modulation circuit includes a second switch control circuit, a control terminal of which is connected to the second output terminal of the main chip, and is used to control the on and off of the second switch control circuit by receiving an output signal from the second output terminal;
[0101] In some embodiments, the modulation circuit includes a charge-discharge circuit having an input connected to an output of the first switch control circuit and an output of the second switch control circuit;
[0102] In some embodiments, the modulation circuit includes a third switch control circuit, whose control end is connected to the output end of the charge and discharge circuit, the output end of the first switch control circuit, and the output end of the second switch control circuit. The third switch control circuit is controlled to be on and off by receiving a combined signal of the three signals, and the output end of the third switch control circuit is connected to the input end of the communication chip.
[0103] Compared with related technologies, Figure 8 In this embodiment, the modulation circuit receives the binary signal output by the main chip and converts it into a signal with a 50% duty cycle, alternating between 0s and 1s, and a 100% duty cycle, logically representing "1." The signal is then transmitted to the communication chip. The communication chip internally converts this signal into an AMI signal for transmission on the bus. This ensures that the binary signal from the main chip is correctly transmitted from the main chip to the communication chip, where it is converted into an AMI signal and transmitted on the bus.
[0104] In some embodiments of the present disclosure, using the MM1192 communication chip as an example, the MM1192 typically uses a 9600Hz communication frequency. The master chip's TXD signal also uses a 9600Hz frequency, meaning a communication cycle T0 = 1 / 9600, or approximately 104µs. The communication clock SCK signal requires a double frequency, i.e., a 19200Hz frequency, resulting in a 52µs communication cycle.
[0105] Reference Figure 7 , the period of transmitting one bit is T1. The modulation circuit is used to convert the signal (001) output by the main chip into a signal that can be recognized by the communication chip.
[0106] When the communication data TXD signal is at "0" level, when the communication clock SCK signal of the main chip is at logic "1", the output is a "1" signal. When the communication clock SCK signal is at logic "0", the output is a "0" signal.
[0107] When the communication data signal is at "1" level, it is not affected by the communication clock signal.
[0108] The following describes how to calculate the time t, taking VCC1 as 5V, R1 as 1k resistor, and C1 as 0.022uF as an example.
[0109] When the SCK signal or TXD signal is high, I1 = 5V / 1KΩ, and the capacitor discharge formula is I1*Δt = C*ΔU. It can be calculated that Δt = 4us.
[0110] When the SCK signal or the TXD signal is at a low level at the same time, 5V charges the first capacitor C1 through the first resistor R1, and the charging time constant T=RC.
[0111] Von = 5 * (1-e^(1-(-t / τ)), where τ is the time constant of R1 and C1; Von is the turn-on voltage of the third transistor Q3; e is the natural logarithm, and t is the charging time in seconds.
[0112] When the voltage across the first capacitor C1 reaches Von=0.7V or above, the third transistor Q3 is turned on. The charging time t=3.3us can be calculated.
[0113] The modulation circuit in the embodiment of the present disclosure receives the binary signal output by the main chip and converts it into a signal and sends it to the communication chip, so that the binary signal emitted by the main chip is correctly transmitted from the main chip to the MM1192 communication chip, and the main chip and the MM1192 communication chip can communicate normally.
[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
[0115] For ease of explanation, the above description has been presented in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations are possible. The above embodiments have been selected and described to better explain the principles and practical applications, thereby enabling those skilled in the art to better utilize the embodiments and various variations of the embodiments suitable for specific use considerations.
Claims
1. An air conditioner, characterized in that: include: An indoor housing, which is used to form the outer contour of the indoor unit; An electrical box, which is arranged inside the indoor housing; A main chip, which is arranged in the electrical box and is used to output a binary signal; A communication chip, which is disposed in the electrical box and is used to receive the alternately inverted signal; A modulation circuit is provided between the main chip and the communication chip. The modulation circuit is used to convert the binary signal into an alternating inverted signal or a 100% high-level signal. The modulation circuit includes: a first switch control circuit, whose control end is connected to the first output end of the main chip, so as to control the on and off of the first switch control circuit; a second switch control circuit, whose control end is connected to the second output end of the main chip, so as to control the on and off of the second switch control circuit; a charge and discharge circuit, an input end of which is connected to the output end of the first switch control circuit and the output end of the second switch control circuit; A third switch control circuit, whose control end is connected to the output end of the charge and discharge circuit, the output end of the first switch control circuit and the output end of the second switch control circuit, so as to control the on and off of the third switch control circuit, and the output end of the third switch control circuit is connected to the input end of the communication chip.
2. The air conditioner according to claim 1, characterized in that The charge and discharge circuit further includes: a first resistor, a first end of which is connected to a power supply, and a second end of which is connected to an output end of the first switch control circuit; A first capacitor has a first end connected to the output end of the first switch control circuit and a second end grounded.
3. The air conditioner according to claim 1, characterized in that Also includes: The filter circuit is provided between the output end of the third switch control circuit and the input end of the communication chip, and is used for filtering the electrical signal output by the third switch control circuit before outputting it to the communication chip.
4. The air conditioner according to claim 3, characterized in that The filtering circuit comprises: a second resistor, a first end of which is connected to the output end of the third switch control circuit, and a second end of which is connected to the input end of the communication chip; A second capacitor has a first end connected to the second end of the second resistor and a second end grounded.
5. The air conditioner according to claim 1, characterized in that A pull-up resistor is also included, wherein a first end of the pull-up resistor is connected to a power supply, and a second end of the pull-up resistor is connected to an output end of the third switch control circuit.
6. The air conditioner according to claim 1, characterized in that The first switch control circuit includes: The first transistor has a base connected to the first output terminal of the main chip, an emitter connected to the ground, and a collector connected to the control terminal of the third switch control circuit.
7. The air conditioner according to claim 6, characterized in that The second switch control circuit includes: The second triode has a base connected to the second output terminal of the main chip, an emitter connected to the ground, and a collector connected to the control terminal of the third switch control circuit.
8. The air conditioner according to claim 7, characterized in that The third switch control circuit includes: The third transistor has a base connected to the output end of the charge and discharge circuit, an emitter connected to the ground, and a collector connected to the input end of the communication chip.
9. The air conditioner according to claim 1, wherein: The power supply provides DC power to the charging and discharging circuit, the first switch control circuit, the second switch control circuit and the third switch control circuit respectively.
10. An air conditioner, characterized in that: It includes a modulation circuit, which is used to convert the binary signal output by the receiving main chip and output it to the communication chip. The modulation circuit includes: a first switch control circuit, whose control end is connected to the first output end of the main chip, so as to control the on and off of the first switch control circuit; a second switch control circuit, whose control end is connected to the second output end of the main chip, so as to control the on and off of the second switch control circuit; a charge and discharge circuit, an input end of which is connected to the output end of the first switch control circuit and the output end of the second switch control circuit; A third switch control circuit, whose control end is connected to the output end of the charge and discharge circuit, the output end of the first switch control circuit and the output end of the second switch control circuit, so as to control the on and off of the third switch control circuit, and the output end of the third switch control circuit is connected to the input end of the communication chip.