Digital synchronous verification relay

Abstract

The utility model relates to the technical field of power generation grid-connected systems, in particular to a digital synchronous verification relay, which comprises a master control CPU (central processing unit), an A / D (analog / digital) sampling circuit, a power supply circuit, a key acquisition circuit, a nixie tube display circuit and a relay execution circuit which are mounted in a shell, wherein the output ends of the A / D sampling circuit and the key acquisition circuit are electrically connected with the input end of the main control CPU, and the output end of the main control CPU is electrically connected with the nixie tube display circuit and the relay execution circuit; according to the utility model, the digital synchronous verification relay and the synchronizing device are interlocked, so that the intrinsic safety performance of equipment is improved, the stable access between the generator and the electric power system is ensured, and the safe and reliable synchronous grid-connected mode can effectively avoid the occurrence of unplanned shutdown events, so that the safety of the equipment is improved. The safe and stable operation of the generator set is ensured, and the generating capacity of a power plant is guaranteed.

Description

Technical Field

[0001] The utility model relates to the technical field of power generation grid-connected systems, in particular to a digital synchronous verification relay. Background Art

[0002] In the power generation process of the electric power industry, generator grid connection is crucial for ensuring power system stability, operational safety, and flexibility. As a core component of the grid connection process, the promotion and application of reliability enhancement technologies for synchronization systems are crucial for improving the overall performance of power systems. Currently, a common configuration in power plant grid-connected power systems is the combination of synchronization devices and mechanical synchronization check relays, as exemplified by the automatic synchronization system and method for power plant grid connection disclosed in Chinese Patent Publication No. "CN107134809B."

[0003] However, this widely used traditional integration approach presents several practical challenges. First, due to limitations in structural design and processing capabilities, traditional synchronization check relays can easily fail to operate or malfunction if a fault occurs, impacting the stability and security of the entire power grid. Second, their mechanical construction results in low accuracy and insufficient locking conditions, making them unable to meet the high-precision synchronization requirements of modern power grids.

[0004] Therefore, in order to solve these problems, we propose a digital synchronous check relay. Utility Model Content

[0005] The purpose of the utility model is to solve the shortcomings of the traditional synchronization check relay in the prior art, such as the limitation of structural design and processing capability, which easily leads to refusal to operate or malfunction, and to propose a digital synchronization check relay.

[0006] In order to achieve the above purpose, the present invention adopts the following technical solutions:

[0007] Design a digital synchronous verification relay, including a main control CPU installed in the shell, A / D sampling circuit, power supply circuit, key acquisition circuit, digital tube display circuit and relay execution circuit;

[0008] The output end of the A / D sampling circuit and the key acquisition circuit is electrically connected to the input end of the main control CPU, and the output end of the main control CPU is electrically connected to the digital tube display circuit and the relay execution circuit;

[0009] The A / D sampling circuit includes two operational amplifier circuits, and the two operational amplifier circuits are respectively used to connect the voltage transformer voltage of the to-be-parallel side Ug and the system side Us.

[0010] Furthermore, the operational amplifier circuit includes a resistor R2 and a resistor R5 for connecting to the side to be paralleled Ug. The other ends of the resistors R2 and R5 are connected to a transformer T1. One output end of the transformer T1 is connected to the negative terminal of the operational amplifier U1A, and the other end is connected in series with a resistor R4 and then connected to the positive terminal of U1A.

[0011] A resistor R1 is electrically connected between the negative terminal of U1A and its output terminal, and the output terminal of U1A is connected to the main control CPU via a resistor R3.

[0012] Furthermore, the output ends of the two operational amplifier circuits are connected to pins 15 and 16 of the main control CPU respectively.

[0013] Furthermore, the input end of the resistor R4 is grounded, and the output end of the resistor R3 is grounded via the capacitor C1.

[0014] Furthermore, the power supply circuit includes a transformer T3 connected to an operational amplifier circuit 31, a variable resistor VR1 is connected in series to one input line of the transformer T3, a rectifier bridge DB1 is connected in parallel to the two output ends of the transformer T3, and a capacitor EC1 is connected between the two output ends of the rectifier bridge DB1.

[0015] Furthermore, the key acquisition circuit has four key switches, one end of the four key switches is respectively connected to pins 7, 8, 9 and 10 of the main control CPU, and the other end is grounded.

[0016] Furthermore, the relay execution circuit includes an optocoupler OP1, one end of the optocoupler OP1 is connected to 3.3V through a resistor R12, and the other end is connected to pin 35 of the main control CPU. One output end of the optocoupler OP1 is connected to VCC, and the other output end is grounded through a diode D1 and a resistor R13. The two ends of the diode D1 are connected to pins 1 and 4 of the relay REL1.

[0017] The utility model proposes a digital synchronization verification relay, which has the beneficial effect that: the utility model improves the inherent safety performance of the equipment by adopting the digital synchronization verification relay to interlock with the synchronization device, and ensures the smooth connection between the generator and the power system. This safe and reliable synchronization grid-connected method can effectively avoid the occurrence of unplanned shutdown events, ensure the safe and stable operation of the generator set, and also play a vital role in protecting the power generation of the power plant. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the shell structure of the utility model;

[0019] Figure 2 A schematic block diagram of the circuit connections of the present invention;

[0020] Figure 3 This is the circuit diagram of the main control CPU of the utility model;

[0021] Figure 4 This is the circuit diagram of the main control CPU and A / D sampling circuit of the utility model;

[0022] Figure 5 This is a circuit diagram of the main control CPU and relay execution circuit of the utility model;

[0023] Figure 6 This is the circuit diagram of the digital tube display circuit of the utility model;

[0024] Figure 7 This is the circuit diagram of the key acquisition circuit of the utility model.

[0025] In the figure: 1. Housing; 2. Main control CPU; 3. A / D sampling circuit; 31. Operational amplifier circuit; 4. Power supply circuit; 5. Key acquisition circuit; 6. Digital tube display circuit; 7. Relay execution circuit. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0027] Reference Figure 1-7 This is an embodiment of the utility model, which discloses a digital synchronous verification relay, which includes a main control CPU 2, an A / D sampling circuit 3, a power supply circuit 4, a key acquisition circuit 5, a digital tube display circuit 6 and a relay execution circuit 7 installed in a housing 1. In this embodiment, the main control CPU 2 is a single-chip microcomputer U2, whose model is STM32F103R6;

[0028] Reference Figure 1 Specifically, it is explained that the housing 1 described in this embodiment is designed with conventional dimensions to adapt to the compatibility issues of the mechanical synchronous inspection relay. The precise matching of its physical installation dimensions and installation methods ensures seamless connection and perfect replacement during the replacement of the old system with the new one.

[0029] The output ends of the A / D sampling circuit 3 and the key acquisition circuit 5 are electrically connected to the input end of the main control CPU 2, and the output end of the main control CPU 2 is electrically connected to the digital tube display circuit 6 and the relay execution circuit 7;

[0030] The A / D sampling circuit 3 includes two operational amplifier circuits 31 , and the two operational amplifier circuits 31 are respectively used to connect the voltage transformer voltages of the to-be-parallel-connected side Ug and the system side Us.

[0031] Reference Figure 3 In some embodiments, the operational amplifier circuit 31 includes a resistor R2 and a resistor R5 for connecting to the side to be paralleled Ug. The other ends of the resistor R2 and the resistor R5 are connected to a transformer T1. One output end of the transformer T1 is connected to the negative terminal of the operational amplifier U1A, and the other end is connected in series with a resistor R4 and then connected to the positive terminal of U1A.

[0032] A resistor R1 is electrically connected between the negative terminal of the U1A and its output terminal, and the output terminal of the U1A is connected to the main control CPU 2 via a resistor R3.

[0033] Reference Figure 3 、 4 The structures of the two operational amplifier circuits 31 are the same, so the specific circuit connection of the other operational amplifier circuit 31 is not repeated here. The output ends of the two operational amplifier circuits 31 are respectively connected to the 15th pin and the 16th pin of the main control CPU 2, so that the main control CPU 2 can calculate the synchronization parameter difference between the to-be-parallel side Ug and the system side Us, and control the switching state of the relay REL1 accordingly.

[0034] The original voltage signal from the external transformer is pre-processed by the A / D sampling circuit 3, including reduction, filtering, isolation, etc., to ensure the quality and stability of the signal. After conditioning, the signal is sent to the main control CPU 2 for further processing.

[0035] On the basis of the above embodiment, in this embodiment, the input end of the resistor R4 is grounded, and the output end of the resistor R3 is grounded via the capacitor C1 , so that a filtering effect is achieved through the provided capacitor C1 .

[0036] Reference Figure 4 In some embodiments, the power supply circuit 4 of the present invention includes a transformer T3 connected to an operational amplifier circuit 31, a variable resistor VR1 is connected in series to one input line of the transformer T3, a rectifier bridge DB1 is connected in parallel to the two output ends of the transformer T3, and a capacitor EC1 is connected between the two output ends of the rectifier bridge DB1. The power supply circuit 4 provides a stable and reliable power supply for the entire relay system to ensure that the relay can operate normally under various working conditions.

[0037] Reference Figure 7 Furthermore, the key acquisition circuit 5 in this embodiment has four key switches, one end of the four key switches is respectively connected to pins 7, 8, 9 and 10 of the main control CPU 2, and the other end is grounded. In this embodiment, the key acquisition circuit 5 is used to set and adjust the fixed value parameters.

[0038] In addition, refer to Figure 6 In this embodiment, the digital tube display circuit 6 is set to a 4-digit digital tube display, which is used to display the currently sampled voltage, frequency, angle difference and view the value of the parameter setting. The pins of the digital tube display circuit 6 are connected to the pins of the main control CPU 2. The specific connection method is a conventional method used by technicians in the relevant field and will not be elaborated here.

[0039] Reference Figure 5 Furthermore, the relay execution circuit 7 in this embodiment includes an optocoupler OP1, one end of the optocoupler OP1 is connected to 3.3V via a resistor R12, and the other end is connected to pin 35 of the main control CPU 2. One output end of the optocoupler OP1 is connected to VCC, and the other output end is grounded via a diode D1 and a resistor R13. Pins 1 and 4 of the relay REL1 are connected between the two ends of the diode D1. The relay execution circuit 7 is responsible for converting the control signal of the main control CPU 2 into an actual switching action. When it is determined that the synchronization parameters between the to-be-parallelized side Ug and the system side Us meet the preset conditions, a control signal will be sent to the relay execution circuit 7 to drive the contacts of the relay REL1 to close or open, thereby realizing the on-off operation of the closing circuit.

[0040] The digital synchronization check relay collects the voltage of the voltage transformer Ug on the side to be connected and the voltage transformer Us on the system side, and intelligently establishes a comprehensive interlocking relationship of voltage difference, frequency difference, and phase angle difference. Grid connection is allowed only when the synchronization device and the synchronization check relay are both judged to be synchronous. Through the precise matching technology of voltage, frequency and phase during the synchronization parallel process, multiple protections are used to ensure the strict synchronicity of both synchronous parallel operations of the same frequency and difference frequency. This redundancy design greatly reduces the risk of incorrect grid connection due to single point failure.

[0041] In summary, the present invention improves the inherent safety performance of the equipment by adopting a digital synchronization check relay and a synchronization device for interlocking, and ensures a smooth connection between the generator and the power system. This safe and reliable synchronization grid-connected method can effectively avoid the occurrence of unplanned shutdown events, ensure the safe and stable operation of the generator set, and also play a vital role in protecting the power generation of the power plant.

[0042] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any technician familiar with the technical field within the technical scope disclosed by the present invention can make equivalent replacements or changes based on the technical solution and utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A digital synchronous check relay, characterized in that: The invention comprises a main control CPU (2) installed in a housing (1), an A / D sampling circuit (3), a power supply circuit (4), a key acquisition circuit (5), a digital tube display circuit (6) and a relay execution circuit (7); The output ends of the A / D sampling circuit (3) and the key acquisition circuit (5) are electrically connected to the input end of the main control CPU (2), and the output end of the main control CPU (2) is electrically connected to the digital tube display circuit (6) and the relay execution circuit (7); The A / D sampling circuit (3) comprises two operational amplifier circuits (31), and the two operational amplifier circuits (31) are respectively used to connect the voltage transformer voltages on the to-be-parallel side Ug and the system side Us.

2. A digital synchronous check relay according to claim 1, characterized in that: The operational amplifier circuit (31) includes a resistor R2 and a resistor R5 for connecting to the parallel side Ug, the other ends of the resistor R2 and the resistor R5 are connected to the transformer T1, one output end of the transformer T1 is connected to the negative end of the operational amplifier U1A, and the other end is connected to the positive end of U1A after being connected in series with a resistor R4; A resistor R1 is electrically connected between the negative terminal of the U1A and its output terminal, and the output terminal of the U1A is connected to the main control CPU (2) via a resistor R3.

3. A digital synchronous check relay according to claim 2, characterized in that: The output ends of the two operational amplifier circuits (31) are respectively connected to pins 15 and 16 of the main control CPU (2).

4. A digital synchronous check relay according to claim 2, characterized in that: The input end of the resistor R4 is grounded, and the output end of the resistor R3 is grounded via the capacitor C1.

5. The digital synchronous check relay according to claim 2, characterized in that: The power supply circuit (4) includes a transformer T3 connected to an operational amplifier circuit (31), a variable resistor VR1 is connected in series to an input line of the transformer T3, a rectifier bridge DB1 is connected in parallel to two output ends of the transformer T3, and a capacitor EC1 is connected between the two output ends of the rectifier bridge DB1.

6. The digital synchronous check relay according to claim 1, characterized in that: The key acquisition circuit (5) has four key switches, one end of each of the four key switches is connected to pins 7, 8, 9 and 10 of the main control CPU (2), and the other ends are grounded.

7. The digital synchronous check relay according to claim 1, characterized in that: The relay execution circuit (7) includes an optocoupler OP1, one end of the optocoupler OP1 is connected to 3.3V via a resistor R12, and the other end is connected to pin 35 of the main control CPU (2). One output end of the optocoupler OP1 is connected to VCC, and the other output end is grounded via a diode D1 and a resistor R13. The two ends of the diode D1 are connected to pins 1 and 4 of the relay REL1.

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