Lower-layer data storage control panel for radar

Abstract

The utility model relates to a lower layer data storage control panel for radar, which comprises a single chip microcomputer, a data storage module, a reset module, a crystal oscillator module and a power supply module, the data storage module, the reset module, the crystal oscillator module and the power supply module are all connected with the single chip microcomputer, and the data storage module comprises a storage chip UC6, capacitors C6 and C7 and resistors R2 and R3. A pin 4 of the storage chip UC6 is connected with the power supply module, one end of the capacitor C6 is connected with an output pin of the power supply module, the other end of the capacitor C6 is grounded, a pin 5 of the storage chip UC6 is grounded, a pin 1 of the storage chip UC6 is connected with a pin 29 of the single chip microcomputer, a pin 3 of the storage chip UC6 is connected with a pin 30 of the single chip microcomputer and is connected with the power supply module through a resistor R2, and a pin 2 of the storage chip UC6 is connected with a pin 60 of the storage chip UC6 through a resistor R3 and a capacitor C7 which are connected in parallel. And a pin 2 of the storage chip UC6 is grounded at the same time. According to the design, the reliability and durability of data are ensured, and packet loss is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic information, in particular to a lower layer data storage control board for radar. Background Art

[0002] Data storage modules play a crucial role in radar systems. They receive control commands from the radar system during operation, store detected target parameters, and transmit them to the control system in real time. High-speed data transmission and storage require configuration of the communication method, transmission rate, and number of interfaces. Microcontrollers (MCUs) can control signal transmission. While current MCUs incorporate internal RAM as a storage module, these typically have limited storage space and limited functionality, making them difficult to adapt to the high-speed data transmission and reading required by specialized radar equipment. Therefore, improvements are needed. Utility Model Content

[0003] Based on this, it is necessary to provide a lower layer data storage control board for radar to address the above problems.

[0004] A lower-layer data storage control board for radar includes a single-chip microcomputer, a data storage module, a reset module, a crystal oscillator module and a power module. The data storage module, reset module, crystal oscillator module and power module are all connected to the single-chip microcomputer. The data storage module includes a storage chip UC6, capacitors C6 and C7, and resistors R2 and R3. Pin 4 of the storage chip UC6 is connected to the power module 5, one end of the capacitor C6 is connected to the output pin of the power module, and the other end is grounded. Pin 5 of the storage chip UC6 is grounded, pin 1 is connected to pin 29 of the single-chip microcomputer, pin 3 is connected to pin 30 of the single-chip microcomputer, and is connected to the power module 5 through resistor R2. Pin 2 of the storage chip UC6 is connected to pin 60 of the storage chip UC6 through a parallel resistor R3 and capacitor C7, and pin 2 of the storage chip UC6 is also grounded.

[0005] Preferably, the model of the single chip microcomputer is STM32F405RG-LQFP64, and the model of the memory chip UC6 is 24LC32AT-I / OT.

[0006] Preferably, the crystal oscillator module includes an oscillator BY1, capacitors C11, C12 and a resistor R4, pins 1 and 4 of the oscillator BY1 are grounded, pin 2 is grounded through capacitor C12, and pin 3 is connected to pin 5 of the microcontroller. One end of the capacitor C11 is connected to pin 5 of the microcontroller 1, and the other end is grounded. One end of the resistor R4 is connected to pin 6 of the microcontroller 1, and the other end is connected to pin 2 of the oscillator BY1.

[0007] Preferably, the power supply module includes a voltage regulator LDO1, capacitors C1~C5, resistors R5 and R6, pin 1 of the voltage regulator LDO1 is connected to the 5V power supply, pin 2 is grounded, and capacitor C1 and resistor R5 are connected in series in sequence, and then connected to the 5V power supply, pin 3 is connected in series with resistor R6 and then connected to the 5V power supply, pin 4 of the voltage regulator LDO1 is connected in series with capacitor C2 and then grounded, capacitors C3~C5 are connected in parallel, one end of capacitors C3~C5 is grounded, and the other end is connected to pin 5 of the voltage regulator LDO1.

[0008] Preferably, the model of the voltage regulator LDO1 is TPS7A2033PDBVR.

[0009] The benefits of the present invention are that the memory chip is an electrically erasable programmable read-only memory, and data can be retained for a long time even when the power is cut off or restored, thereby ensuring the reliability and durability of the data. In conjunction with the outer circuit, the single-chip microcomputer can perform high-speed bidirectional transmission, call, and erase of radar data in the memory chip, thereby avoiding packet loss and rewriting of the entire data chain, saving time and resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a circuit module diagram of a lower layer data storage control board for radar according to one embodiment;

[0011] Figure 2 A circuit diagram of a lower layer data storage control board for radar;

[0012] Figure 3 This is the circuit diagram of the power module. DETAILED DESCRIPTION

[0013] To make the above-mentioned objects, features, and advantages of the present invention more clearly understood, the following detailed description of specific embodiments of the present invention is provided in conjunction with the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0014] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only implementation methods.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of this invention are intended only to describe specific embodiments and are not intended to limit this invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0016] like Figures 1 to 3 As shown, a lower layer data storage control board for radar includes a single chip microcomputer 1, a data storage module 2, a reset module 3, a crystal oscillator module 4 and a power module 5. The data storage module 2, the reset module 3, the crystal oscillator module 4 and the power module 5 are all connected to the single chip microcomputer 1. The data storage module 2 includes a storage chip UC6, capacitors C6 and C7, and resistors R2 and R3. Pin 4 of the storage chip UC6 is connected to the power module 5. One end of the capacitor C6 is connected to the output pin of the power module 5 and the other end is grounded. Pin 5 of the storage chip UC6 is grounded, pin 1 is connected to pin 29 of the single chip microcomputer 1, pin 3 is connected to pin 30 of the single chip microcomputer 1, and is connected to the power module 5 through resistor R2. Pin 2 of the storage chip UC6 is connected to pin 60 of the storage chip UC6 through a parallel resistor R3 and capacitor C7. Pin 2 of the storage chip UC6 is also grounded. Specifically, a single-chip microcomputer 1 is used as the control chip, and a reset module 3 is used to provide a reset signal to the single-chip microcomputer 1. This initializes the registers, ports, and other hardware resources within the single-chip microcomputer 1 to a predetermined state, allowing the single-chip microcomputer 1 to begin program execution from a known and determined state, avoiding erroneous operations caused by unknown states. A power supply module 5 serves as the power supply, and a crystal oscillator module 4 has strong anti-interference capabilities, capable of resisting external electromagnetic interference to a certain extent, ensuring the stable operation of the single-chip microcomputer 1. Furthermore, the oscillation frequency of the crystal oscillator module 4 can be changed by adjusting circuit parameters to meet the clock frequency requirements of different applications. The data storage module 2 in this design supports data erasure and reprogramming. It includes a memory chip UC6, capacitors C6 and C7, and resistors R2 and R3. Pins 29 and 30 of the single-chip microcomputer 1 serve as a serial communication interface, enabling data exchange and communication with the memory chip UC6. Pin 60 of the single-chip microcomputer serves as a startup pin, and its level state (high or low) controls the startup mode of the single-chip microcomputer 1. The capacitors C6, C7 and the resistors R2, R3 arranged around the memory chip UC6 can filter out high-frequency harmonics and noise in the power supply or signal, reduce their interference to the memory chip UC6, and protect the stable operation of the memory chip.

[0017] Specifically, the model of the single chip computer 1 is STM32F405RG-LQFP64, and the model of the memory chip UC6 is 24LC32AT-I / OT.

[0018] like Figure 2 As shown, the crystal oscillator module 4 includes an oscillator BY1, capacitors C11, C12 and a resistor R4. Pins 1 and 4 of the oscillator BY1 are grounded, pin 2 is grounded through capacitor C12, and pin 3 is connected to pin 5 of the microcontroller 1. One end of the capacitor C11 is connected to pin 5 of the microcontroller 1 and the other end is grounded. One end of the resistor R4 is connected to pin 6 of the microcontroller 1 and the other end is connected to pin 2 of the oscillator BY1. Specifically, the oscillator BY1 is used to

[0019] like Figure 3 As shown, the power supply module 5 includes a voltage regulator LDO1, capacitors C1-C5, and resistors R5 and R6. Pin 1 of the voltage regulator LDO1 is connected to the 5V power supply, and pin 2 is grounded. After capacitor C1 and resistor R5 are connected in series, they are connected to the 5V power supply. Pin 3 is connected in series with resistor R6 and then to the 5V power supply. Pin 4 of the voltage regulator LDO1 is connected in series with capacitor C2 and then to ground. Capacitors C3-C5 are connected in parallel, with one end of capacitors C3-C5 grounded and the other end connected to pin 5 of the voltage regulator LDO1. Specifically, the voltage regulator LDO1 is used to stabilize and step down the input 5V voltage, outputting a stable 3.3V voltage to ensure normal operation of the electronic device at the rated voltage. The circuit composed of the peripheral capacitors C1-C5 and resistors R5 and R6 can reduce unstable factors such as interference, noise, and ripple in the input power supply to a low level.

[0020] Specifically, the model of the voltage regulator LDO1 is TPS7A2033PDBVR.

[0021] The above-described embodiments merely represent several implementations of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements fall within the scope of protection of the present invention. Therefore, the scope of protection of the present utility model patent shall be determined by the appended claims.

Claims

1. A radar lower data storage control board, characterized by: It includes a single-chip microcomputer, a data storage module, a reset module, a crystal oscillator module and a power supply module. The data storage module, reset module, crystal oscillator module and power supply module are all connected to the single-chip microcomputer. The data storage module includes a storage chip UC6, capacitors C6 and C7, and resistors R2 and R3. Pin 4 of the storage chip UC6 is connected to the power supply module, one end of the capacitor C6 is connected to the output pin of the power supply module, and the other end is grounded. Pin 5 of the storage chip UC6 is grounded, pin 1 is connected to pin 29 of the single-chip microcomputer, pin 3 is connected to pin 30 of the single-chip microcomputer, and is connected to the power supply module through resistor R2. Pin 2 of the storage chip UC6 is connected to pin 60 of the storage chip UC6 through a parallel resistor R3 and capacitor C7, and pin 2 of the storage chip UC6 is grounded at the same time.

2. A radar lower layer data storage control board as claimed in claim 1, characterized in that: The model of the single chip microcomputer is STM32F405RG-LQFP64, and the model of the memory chip UC6 is 24LC32AT-I / OT.

3. The radar lower layer data storage control board according to claim 1, characterized in that: The crystal oscillator module includes an oscillator BY1, capacitors C11, C12 and a resistor R4. Pins 1 and 4 of the oscillator BY1 are grounded, pin 2 is grounded through capacitor C12, and pin 3 is connected to pin 5 of the microcontroller. One end of the capacitor C11 is connected to pin 5 of the microcontroller, and the other end is grounded. One end of the resistor R4 is connected to pin 6 of the microcontroller, and the other end is connected to pin 2 of the oscillator BY1.

4. The radar lower layer data storage control board according to claim 1, characterized in that: The power supply module includes a voltage regulator LDO1, capacitors C1~C5, and resistors R5 and R6. Pin 1 of the voltage regulator LDO1 is connected to a 5V power supply, and pin 2 is grounded. Capacitor C1 and resistor R5 are connected in series in sequence, and then connected to the 5V power supply. Pin 3 is connected in series with resistor R6 and then connected to the 5V power supply. Pin 4 of the voltage regulator LDO1 is connected in series with capacitor C2 and then grounded. Capacitors C3~C5 are connected in parallel, and one end of capacitors C3~C5 is grounded, and the other end is connected to pin 5 of the voltage regulator LDO1.

5. A radar lower layer data storage control board as claimed in claim 4, characterized in that: The model of the voltage regulator LDO1 is TPS7A2033PDBVR.

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