Communication circuit and communication system of serial peripheral interface
By setting a chip select signal control unit in the SPI controller and utilizing the chip select interface and general input and output interface of the master device, communication with multiple slave devices is achieved, solving the resource shortage problem in the existing technology and ensuring the accuracy and reliability of data transmission.
Patent Information
- Application Number
- CN202422953289.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-09-23
- Estimated Expiration
- 2034-11-29
AI Technical Summary
The existing SPI controller has only one set of chip select signal lines and cannot communicate with multiple slave devices.
By setting a chip select signal control unit and utilizing the chip select interface and universal input and output interface of the master device, the output levels of multiple slave devices are controlled to achieve communication with multiple slave devices.
It expands the selection capability of serial peripheral interfaces, solves the problem of resource shortage, ensures the accuracy and reliability of data transmission, and supports one-to-many situations.
Smart Images
Figure CN223377729U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of communication interfaces, and in particular to a communication circuit and a communication system of a serial peripheral interface. Background Art
[0002] SPI (Serial Peripheral Interface) is a widely used synchronous serial communication protocol primarily used for short-distance communication, particularly between microcontrollers and peripheral devices. The devices involved in the communication are generally categorized as master and slave devices, with the microcontroller typically acting as the master and the peripheral device as the slave. In addition to the SCLK (Synchronous Clock), MOSI (Master Output Slave Input), and MISO (Master Input Slave Output) lines used for communication, the master and slave devices also require a chip select (CS) line. This CS line is used by the master to pull down the corresponding CS line of a slave device when communicating with it.
[0003] In the prior art, the SPI controller has only one set of chip select signal lines, which has limitations when dealing with one-to-many situations and cannot communicate with multiple slave devices. Utility Model Content
[0004] Embodiments of the present application provide a communication circuit and a communication system for a serial peripheral interface, which are used to solve the problem in the prior art of being unable to communicate with multiple slave devices.
[0005] In a first aspect, an embodiment of the present application provides a communication circuit of a serial peripheral interface, comprising: at least one chip select signal control unit;
[0006] The chip select signal control unit includes at least two input terminals and two output terminals, and the output terminals of the chip select signal control unit are connected to the multiple slave devices in a one-to-one correspondence; the first input terminal of the chip select signal control unit is connected to the chip select interface of the master device, and the second input terminal is connected to the universal input and output interface of the master device;
[0007] The chip select signal control unit is used to control the output level of each output terminal according to the signals output by the chip select interface and the universal input and output interface of the master device.
[0008] In one embodiment, the chip select signal control unit further includes a first resistor and a diode, one end of the first resistor is connected to the first input end of the chip select signal control unit, and the other end is commonly connected to the cathode of the diode and the first slave device, the anode of the diode is connected to the second input end of the chip select signal control unit, and the diode is used to isolate the first signal output by the chip select interface.
[0009] In one embodiment, the chip select signal control unit further includes an inverting circuit, wherein a first input terminal of the inverting circuit is commonly connected to the first input terminal of the chip select signal control unit and the anode of the diode, and a second input terminal of the inverting circuit is connected to the first power supply; a first output terminal of the inverting circuit is connected to the second slave device, and a second output terminal of the inverting circuit is grounded;
[0010] The inverting circuit is controlled to be on or off according to the first signal and the second signal output by the universal input and output interface.
[0011] In one embodiment, the reverse circuit controls on and off according to the first signal and the second signal output by the universal input and output interface, including:
[0012] When the first signal is an invalid signal, no matter the second signal is at a low level or a high level, the reverse circuit is not conducting;
[0013] When the first signal is a valid signal and the second signal is a level signal opposite to the first signal, the reverse circuit is turned on;
[0014] When the first signal is a valid signal and the second signal is a signal with the same level as the first signal, the reverse circuit is not turned on.
[0015] In one embodiment, when the reverse circuit is turned on, the master device and the second slave device can communicate normally.
[0016] In one embodiment, the reverse circuit includes a second resistor, a third resistor, and a transistor;
[0017] The base of the transistor is connected to one end of the second resistor, the collector is commonly connected to one end of the third resistor and the second slave device, and the emitter is grounded;
[0018] The other end of the second resistor is commonly connected to the anode of the diode and the second input end of the chip selection signal control unit;
[0019] The other end of the third resistor is connected to the first power supply.
[0020] In one embodiment, the transistor is an NPN transistor.
[0021] In one embodiment, the chip select signal control unit further includes a first logic gate circuit, a second logic gate circuit, and a third input terminal; the master device includes a first universal input / output interface and a second universal input / output interface; and the slave device includes a first slave device and a second slave device;
[0022] The second input end of the chip select signal control unit is connected to the first universal input / output interface of the master device and the first input end of the first logic gate circuit, the third input end is connected to the second universal input / output interface of the master device and the first input end of the second logic gate circuit, the first output end of the chip select signal control unit is connected to the first slave device, and the second output end of the chip select signal control unit is connected to the second slave device;
[0023] The second input terminals of the first logic gate circuit and the second logic gate circuit are commonly connected to the first input terminal of the chip selection signal control unit.
[0024] In one embodiment, when the first signal output by the chip select interface is a valid signal and the second signal output by the first universal input / output interface is the same as the first signal, the master device and the first slave device can communicate normally;
[0025] When the first signal is a valid signal and the third signal output by the second universal input / output interface is the same as the first signal, the master device and the second slave device can communicate normally.
[0026] In one embodiment, when the first signal output by the chip select interface is an invalid signal, the master device does not communicate with the first slave device or the second slave device.
[0027] In one embodiment, the first logic gate circuit and the second logic gate circuit are the same XOR gate circuit.
[0028] In one embodiment, the first logic gate circuit and the second logic gate circuit are the same OR gate circuit.
[0029] In a second aspect, an embodiment of the present application provides a communication system of a serial peripheral interface, comprising a master device, multiple slave devices, and a communication circuit of the serial peripheral interface as described in the first aspect, wherein the communication between the master device and each slave device is controlled by the output level output by the communication circuit of the serial peripheral interface.
[0030] An embodiment of the present application provides a communication circuit and communication system for a serial peripheral interface, the circuit comprising: at least one chip select signal control unit; the chip select signal control unit comprising at least two input terminals and two output terminals, the output terminals of the chip select signal control unit being connected to a plurality of slave devices in a one-to-one correspondence; a first input terminal of the chip select signal control unit being connected to a chip select interface of a master device, and a second input terminal being connected to a universal input / output interface of the master device; the chip select signal control unit being configured to control the output level of each output terminal based on signals output from the chip select interface and the universal input / output interface of the master device. The present application solves the limitation of the prior art in that it is impossible to communicate with multiple slave devices by providing a chip select signal control unit to connect a master device to multiple slave devices, and controlling the master device to communicate with any one of the slave devices based on the chip select interface and the universal input / output interface of the master device. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0032] Figure 1 A schematic diagram of the structure of a communication circuit of a serial peripheral interface provided in one embodiment of the present application;
[0033] Figure 2 A schematic structural diagram of a communication circuit of a serial peripheral interface provided in yet another embodiment of the present application;
[0034] Figure 3 A schematic structural diagram of a communication circuit of a serial peripheral interface provided in yet another embodiment of the present application;
[0035] Figure 4 A structural diagram of a communication circuit of a serial peripheral interface provided in another embodiment of the present application.
[0036] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION
[0037] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present application.
[0038] SPI (Serial Peripheral Interface) is a widely used synchronous serial communication protocol primarily used for short-distance communication, particularly between microcontrollers and peripheral devices. The devices involved in the communication are generally categorized as master and slave devices, with the microcontroller typically acting as the master and the peripheral device as the slave. In addition to the SCLK (Synchronous Clock), MOSI (Master Output Slave Input), and MISO (Master Input Slave Output) lines used for communication, the master and slave devices also require a chip select (CS) line. This CS line is used by the master to pull down the corresponding CS line of a slave device when communicating with it.
[0039] In the prior art, the SPI controller has only one set of chip select signal lines, which has limitations when dealing with one-to-many situations and cannot communicate with multiple slave devices.
[0040] An embodiment of the present application provides a communication circuit and communication system for a serial peripheral interface, the circuit comprising: at least one chip select signal control unit; the chip select signal control unit comprising at least two input terminals and two output terminals, the output terminals of the chip select signal control unit being connected to a plurality of slave devices in a one-to-one correspondence; a first input terminal of the chip select signal control unit being connected to a chip select interface of a master device, and a second input terminal being connected to a universal input / output interface of the master device; the chip select signal control unit being configured to control the output level of each output terminal based on signals output from the chip select interface and the universal input / output interface of the master device. The present application solves the limitation of the prior art in that it is impossible to communicate with multiple slave devices by providing a chip select signal control unit to connect a master device to multiple slave devices, and controlling the master device to communicate with any one of the slave devices based on the chip select interface and the universal input / output interface of the master device.
[0041] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0042] Both the master device and the slave device have a set of chip select signal lines. The master device can communicate with multiple slave devices by adding a general-purpose input and output interface GPIO.
[0043] like Figure 1 As shown, Figure 1A schematic structural diagram of a communication circuit for a serial peripheral interface provided in one embodiment of the present application. The communication circuit of the serial peripheral interface includes: at least one chip select signal control unit; the chip select signal control unit includes at least two input terminals and two output terminals, the output terminals of the chip select signal control unit being connected to a plurality of slave devices in a one-to-one correspondence; a first input terminal of the chip select signal control unit being connected to a chip select interface CS of a master device, and a second input terminal being connected to a general purpose input / output (GPIO) interface (GPIO) of the master device; and the chip select signal control unit being configured to control the output level of each output terminal based on signals output from the chip select interface and the GPIO interface of the master device.
[0044] Specifically, the master device communicates with one of the slave devices, and controls the output level of the output terminal of the chip select signal control unit connected to the slave device through the signals output by the chip select interface and the general input and output interface of the master device, thereby controlling the communication between the master device and the slave device.
[0045] Figure 1 The embodiment is illustrated by taking two slave devices as an example. The two slave devices also have chip select interfaces: corresponding to CS_1 and CS_2 respectively, and the master device has a chip select interface: CS_0. The chip select signal control unit controls the state of its output terminal according to the signals sent by the chip select interface and the general input and output interface it receives. When the chip select signal control unit communicates with one of the slave devices, it must ensure that the state of only one output terminal is a valid level. The valid level can enable the slave device and activate the slave device to work. In the embodiment of the present application, the output level of the chip select interface is a low level as the valid level, that is, when the chip select signal control unit communicates with the slave device, it must meet the requirement that the state of the corresponding output terminal is a low level. The present application allows the master device to flexibly select and control multiple slave devices by combining the chip select interface and the general input and output interface GPIO, expands the selection capability of the communication circuit of the serial peripheral interface, solves the problem of resource constraints, and thus copes with one-to-many situations; at the same time, ensures the accuracy and reliability of data transmission.
[0046] In one embodiment, Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of the communication circuit of the serial peripheral interface provided by one embodiment of the present application. The communication circuit of the serial peripheral interface provided by this embodiment is a one-to-two situation, that is, one master device communicates with two slave devices. The chip select signal control unit in this embodiment can also be N, so that one master device can communicate with (N-1) slave devices. Figure 2As shown, the chip select signal control unit 10 also includes a first resistor R1 and a diode D1. One end of the first resistor R1 is connected to the first input terminal A of the chip select signal control unit 10, and the other end is commonly connected to the cathode of the diode D1 and the first slave device. The anode of the diode D1 is connected to the second input terminal B of the chip select signal control unit 10. The diode D1 is used to isolate the first signal output by the chip select interface CS_0 (that is, the signal received at point A).
[0047] Specifically, when the first signal is a low-level valid signal and the second signal output by the general-purpose input / output interface GPIO (i.e., the signal received at point C) is also a low-level signal, the chip select signal control unit 10 outputs a low-level valid signal to the first slave device, enabling CS_1 of the first slave device, thereby enabling normal communication between the master device and the first device. When the first signal is a high-level signal, the chip select interface CS_0 outputs an invalid signal, preventing the chip from being enabled. Therefore, regardless of whether the second signal is a high-level signal or a low-level signal, the chip select signal control unit 10 outputs a high-level invalid signal to the first slave device, disabling CS_1 of the first slave device and preventing communication between the master device and the first device.
[0048] In one embodiment, the chip select signal control unit 10 further includes an inverting circuit 101, wherein a first input terminal C of the inverting circuit 101 is commonly connected to a second input terminal B of the chip select signal control unit 10 and an anode of a diode D1, and a second input terminal D of the inverting circuit 101 is connected to a first power supply VCC; a first output terminal of the inverting circuit 101 is connected to a second slave device, and a second output terminal of the inverting circuit 101 is grounded; and the inverting circuit 101 is controlled to be on or off according to the first signal and a second signal output by the general input and output interface GPIO (i.e., a signal received at point C).
[0049] In one embodiment, the reverse circuit 101 is controlled to be on and off according to the first signal and the second signal output by the universal input and output interface, including: when the first signal is an invalid signal, the reverse circuit is not conductive regardless of whether the second signal is at a low level or a high level; when the first signal is a valid signal and the second signal is a level signal opposite to the first signal, the reverse circuit is conductive; when the first signal is a valid signal and the second signal is a level signal the same as the first signal, the reverse circuit is not conductive.
[0050] Specifically, depending on the chip select interface CS_0 of the master device, some master devices are valid when the chip select interface CS_0 is at a low level, i.e., they can activate the chip, and are invalid when the chip select interface CS_0 is at a high level, i.e., they can disable the chip, as in the example in this case. Specifically, when the first signal output by the chip select interface CS_0 is a high-level signal, the reverse circuit 101 is not conducting, regardless of whether the second signal output by the CPIO interface is low or high. When the first signal is a low-level signal and the second signal is a high-level signal opposite to the first signal, the reverse circuit 101 is conducting. When the first signal is a low-level signal and the second signal is a low-level signal identical to the first signal, the reverse circuit 101 is not conducting. When the reverse circuit 101 is conducting, it indicates that the master device is communicating normally with the second slave device connected to the reverse circuit 101. When the reverse circuit 101 is not conducting, it indicates that the master device cannot communicate with the second slave device connected to the reverse circuit 101.
[0051] In one embodiment, see Figure 2 The reverse circuit 101 includes a second resistor R2, a third resistor R3 and a transistor Q1; the base of the transistor Q1 is connected to one end of the second resistor R2, the collector is commonly connected to one end of the third resistor R3 and the CS_2 interface of the second slave device, and the emitter is grounded; the other end of the second resistor R2 is commonly connected to the anode of the diode Q1 and the second input terminal B of the chip select signal control unit 10; the other end of the third resistor R3 is connected to the first power supply VCC.
[0052] In one embodiment, the transistor Q1 is an NPN transistor.
[0053] Specifically, when CS_0 outputs a low level and GPIO outputs a high level, diode D1 causes CS_1 to output a high level, transistor Q1 conducts, and the level at CS_2 is pulled low, enabling CS_2. This enables the second slave device, enabling the master device to communicate with the second slave device. When CS_0 outputs a low level and GPIO outputs a low level, CS_1 outputs a low level, transistor Q1 disconnects, and the level at CS_2 is pulled high by the first power supply, enabling CS_1. This enables the first slave device, enabling the master device to communicate with the first slave device. The master device's chip select interface CS_0 and general-purpose input / output interface GPIO output different signals to enable communication with different slave devices.
[0054] In another case, when CS_0 outputs a high level, the GPIO also outputs a high level, and the CS_1 terminal is high. Although the CS_2 terminal is low, the diode isolates the CS_0 signal, so neither the first slave device nor the second slave device can communicate with the master device. When CS_0 outputs a high level, the GPIO outputs a low level, and both the CS_1 and CS_2 terminals are high, so neither the first slave device nor the second slave device is selected.
[0055] In another embodiment, the chip select signal control unit also includes a first logic gate circuit, a second logic gate circuit and a third input end. The master device is provided with a first universal input and output interface and a second universal input and output interface, and the slave device includes a first slave device and a second slave device; the second input end of the chip select signal control unit is connected to the first universal input and output interface of the master device and the first input end of the first logic gate circuit, the third input end is connected to the second universal input and output interface of the master device and the first input end of the second logic gate circuit, the first output end of the chip select signal control unit is connected to the first slave device, and the second output end of the chip select signal control unit is connected to the second slave device; the second input ends of the first logic gate circuit and the second logic gate circuit are commonly connected to the first input end of the chip select signal control unit.
[0056] In one embodiment, when the first signal output by the chip select interface is a valid signal and the second signal output by the first universal input / output interface is the same as the first signal, the master device and the first slave device can communicate normally; when the first signal is a valid signal and the third signal output by the second universal input / output interface is the same as the first signal, the master device and the second slave device can communicate normally.
[0057] In one embodiment, when the first signal output by the chip select interface is an invalid signal, the master device does not communicate with the first slave device or the second slave device.
[0058] In one embodiment, the first logic gate circuit and the second logic gate circuit are the same XOR gate circuit.
[0059] In one embodiment, the first logic gate circuit and the second logic gate circuit are the same OR gate circuit.
[0060] Specifically, if Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a communication circuit of a serial peripheral interface provided in another embodiment of the present application. The first logic gate circuit and the second logic gate circuit are XOR gate circuits of the same structure. The first logic gate circuit is a first XOR gate, and the second logic gate circuit is a second XOR gate.
[0061] Specifically, when the first signal output by the chip select interface CS_0 is low, the second signal output by the first general-purpose input / output interface GPIO_1 is high, and the second signal output by the second general-purpose input / output interface GPIO_2 is low. After the first XOR gate outputs a high level and the second XOR gate outputs a low level, the CS_2 terminal of the second slave device is enabled, thereby turning on the second slave device and enabling communication between the master and the second slave device. When the first signal output by CS_0 is low, the second signal output by GPIO_1 is low, and the second signal output by GPIO_2 is high. After the first XOR gate outputs a low level and the second XOR gate outputs a high level, the CS_1 terminal of the first slave device is enabled, thereby turning on the first slave device and enabling communication between the master and the first slave device.
[0062] When CS_0 outputs a high level, there are four possible scenarios. The first scenario: GPIO_1 outputs a high level, GPIO_2 outputs a low level, and after the first and second XOR gates output a high level, both CS_1 and CS_2 are disabled. Therefore, the master device cannot communicate with either the first or second slave device. The second scenario: GPIO_1 outputs a low level, GPIO_2 outputs a high level, after the first and second XOR gates output a high level, both CS_1 and CS_2 are disabled. Therefore, the master device cannot communicate with either the first or second slave device. The third scenario: GPIO_1 outputs a low level, GPIO_2 outputs a low level, after the first and second XOR gates output a high level, both CS_1 and CS_2 are disabled. Therefore, the master device cannot communicate with either the first or second slave device. Case 4: GPIO_1 and GPIO_2 both output a high level, and after the first and second XOR gates both output a high level, CS_1 and CS_2 are both disabled, preventing the master from communicating with either the first or second slave device. Specifically, if the first signal output by chip select interface CS_0 is an invalid signal, and a low-level signal is defined as a valid signal in the embodiments of this application, then a high-level signal is an invalid signal. Regardless of whether the second signals output by GPIO_1 and GPIO_2 are high or low, CS_1 of the first slave device and CS_2 of the second slave device are disabled, preventing the master from communicating with either the first or second slave device.
[0063] In one embodiment, Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a communication circuit for a serial peripheral interface provided in another embodiment of the present application. The first logic gate circuit and the second logic gate circuit are OR gate circuits of the same structure. The first logic gate circuit is a first OR gate, and the second logic gate circuit is a second OR gate.
[0064] Specifically, when the first signal output by the chip select interface CS_0 of the master device is low, the second signal output by the first general-purpose input / output interface GPIO_1 is high, and the second signal output by the second general-purpose input / output interface GPIO_2 is low. After the first OR gate outputs a high level and the second OR gate outputs a low level, the CS_2 terminal of the second slave device is enabled, thereby turning on the second slave device and enabling communication between the master and the second slave device. When CS_0 outputs a low level, GPIO_1 outputs a low level and GPIO_2 outputs a high level. After the first OR gate outputs a low level and the second OR gate outputs a high level, the CS_1 terminal of the first slave device is enabled, thereby turning on the first slave device and enabling communication between the master and the first slave device.
[0065] When CS_0 outputs a high level, there are four possible scenarios. The first scenario: GPIO_1 outputs a high level, GPIO_2 outputs a low level, and after passing through the first OR gate and the second OR gate, both output a high level. CS_1 and CS_2 are both disabled, so the master device cannot communicate with either the first or second slave device. The second scenario: GPIO_1 outputs a low level, GPIO_2 outputs a high level, after passing through the first OR gate and the second OR gate, both output a high level. CS_1 and CS_2 are both disabled, so the master device cannot communicate with either the first or second slave device. The third scenario: GPIO_1 outputs a low level, GPIO_2 outputs a low level, after passing through the first OR gate and the second OR gate, both output a high level. CS_1 and CS_2 are both disabled, so the master device cannot communicate with either the first or second slave device. Case 4: GPIO_1 and GPIO_2 both output a high level. After the first and second OR gates output a high level, CS_1 and CS_2 are both disabled. Therefore, the master device cannot communicate with either the first or second slave device. In other words, when the first signal output by chip select interface CS_0 is invalid, the master device cannot communicate with either the first or second slave device, regardless of whether the second signals output by GPIO_1 and GPIO_2 are high or low.
[0066] In one embodiment, the circuit includes two chip select signal control units, each of which includes three input terminals and three output terminals; the master device is provided with two universal input and output interfaces; the slave devices include a first slave device, a second slave device, and a third slave device; the three input terminals of the chip select signal control unit are respectively connected to the chip select interface and the two universal input and output interfaces of the master device; and the three output terminals of the chip select signal control unit are respectively connected to the first slave device, the second slave device, and the third slave device.
[0067] Specifically, this embodiment is directed to a situation where a master device communicates with three slave devices. By analogy, a circuit structure for a master device to communicate with multiple slave devices can be derived, which is not described in detail in this application.
[0068] Based on the aforementioned serial peripheral interface communication circuit, an embodiment of the present application also provides a serial peripheral interface communication system, including a master device, multiple slave devices, and the serial peripheral interface communication circuit as described above, wherein the communication between the master device and each slave device is controlled by the output level output by the serial peripheral interface communication circuit.
[0069] An embodiment of the present application provides an electronic device, including a controller having a communication circuit with a serial peripheral interface and at least one slave device.
[0070] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the solutions disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. It is not limited to the precise structure described above and shown in the drawings, and various modifications and changes may be made without departing from the scope of this application. The scope of this application is limited solely by the appended claims.
Claims
1. A communication circuit for a serial peripheral interface, characterized in that: include: at least one chip select signal control unit; The chip select signal control unit includes at least two input terminals and two output terminals, and the output terminals of the chip select signal control unit are connected to a plurality of slave devices in a one-to-one correspondence; the first input terminal of the chip select signal control unit is connected to the chip select interface of the master device, and the second input terminal is connected to the universal input and output interface of the master device; The chip select signal control unit is used to control the output level of each of the output terminals according to the signals output by the chip select interface of the master device and the universal input / output interface.
2. The communication circuit of the serial peripheral interface according to claim 1, characterized in that: The chip select signal control unit also includes a first resistor and a diode, one end of the first resistor is connected to the first input end of the chip select signal control unit, and the other end is commonly connected to the cathode of the diode and the first slave device, the anode of the diode is connected to the second input end of the chip select signal control unit, and the diode is used to isolate the first signal output by the chip select interface.
3. The communication circuit of the serial peripheral interface according to claim 2, characterized in that: The chip select signal control unit further includes a reverse circuit, a first input end of the reverse circuit being commonly connected to the second input end of the chip select signal control unit and the anode of the diode, and a second input end of the reverse circuit being connected to a first power supply; The first output terminal of the reverse circuit is connected to the second slave device, and the second output terminal of the reverse circuit is grounded; The inverting circuit is controlled to be on or off according to the first signal and a second signal output by the universal input / output interface.
4. The communication circuit of the serial peripheral interface according to claim 3, characterized in that: The reverse circuit is controlled to be on and off according to the first signal and the second signal output by the universal input and output interface, including: When the first signal is an invalid signal, no matter the second signal is at a low level or a high level, the reverse circuit is not turned on; When the first signal is a valid signal and the second signal is a level signal opposite to that of the first signal, the reverse circuit is turned on; When the first signal is a valid signal and the second signal is a signal of the same level as the first signal, the reverse circuit is not turned on.
5. The communication circuit of the serial peripheral interface according to claim 4, characterized in that: When the reverse circuit is turned on, the master device and the second slave device can communicate normally.
6. The communication circuit of the serial peripheral interface according to any one of claims 3 to 5, characterized in that: The reverse circuit includes a second resistor, a third resistor and a transistor; The base of the transistor is connected to one end of the second resistor, the collector is commonly connected to one end of the third resistor and the second slave device, and the emitter is grounded; The other end of the second resistor is commonly connected to the anode of the diode and the second input end of the chip select signal control unit; The other end of the third resistor is connected to the first power supply.
7. The communication circuit of the serial peripheral interface according to claim 6, characterized in that: The transistor is an NPN transistor.
8. The communication circuit of the serial peripheral interface according to claim 1, characterized in that: The chip select signal control unit further includes a first logic gate circuit, a second logic gate circuit and a third input terminal, the master device is provided with a first universal input and output interface and a second universal input and output interface, and the slave device includes a first slave device and a second slave device; The second input end of the chip select signal control unit is connected to the first universal input / output interface of the master device and the first input end of the first logic gate circuit, the third input end is connected to the second universal input / output interface of the master device and the first input end of the second logic gate circuit, the first output end of the chip select signal control unit is connected to the first slave device, and the second output end of the chip select signal control unit is connected to the second slave device; The second input terminals of the first logic gate circuit and the second logic gate circuit are commonly connected to the first input terminal of the chip select signal control unit.
9. The communication circuit of the serial peripheral interface according to claim 8, characterized in that: When the first signal output by the chip select interface is a valid signal and the second signal output by the first universal input / output interface is the same as the first signal, the master device and the first slave device can communicate normally; When the first signal is a valid signal and the third signal output by the second universal input / output interface is the same as the first signal, the master device and the second slave device can communicate normally.
10. The communication circuit of the serial peripheral interface according to claim 8, characterized in that: When the first signal output by the chip select interface is an invalid signal, the master device does not communicate with either the first slave device or the second slave device.
11. The communication circuit of the serial peripheral interface according to any one of claims 8 to 10, characterized in that: The first logic gate circuit and the second logic gate circuit are identical XOR gate circuits.
12. The communication circuit of the serial peripheral interface according to any one of claims 8 to 10, characterized in that: The first logic gate circuit and the second logic gate circuit are the same OR gate circuit.
13. A communication system of a serial peripheral interface, characterized in that: The invention comprises a master device, a plurality of slave devices and a communication circuit of a serial peripheral interface according to any one of claims 1 to 12, wherein the communication between the master device and each slave device is controlled by output levels output by the communication circuit of the serial peripheral interface.