Device with cover

Abstract

An apparatus with a lid is provided that includes a workpiece, a thermal interface layer disposed on the workpiece, and a lid disposed over the workpiece. A groove is formed in the lower side of the cover. A vertical portion of the thermal interface layer extends into the trench. A base portion of the thermal interface layer is located outside the trench.

Description

Technical Field

[0001] The present disclosure relates to a device having a cover. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. In some devices, multiple dies are stacked vertically to reduce the footprint of the device package and interconnect dies with different process technologies. As the size of active components on the dies shrinks, heat dissipation from the increasingly compact active components can be managed by installing a lid on the stacked dies. The lid protects the dies and provides a path for heat to be transferred away from the dies. Utility Model Content

[0004] The present disclosure provides a device with a cover, comprising: a workpiece; a thermal interface layer disposed above the workpiece; and a cover disposed above the workpiece, wherein a groove is formed on an underside of the cover, wherein a vertically extending portion of the thermal interface layer extends into the groove, and a base portion of the thermal interface layer is located outside the groove.

[0005] The present disclosure provides a device with a lid, comprising: a system-on-a-chip (SOC); a substrate, wherein the SOC is mounted on the substrate; a lid, disposed above the SOC; a thermal interface layer, disposed between the SOC and the lid, wherein the thermal interface layer extends laterally from a first end to a second end; and a dam structure, laterally adjacent to the first end and the second end of the thermal interface layer.

[0006] The present disclosure provides a device having a lid, comprising a workpiece, a thermal interface layer disposed over the workpiece, a lid disposed over the workpiece, and a dam structure. A groove is formed on an underside of the lid, wherein a vertically extending portion of the thermal interface layer extends into the groove and a base portion of the thermal interface layer is located outside the groove. The dam structure includes a first portion and a second portion, wherein the first portion is laterally adjacent to a first end of the thermal interface layer and the second portion is laterally adjacent to a second end of the thermal interface layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1The present disclosure is best understood from the following detailed description when read together. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a schematic top view of a workpiece positioned above a carrier package during a manufacturing stage according to some embodiments;

[0009] Figure 2 According to some embodiments, Figure 1 A schematic top view of a workpiece and a cover above a carrier package;

[0010] Figure 3 According to some embodiments, along Figure 1 and Figure 2 The cross-sectional view is taken along line 3-3;

[0011] Figure 4 According to some embodiments, Figure 3 A focused view of the grooves in the lid;

[0012] Figure 5 According to some embodiments, along Figure 1 and Figure 2 The cross-sectional view is taken along line 5-5;

[0013] Figure 6 According to some embodiments, along Figure 1 and Figure 2 A cross-sectional view taken along line 6-6;

[0014] Figure 7 is similar Figure 3 Schematic cross-sectional view illustrating the structure of the device before the thermal annealing process;

[0015] Figure 8 yes Figure 7 A schematic cross-sectional view of the structure after thermal annealing process;

[0016] Figure 9 is similar Figure 6 Schematic cross-sectional view illustrating the structure of the device before the thermal annealing process;

[0017] Figure 10 yes Figure 9 Schematic cross-sectional view of the structure after thermal annealing process.

[0018]

Explanation of symbols

[0019] 100: Packaged semiconductor devices

[0020] 101: Artifacts

[0021] 104: Connector

[0022] 106: bottom filling material

[0023] 110:IC bare crystal

[0024] 111: Wafer edge

[0025] 112: Interconnection structure

[0026] 113: Gap

[0027] 114: Molding material

[0028] 115: Centerline

[0029] 118: Sealing ring

[0030] 119: Top surface

[0031] 200: Thermal interface layer

[0032] 211: First End

[0033] 212: Second End

[0034] 221: First Edge

[0035] 222: Second Edge

[0036] 298: base part

[0037] 299: Vertical extension

[0038] 300:Substrate

[0039] 301: Top side

[0040] 310: Periphery

[0041] 350: Adhesive

[0042] 400: Dam structure

[0043] 401: First End

[0044] 402: Second End

[0045] 403:Pin

[0046] 404: base part

[0047] 405: Pin

[0048] 411: Part 1

[0049] 412: Part 2

[0050] 431: First Gap

[0051] 432: Second gap

[0052] 500: lid

[0053] 510: Peripheral

[0054] 520: bottom foot

[0055] 521: bottom edge

[0056] 525: Interior Space

[0057] 530: Center part

[0058] 531: lower side

[0059] 538: Top surface

[0060] 539: lower side

[0061] 580: Groove

[0062] 581: Upper part

[0063] 582:lower part

[0064] 583: Sidewall

[0065] 584: Sidewall

[0066] 585: Centerline

[0067] 589: Upper groove surface

[0068] 590: Insert

[0069] 591: lowest surface

[0070] 600: Prominent

[0071] 601: First Prominence

[0072] 602: Second Prominence

[0073] 641: First end

[0074] 642: Second end

[0075] 651: First Edge

[0076] 652: Second Edge

[0077] 698:Top surface

[0078] 699: lowest surface

[0079] W1~W10: Length / Width / Distance

[0080] H1~H8:Thickness / Height / Distance

[0081] L1~L3: Length / distance

[0082] R1: Radius

[0083] 3-3: Line

[0084] 5-5: Line

[0085] 6-6: Line

[0086] X: direction

[0087] Y: direction

[0088] Z: direction DETAILED DESCRIPTION

[0089] The following disclosure provides numerous different embodiments or examples for implementing various features of the subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features, such that the first and second features are not in direct contact. As used herein, "directly above" refers to the vertical alignment of features such that when the upper feature is directly above the lower feature, the vertical axis passes through the two features. On the other hand, "above" refers to the relative height of two features such that when the upper feature is above the lower feature, the upper feature is at a greater relative height than the lower feature. An upper feature positioned above a lower feature may or may not be directly above the lower feature. Furthermore, the disclosure may repeat reference numerals and / or letters throughout the various examples. This repetition is for simplicity and clarity and does not in itself dictate the relationship between the various embodiments and / or configurations discussed.

[0090] Additionally, for ease of description, spatially relative terms such as "directly above," "on," "above," "upper," "top," "lower," "below," "below," "bottom," "side," "positive slope," and "negative slope" may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative terms used herein should likewise be interpreted accordingly.

[0091] All numbers in this specification indicating amounts, proportions, physical properties of materials, and / or uses should be understood as modified by the word "about," unless expressly indicated otherwise. When modifying a numerical value in the specification or claims, "about" indicates a range of accuracy familiar and acceptable to one of ordinary skill in the art. Generally, such an accuracy range is ±10 percent. Thus, "about 10" means between 9 and 11.

[0092] Unless otherwise specified, in certain embodiments herein, a "material layer" is a layer comprising at least 50 wt.% of the specified material, e.g., at least 60 wt.% of the specified material, or at least 75 wt.% of the specified material, or at least 90 wt.% of the specified material. A "material" layer is a layer comprising at least 50 wt.% of the specified material, e.g., at least 60 wt.% of the specified material, at least 75 wt.% of the specified material, at least 90 wt.% of the specified material, or at least 99 wt.% of the specified material. For example, in certain embodiments, each titanium nitride layer and a titanium nitride layer is at least 50 wt.% titanium nitride, at least 60 wt.%, at least 75 wt.% titanium nitride, at least 90 wt.% titanium nitride, or at least 99 wt.% titanium nitride.

[0093] For the sake of brevity, well-known techniques related to the manufacture of semiconductor devices may not be described in detail herein. In addition, the various tasks and processes described herein may be integrated into a more comprehensive program or process having additional functionality not described in detail herein. In particular, the various processes in the manufacture of semiconductor devices are well known, and therefore, for the sake of brevity, many processes will only be briefly mentioned herein or will be omitted entirely without providing well-known process details. A person of ordinary skill in the art will readily understand, after reading this disclosure in its entirety, that the structures disclosed herein can be used with a variety of techniques and can be incorporated into a variety of semiconductor devices and products. In addition, it should be noted that the semiconductor device structure includes a varying number of components, and that a single component shown in the figures may represent multiple components.

[0094] Embodiments will be described with particular reference to bonding a lid, heat sink cover, casing, or the like to a wafer, die, substrate, or other structure. However, other embodiments may also be applied to bonding substrates, packages, structures, or devices, or any combination of integrated circuit devices or components.

[0095] The present disclosure discloses cooling devices, packaged semiconductor devices, and methods for packaging semiconductor devices. The cooling devices can be applied to portable electronic devices such as mobile phones, smartphones, tablet computers, notebook computers, or other applications. The cooling devices can be applied to packaged semiconductor devices, which can include a substrate attached to another substrate, wherein each substrate can be a die, a wafer, a printed circuit board, a package substrate, or the like. The cooling devices can thus cool die-to-die, wafer-to-die, wafer-to-wafer, die or wafer to printed circuit board or package substrate type packages, or the like.

[0096] This embodiment can improve thermal interface material (TIM) coverage and reduce TIM stress. Furthermore, this embodiment can provide a low-stress trench and composite design for trenches and dams to reduce stress in the metal TIM and enhance TIM coverage. This embodiment will be used in high-performance computing (HPC) packaging.

[0097] Will refer to Figures 1 to 10 Embodiments of the present disclosure are described, and variations of the embodiments will also be discussed. A three dimensional integrated circuit (3D IC) package is typically formed by attaching one or more top dies to a carrier die, which is then attached to a package substrate. The dies and substrate are attached by, for example, ball grid arrays (BGAs), land grid arrays (LGAs), solder balls, studs, wire bonds, or other conductive connectors. One or more dies may form a seal ring in a redistribution layer (RDL) around the outer edge of the die. The seal ring may be formed by a metal element extending through a dielectric layer of the redistribution layer. The seal ring prevents the dielectric layer from peeling off, particularly when the die is sawn from the wafer. To ensure that the stacked dies remain connected and that the conductive connections between the dies remain intact, an underfill may be applied between the dies. A lid may be used as a heat sink over the die, and a thermal interface layer may be used between the lid and the underlying components.

[0098] The embodiments described herein improve the process of thermal interface layers. For example, a metal thermal interface layer may melt during the thermal annealing process. The structures and features herein can guide the molten portion of the thermal interface layer to a desired location or desired direction and restrict the molten portion of the thermal interface layer from flowing to an unwanted location or direction. For example, the embodiments herein can provide a groove at the bottom of the cover. The groove provides an open space or area to receive the flow of the molten portion along the thermal interface layer in a vertical direction and reduce the stress on the thermal interface layer. In some embodiments, the cover has downwardly extending protrusions that surround the thermal interface layer in the longitudinal direction and block or inhibit the flow of the molten portion of the thermal interface layer in the longitudinal direction. In some embodiments, a dam structure or structure surrounds the thermal interface layer in the transverse direction and blocks or inhibits the flow of the molten portion of the thermal interface layer in the transverse direction.

[0099] Figure 1 1 is a schematic top view of a packaged semiconductor device 100 during a manufacturing stage according to some embodiments. As shown, the structure includes a thermal interface layer 200. The thermal interface layer 200 has a lateral length W1 extending from a first end 211 to a second end 212 along a lateral direction (i.e., the X direction). In addition, the thermal interface layer 200 has a longitudinal length L1 extending from a first edge 221 to a second edge 222 along a longitudinal direction (i.e., the Y direction). In some embodiments, the thermal interface layer 200 matches the size of a molding-chiplet die, so that the size of the molding-chiplet die has a lateral length W1 and a longitudinal length L1. In some embodiments, the ratio of the lateral length W1 to the longitudinal length L1 (W1 / L1) can be 0.3 to 3. Generally, the coverage area of ​​the metal thermal interface layer 200 is less than or equal to the area of ​​the molding-chiplet die.

[0100] As shown, thermal interface layer 200 is positioned on substrate 300 having a top side 301 and a periphery 310. As shown, adhesive 350 is disposed on top side 301 of substrate 300 along periphery 310.

[0101] exist Figure 1In the embodiment shown, the thermal interface layer 200 is almost completely surrounded by the dam structure 400. Specifically, the dam structure includes a first portion 411 and a second portion 412. Each of the first portion 411 and the second portion 412 can be C-shaped, such as a "blocked C" shape. As shown, each of the first portion 411 and the second portion 412 extends from a first end 401 to a second end 402. Furthermore, each of the first portion 411 and the second portion 412 includes a first laterally extending pin 403, a longitudinally extending base portion 404, and a second laterally extending pin 405. Thus, each of the first portion 411 and the second portion 412 includes a central base portion 404 and a pin 403 and a pin 405 extending from each end of the base portion 404. In the illustrated embodiment, each pin 403 and each pin 405 are substantially perpendicular to the base portion 404. Thus, in the illustrated embodiment, the pins 403 and each pin 405 are parallel to each other. As shown, the pin 403 of each of the first portion 411 and the second portion 412 terminates at its respective first end 401. These first ends 401 are aligned and adjacent to each other. Similarly, the pins 405 of each first portion 411 and second portion 412 terminate at respective second ends 402, which are aligned and adjacent to each other. Other geometric designs of the first portion 411 and second portion 412 are also contemplated.

[0102] The base portion 404 of the first portion 411 of the dam structure 400 is continuous from the first edge 221 to the second edge 222 adjacent to the first end 211 of the thermal interface layer 200. The base portion 404 of the second portion 412 of the dam structure 400 is continuous from the first edge 221 to the second edge 222 adjacent to the second end 212 of the thermal interface layer 200.

[0103] A first gap 431 in the dam structure 400 is defined between the first end 401 of the first portion 411 and the first end 401 of the second portion 412. A second gap 432 in the dam structure 400 is defined between the second end 402 of the first portion 411 and the second end 402 of the second portion 412.

[0104] Figure 2 Explains coverage Figure 1 The base plate 300 is provided with a cover 500. Figure 2 In the embodiment of the present invention, the cover 500 is partially translucent so that features located on the underside of the cover 500 are visible. Specifically, the cover 500 includes a periphery 510 having an annular foot 520. The annular foot 520 extends vertically (i.e., in the Z direction in the following figures) to a bottom edge (not shown). The bottom edge of the foot 520 can be aligned with the bottom edge of the cover 500. Figure 1The cover 500 contacts and adheres the adhesive 350 of the packaged semiconductor device 100. Furthermore, the cover 500 includes protrusions 600. The protrusions 600 include a first protrusion 601 and a second protrusion 602. Each protrusion 600 extends vertically (i.e., in the Z direction in the following figures) to a bottom edge (not shown). Furthermore, each protrusion 600 extends laterally (i.e., in the X direction) from a first end 641 to a second end 642. Furthermore, each protrusion 600 extends longitudinally (i.e., in the Y direction) from a first edge 651 to a second edge 652.

[0105] Figure 3 According to some embodiments, along Figure 1 and Figure 2 The cross-sectional view is taken along line 3-3.

[0106] As shown, the device may be a packaged semiconductor device. For example, packaged semiconductor device 100 includes an integrated circuit die 110 (also referred to as a workpiece) that has been packaged. In some embodiments, integrated circuit die 110 may be a system-on-chip (SOC) or include one or more dies, such as one or more SOCs.

[0107] The packaged semiconductor device 100 includes an interconnect structure 112 coupled to an integrated circuit die 110, and a molding material 114 surrounding the integrated circuit die 110 and covering the interconnect structure 112. In some embodiments, the packaged semiconductor device 100 includes a fan-out structure. For example, the pitch of the conductive wiring of the interconnect structure 112 may be larger than the pitch of the conductive wiring of the integrated circuit die 110. Similarly, the contact pads of the interconnect structure 112 may have a larger footprint than the contacts (not shown) of the integrated circuit die 110. In some embodiments, the packaged semiconductor device 100 includes an integrated fan-out (InFO) device or a wafer level packaging (WLP) device. The packaged semiconductor device 100 may also include other types of packaging.

[0108] The integrated circuit die 110 may include a substrate having circuitry formed therein or thereon. The substrate may include, for example, a doped or undoped bulk silicon or an active layer of a semiconductor-on-insulator (SOI) substrate. The circuitry of the substrate of the integrated circuit die 110 may be any type of circuitry suitable for a particular application. The integrated circuit die 110 may include logic, memory, a processor, or other types of devices. As another example, the circuitry formed within or on the substrate of the integrated circuit die 110 may include various N-type metal-oxide semiconductor (NMOS) and / or P-type metal-oxide semiconductor (PMOS) components, such as transistors, capacitors, resistors, diodes, photodiodes, fuses, etc., interconnected to perform one or more functions. These functions may include memory structures, logic structures, processing structures, sensors, amplifiers, power distribution, input / output circuits, etc. Those skilled in the art will appreciate that the above examples are provided for illustrative purposes to further explain the application of some illustrative embodiments and are not intended to limit the present disclosure in any way. Other circuits may be used as appropriate for a given application. The integrated circuit die 110 is typically manufactured by forming a plurality of integrated circuit dies 110 on a semiconductor wafer and singulating the plurality of integrated circuit dies 110 along scribe lines.

[0109] In some embodiments, the packaging process for the integrated circuit die 110 includes providing a carrier (not shown) and attaching the integrated circuit die 110 to the carrier. The carrier may include a wafer, tape, or other type of support, substrate, or device that can be used as a platform for packaging one or more integrated circuit dies 110 during the packaging process. In some embodiments, for example, after packaging multiple integrated circuit dies 110, the carrier is removed.

[0110] In some embodiments, through holes are also formed (in Figure 3(not shown) above the carrier. For example, the through-holes can be electroplated on a seed layer formed on the carrier. In some embodiments, no through-holes are included. In some embodiments, before or after the plurality of integrated circuit dies 110 are coupled to the carrier, a plurality of through-holes can be formed above the carrier by electroplating, photolithography, or other methods. A seed layer can be deposited above the carrier by an electroplating process, and a patterned mask having a desired pattern for the through-holes is formed above the seed layer. The through-holes are electroplated onto the carrier through the patterned mask and then the patterned mask is removed. The exposed portion of the seed layer is also removed. The through-holes can include copper, copper alloys, or other metals or conductive materials. For example, each package of integrated circuit dies 110 or a group of integrated circuit dies 110 packaged together can include tens or hundreds of through-holes. In some embodiments, the plurality of through-holes provide electrical connections in the vertical direction of the packaged semiconductor device 100. For example, each of the plurality of through-holes can be positioned so that it is coupled to a conductive portion in the interconnect structure 112 to be formed subsequently.

[0111] In some embodiments, a plurality of integrated circuit dies 110 are coupled to a carrier between some of the plurality of through-holes. A die attach film (DAF) (not shown) is provided on the bottom surface of the integrated circuit die 110 to couple the plurality of integrated circuit dies 110 to the carrier. For example, the plurality of integrated circuit dies 110 can be placed on the carrier using a pick-and-place machine or manually. In some embodiments, the plurality of integrated circuit dies 110 are coupled to the carrier and packaged simultaneously. One or two or more integrated circuit dies 110 are later separated along the scribe lines (i.e., the scribe lines of the package or interconnect structure 112) to form a plurality of packaged semiconductor devices 100.

[0112] In some embodiments including through-holes, a molding material 114 is then formed over the carrier, the integrated circuit die 110, and the through-holes. The molding material 114 may include, for example, a molding compound, an insulating material such as an epoxy resin, a filling material, a stress release agent (SRA), an adhesion promoter, other materials, or a combination thereof. In some embodiments, the molding material 114 may include a liquid or gel when applied so that it flows between the multiple integrated circuit dies 110 packaged at the same time and around the through-holes. The molding material 114 is then cured or dried to form a solid. In some embodiments, a molding compound sandwich may be applied during the curing process and plasma treatment process of the molding material 114. In some embodiments, when deposited, the molding material 114 extends over the top surfaces of the multiple integrated circuit dies 110 and the through-holes, and after applying the molding material 114, a planarization process is used to remove the top portion of the molding material 114, for example, using a chemical mechanical polishing (CMP) process, a grinding process, an etching process, or a combination thereof. Other methods may also be used to planarize the molding material 114. During the planarization process of the molding material 114, the top portion of the integrated circuit die 110 and / or the vias may also be removed. In some embodiments, the amount of molding material 114 applied can be controlled to expose the top surface of the integrated circuit die 110 and the vias. Other methods of forming the molding material 114 may also be used.

[0113] An interconnect structure 112 may then be formed over the planarized molding material 114, the integrated circuit die 110, and the vias. In some embodiments, the interconnect structure 112 comprises a redistribution layer or a post-passivation interconnect (PPI). The interconnect structure 112 may include one, two, or more conductive line layers and via layers. Some conductive lines of the interconnect structure 112 are coupled to contact pads (not shown) of the integrated circuit die 110. In some embodiments, the conductive features or wires of the interconnect structure may comprise copper, copper alloys, or other metals formed by electroplating processes, photolithography processes, and / or other methods, formed within one or more layers of insulating material.

[0114] The carrier wafer is then removed. In some embodiments, the plurality of packaged semiconductor devices 100 are separated to form Figure 3 Packaged semiconductor device 100 is shown (e.g., in an inverted view with interconnect structure 112 at the bottom). Packaged semiconductor device 100 can be singulated using a saw or laser (not shown), which can include a blade composed of diamond or other materials. In some embodiments, for example, the semiconductor device can be packaged with one or more carriers.

[0115] In some embodiments, before singulating the plurality of packaged semiconductor devices 100, the interconnect structure 112 includes a first interconnect structure formed on a first side of the integrated circuit die 110, and a second interconnect structure (not shown) formed on a second side of the integrated circuit die 110 in addition to the first interconnect structure. The second side is opposite the first side. For example, the carrier described above may include a first carrier, and after forming the first interconnect structure, the second carrier may be attached to the first interconnect structure. The first carrier is removed. A second interconnect structure is formed on the second side of the integrated circuit die 110, over the through-holes and the molding material 114. The second carrier is then removed, and the packaged semiconductor devices 100 are singulated. In some embodiments, for example, the first interconnect structure 112 and the second interconnect structure provide lateral electrical connections between the plurality of packaged semiconductor devices 100. For the packaged semiconductor devices 100 in some embodiments, the second interconnect structure may include backside routing, while the first interconnect structure includes frontside routing, or vice versa (e.g., relative to the integrated circuit die 110).

[0116] The method of packaging a semiconductor device using one or more carriers described herein is merely an example, and the integrated circuit die 110 may be packaged using different methods or different sequences of packaging processes.

[0117] In some embodiments, as Figure 3As shown, packaged semiconductor device 100 is coupled to a substrate or printed circuit board (PCB) via a plurality of connectors 104. Connectors 104 may comprise a eutectic material, such as solder. Connectors 104 may be arranged in a fully or partially populated ball grid array (BGA). The term "solder" as used herein includes lead-based solders and lead-free solders, such as Pb-Sn compositions used for lead-based solders, lead-free solders including InSb, tin, silver, and copper (SAC) compositions, and other eutectic materials that have a common melting point and form conductive solder connections in electrical applications. For lead-free solders, SAC solders of different compositions may be used, such as SAC 105 (98.5% Sn, 1.0% Ag, 0.5% Cu), SAC 305, and SAC 405. Lead-free conductive materials (e.g., solder balls) may also be formed from SnCu compounds instead of silver (Ag). The lead-free solder of connector 104 may also include tin and silver, or Sn-Ag, instead of copper. In some embodiments, for example, connector 104 may include solder bumps or solder balls. In some embodiments, connector 104 includes a conductive ball having a partial spherical shape. Connector 104 may also include other shapes, such as a non-spherical conductive connector. In some embodiments, connector 104 may include a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition (CVD), or the like. The metal pillar may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the metal pillar. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like, or a combination thereof, and may be formed by an electroplating process. Connector 104 may also be used to couple packaged semiconductor device 100 to other types of devices, such as other packaged semiconductor devices, unpackaged semiconductor devices, or directly in an end application.

[0118] In some embodiments, as Figure 3As shown, the interconnect structure 112 of the packaged semiconductor device 100 is coupled to a PCB or substrate 300 (also referred to as a package carrier) using a plurality of connectors 104. The connectors 104 are coupled between contact pads (not shown) on the PCB or substrate 300 and the contact pads of the interconnect structure 112. The connectors 104 are coupled to the contact pads of the PCB or substrate 300 through the following steps: The connectors 104 are aligned with the contact pads of the PCB or substrate 300. The connectors 104 are heated to the melting point of their eutectic material to reflow the material of the connectors 104. The connector 104 material is cooled, electrically and mechanically coupling the connectors 104 to the contact pads of the PCB or substrate 300, thereby coupling the packaged semiconductor device 100 to the PCB or substrate 300.

[0119] An underfill material 106 may be applied between the plurality of connectors 104 and between the interconnect structure 112 and the PCB or substrate 300. The underfill material 106 may comprise, for example, a material similar to that described for the molding material 114. The underfill material 106 may be dispensed along the edges of the connectors 104 and along one or more sides of the interconnect structure 112. For example, the underfill material 106 may flow to one or more other sides beneath the packaged semiconductor device 100. The underfill material 106 is then cured or allowed to cure. In some embodiments, the underfill material 106 is not included.

[0120] exist Figure 3 In the embodiment, the underfill material 106 may extend laterally in the X direction beyond the first end 211 and the second end 212 by a lateral width W2. In some embodiments, the lateral width W2 is 0 mm to 10 mm.

[0121] like Figure 3 As shown, in some embodiments, a thermal interface layer 200 is applied to the top surface 119 of the integrated circuit die 110 and the top surface of the molding material 114. The thermal interface layer 200 can include a metal such as a solder material. In some embodiments, the thermal interface layer 200 is indium (In) or silver (Ag), or a combination of In and Ag. For example, the thermal interface layer 200 can be 99.99% In, 90% In, and 10% Ag, or can include greater than or equal to 80% Ag.

[0122] For example, the thickness of the thermal interface layer 200 may be from about 20 μm to about 150 μm. The thermal interface layer 200 may also include other materials and sizes. The thermal interface layer 200 may be applied by dispensing on the top surface of the integrated circuit die 110 and the molding material 114. The dispensing process may be performed using automated dispensing equipment that can control the amount and pattern of the thermal interface layer 200, such as a serpentine, spiral, or other pattern, to achieve full coverage and the desired thickness of the thermal interface layer 200 bond line. The thermal interface layer 200 may also be applied using other methods.

[0123] like Figure 3 As further shown, a lid 500 or cooling device is coupled to the thermal interface layer 200 using an automated pick-and-place machine or equipment or other methods. In some embodiments, for example, the lid 500 is coupled to the integrated circuit die 110 or the molding material 114 via the thermal interface layer 200. The lid 500 advantageously provides cooling and heat dissipation from the integrated circuit die 110. In some embodiments, for example, the lid 500 is adapted to dissipate heat from the integrated circuit die 110, the interconnect structure 112, and / or the molding material 114.

[0124] As shown, the lid 500 has a central portion 530 and includes a periphery 510 with an annular foot 520 extending vertically downward, i.e., along the Z-direction, from the central portion 530 to a bottom edge 521. The bottom edge 521 of the foot 520 contacts and adheres to the adhesive 350. The foot 520 defines an interior space 525 enclosed by the lid 500. As shown, the integrated circuit die 110 and the thermal interface layer 200 are housed in the interior space 525.

[0125] like Figure 3 As further shown, the central portion 530 has an underside 539. The underside 539 can be substantially planar. As shown, the underside 539 contacts the thermal interface layer 200.

[0126] In some embodiments, the underside 539 of the central portion 530 of the cover 500 is formed by a groove 580. In addition, an insert 590 is positioned within the groove 580 and only partially fills the groove 580. In some embodiments, the insert 590 is a polymer material. For example, the insert 590 can be a polymer thermal interface layer.

[0127] exist Figure 3In the embodiment, packaged semiconductor device 100 further includes a dam structure 400. As shown, dam structure 400 may include two separate portions: a first portion 411 and a second portion 412. Each of first portion 411 and second portion 412 contacts the underside 539 of lid 500 and the top side 301 of substrate 300. Each of first portion 411 and second portion 412 may contact underfill material 106. As shown, each of first portion 411 and second portion 412 has a lateral width W3 in the X-direction. Furthermore, each of first portion 411 and second portion 412 is a lateral distance W4 from the first end 211 and second end 212 of thermal interface layer 200 in the X-direction.

[0128] In some embodiments, a ratio of lateral distance W4 to underfill lateral width W2 ( W4 / W2 ) is less than or equal to 1.

[0129] In some embodiments, a ratio of the dam lateral width W3 to the lateral distance W4 ( W3 / W4 ) is less than or equal to 1.

[0130] Figure 3 4. A cross-sectional view of FIG. 4 is provided through the base portion 404 of each of the first portion 411 and the second portion 412. As shown, the base portion 404 of the first portion 411 of the dam structure 400 is adjacent to the first end 211 of the thermal interface layer 200, and the base portion 404 of the second portion 412 of the dam structure 400 is adjacent to the second end 212 of the thermal interface layer 200.

[0131] In some embodiments, each of the first portion 411 and the second portion 412 is formed of a polymer thermal interface layer.

[0132] The connector 104 , the underfill material 106 , the interconnect structure 112 , and the integrated circuit die 110 may be collectively referred to as a workpiece 101 located above the substrate 300 .

[0133] Figure 4 A focused cross-sectional view is shown of a groove 580 formed in an underside 539 of a cover 500. As shown, the cover 500 has a top surface 538. Additionally, a central portion 530 of the cover 500 has a vertical thickness H1 extending in the Z direction from the top surface 538 to the underside 539.

[0134] As shown, groove 580 includes an upper portion 581 and a lower portion 582. Upper portion 581 extends vertically downward in the Z direction from upper groove surface 589 along substantially planar sidewalls 583. Lower portion 582 includes curved sidewalls 584. For example, each curved sidewall 584 can be formed to have a radius R1. In some implementations, radius R1 can be 0.025 mm to 0.6 mm.

[0135] Furthermore, the sidewalls 583 in the upper portion 581 of the trench 580 may be spaced apart from each other by a lateral distance W5 in the X direction. A vertical centerline 585 is defined equidistant between the plurality of sidewalls 583 .

[0136] The upper groove surface 589 may be located at a vertical distance H2 in the Z direction from the top surface 538. In other words, the cover 500 has a vertical thickness H2 relative to the groove 580. The vertical thickness H2 is greater than zero and less than the vertical thickness H1.

[0137] like Figure 4 As shown, insert 590 can be located in upper portion 581 of groove 580. More specifically, insert 590 can abut upper groove surface 589. Insert 590 can have a lowest surface 591. Furthermore, insert 590 can have a vertical thickness H3 extending from upper groove surface 589 to lowest surface 591 in the Z-direction. Furthermore, lowest surface 591 of insert 590 can be located above underside 539 at a vertical height H4 in the Z-direction.

[0138] The trench 580 has a total depth equal to the sum of the thickness H3 and the height H4, which is the vertical distance from the upper trench surface 589 to the underside 539. In some embodiments, H3 + H4 is less than H1.

[0139] Figure 4 As shown, each integrated circuit die 110 may include scribe lines and / or an embedded seal ring 118 and may extend laterally in the X-direction to the die edge 111. Furthermore, the die edges 111 may be separated from each other by a gap 113 having a lateral distance W6 in the X-direction (i.e., a die-to-die gap 113). The die-to-die gap 113 is defined by a vertical centerline 115 that is equidistant from each die edge 111. A molding material 114 fills the die-to-die gap 113, such that the thickness of the portion of the molding material 114 between the dies is equal to the lateral distance W6.

[0140] The width W7 may include the inter-die portions of the molding material 114 and the scribe lines and / or embedded seal ring 118 of each integrated circuit die 110 .

[0141] In the illustrated embodiment, the trench 580 can be located directly above the die-to-die gap 113. In some embodiments, the lateral distance in the X direction between the centerline 585 of the trench 580 and the perpendicular centerline 115 of the die-to-die gap 113 is 0 mm to 0.5 mm.

[0142] In some embodiments, the lateral distance W6 of the die-to-die gap 113 is less than the trench width W5. In some embodiments, the trench width W5 is less than or equal to the width W7.

[0143] Figure 5 According to some embodiments, along Figure 1 and Figure 2 As shown, the second gap 432 is defined between the second end 402 of the first portion 411 of the dam structure 400 and the second end 402 of the second portion 412 of the dam structure 400. The second gap 432 has a lateral distance W8 along the X direction.

[0144] Furthermore, the protrusion 600, particularly the second protrusion 602, extends vertically downward from the underside 531 of the cover 500 into the second gap 432 along the Z direction. The protrusion 600 stops at the lowest surface 699. As shown, the protrusion 600 has a transverse width W9 along the X direction from the first end 641 to the second end 642.

[0145] comparison Figure 1 and Figure 5 In some embodiments, the width W9 of the protrusion is greater than zero and less than or equal to the lateral length W1.

[0146] exist Figure 5 In the embodiment, each first end 641 and second end 642 of the protrusion 600 has a transverse distance W10 from the adjacent first portion 411 or second portion 412 along the X direction. In some embodiments, the distance W10 is less than 20 mm.

[0147] Figure 5 The cross-sectional view does not pass through the workpiece including the integrated circuit die 110, the interconnect structure 112 or the thermal interface layer 200. The bottom fill material 106 extends beyond the other workpiece components in the Y direction, so Figure 5 The cross-sectional view of FIG. 1 shows the underfill material 106 . As shown, the underfill material 106 has an uppermost surface 698 .

[0148] A vertical distance H5 in the Z direction is defined between the lowest surface 699 of the protrusion 600 and the uppermost surface 698 of the underfill material 106 .

[0149] Furthermore, the protrusion 600 has a vertical length H6 from the underside 531 to the lowest surface 699 in the Z-direction.

[0150] As shown, the foot 520 extends vertically downward along the Z direction a vertical distance H7 from the lower side 531 to the bottom edge 521. The bottom edge 521 of the foot 520 contacts and is adhered to the adhesive 350. Figure 4 and Figure 5 , it can be seen that the ratio of the cover thickness H1 to the foot length H7 (H1 / H7) is 0 to 2.

[0151] In some embodiments, the vertical length H6 of the protrusion is greater than zero and less than the vertical foot length H7.

[0152] In some embodiments, vertical distance H5 is greater than zero and less than vertical footing length H7.

[0153] Figure 6 According to some embodiments Figure 1 and Figure 2 The cross-sectional view is taken along line 6-6.

[0154] As shown, each of the first protrusion 601 and the second protrusion 602 extends downward from the lower side 531 to a lowermost surface 699. The lowermost surface 699 is located at a vertical distance H8 from the top side 301 of the substrate 300 in the Z direction.

[0155] In some embodiments, vertical distance H8 is greater than zero and less than vertical footing length H7.

[0156] Each of the first protrusions 601 and the second protrusions 602 has a longitudinal length L2, extending from the first edge 651, or outer edge, to the second edge 652, or inner edge, in the Y direction. The longitudinal length L2 is greater than zero. Furthermore, the second edge 652 (inner edge) of each of the first protrusions 601 and the second protrusions 602 is a longitudinal distance L3 from each of the first edge 221 and the second edge 222 of the thermal interface layer 200 in the Y direction.

[0157] In some embodiments, a ratio of the longitudinal distance L3 to the lateral underfill width W2 ( L3 / W2 ) is less than or equal to 1.

[0158] Figures 1 to 6 A schematic diagram showing the assembly of components. Figures 7 to 10 Depicts the deformation and movement of a component during the annealing process.

[0159] Figure 7 For similar Figure 3 A simplified schematic diagram of the device structure prior to the thermal annealing process is shown. As shown, the cap 500 and the trench 580 are positioned above the thermal interface layer 200. The polymer insert partially filling the trench 580 is not shown. However, inserting a polymer into the trench 580 is contemplated. As further shown, the thermal interface layer 200 and the remaining portion of the workpiece are positioned between portions of the dam structure 400.

[0160] Figure 8 yes Figure 7 A schematic cross-sectional view of the structure after thermal annealing. As shown, during the thermal annealing process, substrate 300 and lid 500 may warp. Grooves 580 reduce the rigidity of lid 500, thereby alleviating stress. Furthermore, the polymer dam structure controls the bending of the lid toward the substrate.

[0161] Furthermore, during the thermal annealing process, all or part of the thermal interface layer 200 may melt. As shown, the vertically extending portion 299 of the thermal interface layer 200 may flow into the trench 580, while the base portion 298 of the thermal interface layer 200 remains outside the trench 580. Meanwhile, the dam structure 400 prevents the melted portion of the thermal interface layer 200 from flowing laterally along the X-direction.

[0162] Figure 9 For similar Figure 6 A simplified schematic diagram depicts the device structure prior to the thermal annealing process. As shown, the cover 500 is positioned above the thermal interface layer 200. As further shown, the thermal interface layer 200 and the remaining portion of the workpiece are positioned between a first protrusion 601 and a second protrusion 602. Furthermore, the first and second protrusions 601, 602 are spaced apart from the substrate 300 to facilitate the application of a vacuum during the annealing process, thereby extracting air bubbles from the thermal interface layer 200.

[0163] Figure 10 for Figure 9 A schematic cross-sectional view of the structure after thermal annealing. As shown, during the thermal annealing process, substrate 300 and cover 500 may warp. Furthermore, during the thermal annealing process, all or part of thermal interface layer 200 may melt. First protrusion 601 and second protrusion 602 prevent the melted portion of thermal interface layer 200 from flowing longitudinally along the Y direction.

[0164] As described herein, embodiments provide a cover, such as a cooling structure, that relieves stress on the underlying structure during a thermal annealing process. In addition, such a cover may include, for example, a location for a groove that provides an open space to receive a flow of molten material (e.g., in a longitudinal direction). Thus, the flow of the molten material may be redirected away from an undesired direction. Moreover, such a cover may be provided with a downwardly extending protrusion that restricts the flow of the molten material in the longitudinal direction. In addition, embodiments herein provide a dam structure of a non-metallic material (e.g., a polymeric thermal interface layer) that restricts the flow of the molten material in a lateral direction.

[0165] In one embodiment, a device having a cover includes: a workpiece; a thermal interface layer disposed over the workpiece; and a cover disposed over the workpiece, wherein a groove is formed on an underside of the cover, wherein a vertically extending portion of the thermal interface layer extends into the groove, and a base portion of the thermal interface layer is located outside the groove.

[0166] In some embodiments of the device, the thermal interface layer extends longitudinally from the first edge to the second edge. The cover includes a first protrusion extending downwardly from an underside of the cover, wherein the first protrusion is longitudinally adjacent to the first edge. The cover includes a second protrusion extending downwardly from an underside of the cover, wherein the second protrusion is longitudinally adjacent to the second edge.

[0167] In some embodiments of the device, the thermal interface layer extends laterally from the first end to the second end; and the device further includes a first portion of the dam structure laterally adjacent to the first end of the thermal interface layer, and a second portion of the dam structure laterally adjacent to the second end of the thermal interface layer.

[0168] In some embodiments of the device, the first gap is located between the first portion and the second portion of the dam structure, adjacent to the first edge of the thermal interface layer; the second gap is located between the first portion and the second portion of the dam structure, adjacent to the second edge of the thermal interface layer; the first protrusion extends downwardly into the first gap; and the second protrusion extends downwardly into the second gap.

[0169] In some embodiments of the device, the thermal interface layer is metal and the dam structure is polymer.

[0170] In some embodiments, the workpiece is an integrated circuit die.

[0171] In another embodiment, a device with a lid includes: a system on a chip; a substrate, wherein the system on a chip is mounted on the substrate; a lid, disposed above the system on a chip; a thermal interface layer, disposed between the system on a chip and the lid, wherein the thermal interface layer extends laterally from a first end to a second end; and a dam structure, laterally adjacent to the first end of the thermal interface layer and the second end of the thermal interface layer.

[0172] In some embodiments of the device, the cover has an underside; the substrate has a top side; and the dam structure extends longitudinally from the top side of the substrate to the underside of the cover.

[0173] In some embodiments of the device, the thermal interface layer is metal.

[0174] In some embodiments of the device, the dam structure is a polymer.

[0175] In some embodiments of the device, the thermal interface layer extends longitudinally from a first edge to a second edge; the dam structure includes a first portion laterally adjacent to a first end of the thermal interface layer; the dam structure includes a second portion laterally adjacent to a second end of the thermal interface layer; a first gap is located between the first and second portions of the dam structure, adjacent to the first edge of the thermal interface layer; a second gap is located between the first and second portions of the dam structure, adjacent to the second edge of the thermal interface layer; the cover includes a first protrusion extending downwardly from an underside of the cover into the first gap; and the cover includes a second protrusion extending downwardly from an underside of the cover into the second gap.

[0176] In some embodiments of the apparatus, the lid has an underside; a trench is formed in the underside of the lid above the system on wafer; and the vertically extending portion of the thermal interface layer extends into the trench.

[0177] In some embodiments of the device, the polymer insert material is located in the groove above the vertically extending portion.

[0178] In some embodiments of the device, the thermal interface layer directly contacts the system-on-wafer and the underside of the lid.

[0179] In other embodiments, a method of forming a device having a lid includes positioning a workpiece over a package carrier; disposing a thermal interface layer over the workpiece; positioning a lid over the workpiece, wherein a groove is formed on an underside of the lid and wherein the lid has an annular foot; adhering the foot to the package carrier; and performing a thermal annealing process, wherein during the thermal annealing process, a portion of the thermal interface layer melts and flows into the groove.

[0180] In some embodiments of the method, after disposing the thermal interface layer over the workpiece, the thermal interface layer extends longitudinally from the first edge to the second edge; the cover includes a first protrusion and a second protrusion extending downwardly from an underside of the cover; after adhering the foot to the package carrier, the first protrusion is longitudinally adjacent to the first edge, and the second protrusion is longitudinally adjacent to the second edge; and during the thermal annealing process, the first protrusion and the second protrusion block longitudinal flow of a molten portion of the thermal interface layer.

[0181] In some embodiments, the method further includes applying a vacuum to extract bubbles from the thermal interface layer during the thermal annealing process.

[0182] In some embodiments of the method, after disposing the thermal interface layer over the workpiece, the thermal interface layer extends laterally from the first end to the second end; the method further includes forming a dam structure over the package carrier; after disposing the thermal interface layer over the workpiece, the dam structure is laterally adjacent to the first end of the thermal interface layer and the second end of the thermal interface layer; and during the thermal annealing process, the dam structure blocks the lateral flow of a molten portion of the thermal interface layer.

[0183] In some embodiments, the method further includes partially filling the trench with a polymer insert before positioning the cover over the workpiece.

[0184] In some embodiments of the method, the workpiece includes a first system-on-wafer and a second system-on-wafer separated by a gap; and positioning the cover over the workpiece includes positioning the groove directly over the gap.

[0185] In yet other embodiments, a device having a lid includes a workpiece, a thermal interface layer disposed over the workpiece, a lid disposed over the workpiece, and a dam structure. A groove is formed on an underside of the lid, wherein a vertically extending portion of the thermal interface layer extends into the groove and a base portion of the thermal interface layer is located outside the groove. The dam structure includes a first portion and a second portion, wherein the first portion is laterally adjacent to a first end of the thermal interface layer and the second portion is laterally adjacent to a second end of the thermal interface layer.

[0186] In some embodiments of the device, a first gap is located between the first portion and the second portion of the dam structure, adjacent to the first end of the thermal interface layer; a second gap is located between the first portion and the second portion of the dam structure, adjacent to the second end of the thermal interface layer; and the cover includes a first protrusion extending downwardly into the first gap and a second protrusion extending downwardly into the second gap.

[0187] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of this disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of this disclosure.

Claims

1. A device having a cover, characterized in that include: a workpiece; a thermal interface layer disposed above the workpiece; as well as A cover is disposed above the workpiece, wherein a groove is formed on a lower side of the cover, wherein a vertical extension portion of the thermal interface layer extends into the groove, and a base portion of the thermal interface layer is located outside the groove.

2. The device with a cover according to claim 1, characterized in that in: The thermal interface layer extends longitudinally from a first edge to a second edge; The cover includes a first protrusion extending downwardly from the underside of the cover, wherein the first protrusion is longitudinally adjacent to the first edge; as well as The cover includes a second protrusion extending downwardly from the underside of the cover, wherein the second protrusion is longitudinally adjacent to the second edge.

3. The device with a cover according to claim 2, characterized in that in: The thermal interface layer extends laterally from a first end to a second end; and The device also includes a first portion of a dam structure laterally adjacent to the first end of the thermal interface layer, and a second portion of the dam structure laterally adjacent to the second end of the thermal interface layer.

4. The device with a cover according to claim 3, characterized in that in: a first gap between the first portion and the second portion of the dam structure, adjacent to the first edge of the thermal interface layer; a second gap between the first portion and the second portion of the dam structure, adjacent to the second edge of the thermal interface layer; The first protrusion extends downwardly into the first gap; as well as The second protrusion extends downward into the second gap.

5. The device with a cover according to claim 1, wherein The workpiece is a bare integrated circuit die.

6. A device having a cover, characterized in that include: A system-on-a-chip; a substrate, wherein the system chip is mounted on the substrate; a cover disposed above the system single chip; a thermal interface layer disposed between the system wafer and the cover, wherein the thermal interface layer extends laterally from a first end to a second end; as well as A dam structure is laterally adjacent to the first end of the thermal interface layer and the second end of the thermal interface layer.

7. The device with a cover according to claim 6, wherein in: The cover has a lower side; The substrate has a top side; and The dam structure extends longitudinally from the top side of the base plate to the underside of the cover.

8. The device with a cover according to claim 6, wherein in: The thermal interface layer extends longitudinally from a first edge to a second edge; The dam structure includes a first portion laterally adjacent to the first end of the thermal interface layer; The dam structure includes a second portion laterally adjacent to the second end of the thermal interface layer; a first gap between the first portion and the second portion of the dam structure, adjacent to the first edge of the thermal interface layer; a second gap between the first portion and the second portion of the dam structure, adjacent to the second edge of the thermal interface layer; The cover includes a first protrusion extending downward from a lower side of the cover into the first gap; and The cover includes a second protrusion extending downward from the underside of the cover into the second gap.

9. A device having a cover, characterized in that: include: a workpiece; a thermal interface layer disposed above the workpiece; a cover disposed above the workpiece, wherein a groove is formed on a lower side of the cover, wherein a vertically extending portion of the thermal interface layer extends into the groove, and a base portion of the thermal interface layer is located outside the groove; as well as A dam structure includes a first portion and a second portion. The first portion is laterally adjacent to a first end of the thermal interface layer, and the second portion is laterally adjacent to a second end of the thermal interface layer.

10. The device with a cover according to claim 9, characterized in that in: a first gap between the first portion and the second portion of the dam structure, adjacent to the first end of the thermal interface layer; a second gap between the first portion and the second portion of the dam structure, adjacent to the second end of the thermal interface layer; The cover includes a first protrusion extending downwardly into the first gap and a second protrusion extending downwardly into the second gap.

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