Substrate structure
By stacking chip components in a substrate structure and utilizing conductive connections and a build-up layer structure, the problem of insufficient space in a multi-chip module is solved, and miniaturization and high-density integration of the substrate structure are achieved.
Patent Information
- Application Number
- CN202422535870.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-09-26
- Estimated Expiration
- 2034-10-18
AI Technical Summary
In existing multi-chip modules, multiple chips are tiled in a single layer, resulting in insufficient space utilization and difficulty in miniaturization.
A substrate structure is adopted, and the chip components are stacked along the first direction. The chip components are formed by bonding the conductive parts of the first chip and the second chip, and are embedded in the accommodating cavity of the core board. The protective layer and the conductive column are used for connection, and the layered structure is used to improve the integration.
Without increasing the thickness of the substrate, more chips can be integrated to improve the density and miniaturization of the substrate structure.
Smart Images
Figure CN223390553U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a substrate structure. Background Art
[0002] In recent years, the design of consumer electronics has consistently prioritized lightweight, thin, short, and compact design, driving the trend toward thinner, higher-density chip integration. Multi-chip modules (MCMs) have become widely used in electronic devices. These modules primarily incorporate two or more chips to enhance their electrical performance and efficiency. However, current MCMs utilize a single layer of chips stacked flat within the module, leaving limited room for miniaturization. Utility Model Content
[0003] The purpose of this application is to provide a substrate structure that can solve the technical problem in the prior art that multiple chips are laid out in a multi-chip module in the form of a single-layer chip, and the multi-chip module has limited space for miniaturization.
[0004] In order to solve the above problems, the present application provides a substrate structure, the substrate structure has a first direction, and the substrate structure includes: a core board, the core board has a accommodating cavity extending along the first direction; a chip assembly, arranged in the accommodating cavity of the core board; the chip assembly includes a first chip and a second chip stacked along the first direction, the first chip includes a first main body and a first conductive part arranged on a side of the first main body close to the second chip, the second chip includes a second main body and a second conductive part arranged on a side of the second main body close to the first chip, and the first conductive part and the second conductive part are bonded to each other.
[0005] In some embodiments, the accommodating cavity penetrates the core plate along the first direction.
[0006] In some embodiments, a surface of the first body portion at a side away from the second body portion is flush with a surface of the core plate at one side in the first direction.
[0007] In some embodiments, the substrate structure further includes: a protective layer disposed in the accommodating cavity and covering a side of the first main body portion close to the second main body portion.
[0008] In some embodiments, the protective layer located on the side of the first main body close to the second main body has a first conductive hole extending along the first direction; the substrate structure also includes a first conductive column arranged in the first conductive hole, and the first conductive column is electrically connected to the first conductive part.
[0009] In some embodiments, the substrate structure further includes a conductive electrode disposed on a side of the protection layer away from the first main portion, and the conductive electrode is electrically connected to the first conductive pillar.
[0010] In some embodiments, the core board has a first surface and a second surface in a first direction; the substrate structure also includes: a first core layer circuit, which is arranged on the first surface of the core board and on the surface of the first main body away from the second main body; a second core layer circuit, which is arranged on the second surface of the core board and on the surface of the protective layer away from the first main body, and the second core layer circuit includes a conductive electrode.
[0011] In some embodiments, the substrate structure further includes: at least one build-up layer structure group, each build-up layer structure group includes a first sub-build-up layer structure and a second sub-build-up layer structure, the first sub-build-up layer structure is located on the side of the first surface away from the second surface, and the second sub-build-up layer structure is located on the side of the second surface away from the first surface; the first sub-build-up layer structure includes: a first sub-build-up layer board and a first sub-build-up layer circuit located on the side of the first sub-build-up layer board away from the core board, and the first sub-build-up layer circuit closest to the core board is connected to the first core layer circuit; the second sub-build-up layer structure includes: a second sub-build-up layer board and a second sub-build-up layer circuit located on the side of the second sub-build-up layer board away from the core board, and the second sub-build-up layer circuit closest to the core board is connected to the second core layer circuit.
[0012] In some embodiments, at least one first build-up sub-board is provided with a chip assembly; and / or at least one second build-up sub-board is provided with a chip assembly.
[0013] In some embodiments, the first conductive portion and the second conductive portion are bonded to each other by using one of thermocompression welding, ultrasonic welding, laser welding, conductive adhesive welding, and micro welding.
[0014] The chip assembly of the present application includes a first chip and a second chip stacked along a first direction, and the first main body of the first chip and the second conductive part of the second chip are bonded to each other; the chip assembly is formed by stacking and bonding the first chip and the second chip and then arranged in the accommodating cavity of the core board. Since the overall thickness of the chip assembly is less than the thickness of the core board, more chips can be integrated without affecting the thickness of the substrate structure, thereby improving the density of the substrate structure and realizing the function of miniaturization of the substrate structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0016] Figure 1 is a schematic diagram of the substrate structure of Example 1 of the present application;
[0017] Figure 2is a schematic diagram of the substrate structure of Example 2 of the present application;
[0018] Figure 3 is a schematic diagram of the substrate structure of Example 3 of the present application;
[0019] Figure 4 It is a schematic diagram of the substrate structure of Example 4 of the present application.
[0020] Description of reference numerals:
[0021] 1. Chip assembly; 2. Protective layer; 3. First conductive column; 4. Core board; 5. First core layer circuit; 6. Second core layer circuit; 7. Build-up structure group; 8. Conductive electrode; 9. First conductive hole; 10. Accommodation cavity;
[0022] 110. First chip; 111. First main body; 112. First conductive portion;
[0023] 120, second chip; 121, second main body; 122, second conductive part;
[0024] 410, first surface; 420, second surface;
[0025] 710, first sub-build-up layer structure; 711, first sub-build-up layer board; 712, first sub-build-up layer circuit;
[0026] 720 , second sub-build-up layer structure; 721 , second sub-build-up layer board; 722 , second sub-build-up layer circuit. DETAILED DESCRIPTION
[0027] The following describes in detail the preferred embodiments of the present application in conjunction with the accompanying drawings to fully introduce the technical content of the present application to those skilled in the art, to illustrate that the present application can be implemented, to make the technical content disclosed in the present application clearer, and to make it easier for those skilled in the art to understand how to implement the present application. However, the present application can be embodied in many different forms of embodiments, and the scope of protection of the present application is not limited to the embodiments mentioned herein. The description of the embodiments below is not intended to limit the scope of the present application.
[0028] The directional terms mentioned in this application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate this application, and are not used to limit the scope of protection of this application.
[0029] In the drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for the sake of ease of understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and this application does not limit the size and thickness of each component.
[0030] Example 1
[0031] See also Figure 1 , Figure 1 Schematic diagram of the substrate structure of Example 1 of the present application. The substrate structure has a first direction M and a second direction N intersecting the first direction M. In this embodiment, the first direction M and the second direction N are perpendicular to each other. In other embodiments, the first direction M may not be perpendicular to the second direction N. The substrate structure in the embodiment of the present application may also be referred to as a chip-embedded substrate.
[0032] See also Figure 1 The substrate structure includes: a chip component 1, a protective layer 2, a first conductive column 3, a core board 4, a first core layer circuit 5, a second core layer circuit 6 and a build-up layer structure group 7, a conductive electrode 8, a first conductive hole 9 and an accommodating cavity 10.
[0033] See also Figure 1 The chip assembly 1 includes a first chip 110 and a second chip 120 stacked along a first direction M. In this embodiment, the second chip 120 is located above the first chip 110. In other embodiments, the first chip 110 may also be located above the second chip 120.
[0034] The first chip 110 includes a first main body portion 111 and a first conductive portion 112 disposed on a side of the first main body portion 111 close to the second chip 120 .
[0035] The second chip 120 includes a second main portion 121 and a second conductive portion 122 disposed on a side of the second main portion 121 close to the first chip 110. The first conductive portion 112 and the second conductive portion 122 are bonded to each other. In some embodiments, the first conductive portion 112 and the second conductive portion 122 can be bonded using one of thermocompression welding, ultrasonic welding, laser welding, conductive adhesive welding, and micro welding.
[0036] In some embodiments, the substrate structure further includes: a core board 4 , a first core layer circuit 5 and a second core layer circuit 6 .
[0037] See also Figure 1 The core board 4 has a receiving cavity 10 extending along the first direction M, and the chip assembly 1 is arranged in the receiving cavity 10 of the core board 4.
[0038] See also Figure 1In this embodiment, the accommodating cavity 10 passes through the core plate 4 along the first direction M. That is, the accommodating cavity 10 is a through hole that passes through the core plate 4. In other embodiments, the accommodating cavity 10 may be a groove that does not pass through the core plate 4.
[0039] In some embodiments, the surface of the first body portion 111 away from the second body portion 121 is flush with the surface of the core plate 4 in the first direction M. Specifically, the core plate 4 has a first surface 410 and a second surface 420 in the first direction M. Figure 1 In this embodiment, the first surface 410 is the lower surface of the core board 4, and the second surface 420 is the upper surface of the core board 4. The first surface 410 is flush with the surface of the first main body 111 on the side away from the second main body 121, thereby providing a flat surface for the preparation of the first core layer circuit 5.
[0040] See also Figure 1 The protective layer 2 is disposed within the accommodating cavity 10 and covers the side of the first main body 111 near the second main body 121. The protective layer 2 protects the chip assembly 1 from external damage and from water and oxygen intrusion. In some embodiments, the surface of the protective layer 2 facing away from the first main body 111 is flush with the second surface 420, thereby providing a smooth surface for the preparation of the second core circuit 6.
[0041] See also Figure 1 The protective layer 2 located on the side of the first main portion 111 close to the second main portion 121 has a first conductive via 9 extending along the first direction M. In this embodiment, the first conductive via 9 penetrates the protective layer 2 located on the side of the first conductive portion 112 away from the first main portion 111. In other words, the surface of the first conductive via 9 close to the first main portion 111 is flush with the surface of the first conductive portion 112 away from the first main portion 111.
[0042] See also Figure 1 The first conductive column 3 is disposed in the first conductive hole 9 and electrically connected to the first conductive portion 112. In this embodiment, the surface of the first conductive column 3 close to the first main portion 111 is electrically connected to the surface of the first conductive portion 112 away from the first main portion 111.
[0043] See also Figure 1 The conductive electrode 8 is disposed on the side of the protective layer 2 away from the first main portion 111. In this embodiment, the conductive electrode 8 is made of copper. In other embodiments, the conductive electrode 8 may be made of other conductive materials. The conductive electrode 8 is electrically connected to the first conductive pillar 3. In this embodiment, the surface of the first conductive pillar 3 away from the first main portion 111 is electrically connected to the surface of the conductive electrode 8 near the first main portion 111.
[0044] See also Figure 1 The first core layer circuit 5 is arranged on the first surface 410 of the core board 4 and on the surface of the first main body portion 111 away from the second main body portion 121 .
[0045] See also Figure 1 The second core circuit 6 is provided on the second surface 420 of the core board 4 and on the surface of the protective layer 2 away from the first main body 111. The second core circuit 6 includes a conductive electrode 8. In other words, the second core circuit 6 and the conductive electrode 8 are integrally formed.
[0046] In some embodiments, the substrate structure further includes at least one build-up layer structure group 7. Figure 1 In this embodiment, the substrate structure includes a build-up layer structure group 7 .
[0047] Each build-up layer structure group 7 includes a first sub-build-up layer structure 710 and a second sub-build-up layer structure 720 .
[0048] The first sub-build-up layer structure 710 is located on a side of the first surface 410 away from the second surface 420. The first sub-build-up layer structure 710 includes a first sub-build-up layer board 711 and a first sub-build-up layer circuit 712 located on a side of the first sub-build-up layer board 711 away from the core board 4. The first sub-build-up layer circuit 712 closest to the core board 4 is connected to the first core layer circuit 5.
[0049] The second sub-build-up layer structure 720 is located on a side of the second surface 420 away from the first surface 410. The second sub-build-up layer structure 720 includes a second sub-build-up layer board 721 and a second sub-build-up layer circuit 722 located on a side of the second sub-build-up layer board 721 away from the core board 4. The second sub-build-up layer circuit 722 closest to the core board 4 is connected to the second core layer circuit 6.
[0050] See also Figure 1 In this embodiment, neither the first sub-build-up board 711 nor the second sub-build-up board 721 is provided with a chip assembly 1. In other embodiments, at least one first sub-build-up board 711 is provided with a chip assembly 1; and / or at least one second sub-build-up board 721 is provided with a chip assembly 1. Specifically, depending on actual circumstances and requirements, the chip assembly 1 can be provided in the first sub-build-up board 711, the second sub-build-up board 721, or both.
[0051] Through the above scheme, the present application forms a chip assembly 1 by stacking and bonding the first chip 110 and the second chip 120, and then arranges it in the accommodating cavity 10 of the core board 4. Since the thickness of the chip assembly 1 is less than the thickness of the core board 4, the chip assembly 1 is embedded in the core board 4. On the basis of not affecting the thickness of the substrate structure, more chips can be integrated, the density of the substrate structure can be improved, and the function of miniaturization of the substrate structure can be realized.
[0052] Example 2
[0053] See also Figure 2 , Figure 2 Schematic diagram of the substrate structure of Example 2 of the present application. This embodiment includes most of the technical features of Example 1. The difference between this embodiment and Example 1 is that in this embodiment, the first chip 110 is arranged above the second chip 120. The first surface 410 is the upper surface of the core board 4, and the first surface 410 is flush with the surface of the first main body 111 on the side away from the second main body 121. The second surface 420 is the lower surface of the core board 4, and the second surface 420 is flush with the surface of the protective layer 2 on the side away from the first main body 111.
[0054] Through the above scheme, the present application forms a chip assembly 1 by stacking and bonding the first chip 110 and the second chip 120, and then arranges it in the accommodating cavity 10 of the core board 4. Since the thickness of the chip assembly 1 is less than the thickness of the core board 4, the chip assembly 1 is embedded in the core board 4. On the basis of not affecting the thickness of the substrate structure, more chips can be integrated, the density of the substrate structure can be improved, and the function of miniaturization of the substrate structure can be realized.
[0055] Example 3
[0056] See also Figure 3 , Figure 3 Schematic diagram of the substrate structure of Example 3 of the present application. This embodiment includes most of the technical features of Example 1, and the difference between this embodiment and Example 1 is that: in this embodiment, the substrate structure includes two build-up layer structure groups 7.
[0057] Specifically, the first sub-build-up layer structure 710 of the first build-up layer structure group 7 is located on the side of the first surface 410 away from the second surface 420, and the second sub-build-up layer structure 720 of the first build-up layer structure group 7 is located on the side of the second surface 420 away from the first surface 410; the first sub-build-up layer structure 710 of the second build-up layer structure group 7 is located on the side of the first sub-build-up layer structure 710 of the first build-up layer structure group 7 away from the second surface 420, and the second sub-build-up layer structure 720 of the second build-up layer structure group 7 is located on the side of the second sub-build-up layer structure 720 of the first build-up layer structure group 7 away from the first surface 410.
[0058] Through the above scheme, the present application forms a chip assembly 1 by stacking and bonding the first chip 110 and the second chip 120, and then arranges it in the accommodating cavity 10 of the core board 4. Since the thickness of the chip assembly 1 is less than the thickness of the core board 4, the chip assembly 1 is embedded in the core board 4. On the basis of not affecting the thickness of the substrate structure, more chips can be integrated, the density of the substrate structure can be improved, and the function of miniaturization of the substrate structure can be realized.
[0059] Example 4
[0060] See also Figure 4 , Figure 4 Schematic diagram of the substrate structure of Example 4 of the present application. This embodiment includes most of the technical features of Example 2, and the difference between this embodiment and Example 2 is that: in this embodiment, the substrate structure includes two build-up layer structure groups 7.
[0061] Specifically, the first sub-build-up layer structure 710 of the first build-up layer structure group 7 is located on the side of the first surface 410 away from the second surface 420, and the second sub-build-up layer structure 720 of the first build-up layer structure group 7 is located on the side of the second surface 420 away from the first surface 410; the first sub-build-up layer structure 710 of the second build-up layer structure group 7 is located on the side of the first sub-build-up layer structure 710 of the first build-up layer structure group 7 away from the second surface 420, and the second sub-build-up layer structure 720 of the second build-up layer structure group 7 is located on the side of the second sub-build-up layer structure 720 of the first build-up layer structure group 7 away from the first surface 410.
[0062] Through the above scheme, the present application forms a chip assembly 1 by stacking and bonding the first chip 110 and the second chip 120, and then arranges it in the accommodating cavity 10 of the core board 4. Since the thickness of the chip assembly 1 is less than the thickness of the core board 4, the chip assembly 1 is embedded in the core board 4. On the basis of not affecting the thickness of the substrate structure, more chips can be integrated, the density of the substrate structure can be improved, and the function of miniaturization of the substrate structure can be realized. The above is a detailed introduction to a substrate structure provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of the present application. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A substrate structure, characterized in that: The substrate structure has a first direction (M), and the substrate structure includes: A core plate (4), the core plate (4) having a receiving cavity (10) extending along the first direction (M); A chip assembly (1) is arranged in the accommodating cavity (10) of the core board (4); The chip assembly (1) comprises a first chip (110) and a second chip (120) stacked along the first direction (M), the first chip (110) comprising a first main body portion (111) and a first conductive portion (112) arranged on a side of the first main body portion (111) close to the second chip (120), the second chip (120) comprising a second main body portion (121) and a second conductive portion (122) arranged on a side of the second main body portion (121) close to the first chip (110), and the first conductive portion (112) and the second conductive portion (122) are bonded to each other.
2. The substrate structure according to claim 1, wherein: The accommodating cavity (10) passes through the core plate (4) along the first direction (M).
3. The substrate structure according to claim 2, wherein: The surface of the first main body portion (111) on the side away from the second main body portion (121) is flush with the surface of the core plate (4) on the side in the first direction (M).
4. The substrate structure according to claim 1, wherein: Also includes: A protective layer (2) is disposed in the accommodating cavity (10) and covers a side of the first main body portion (111) close to the second main body portion (121).
5. The substrate structure according to claim 4, characterized in that: The protective layer (2) located on a side of the first main body (111) close to the second main body (121) has a first conductive hole (9) extending along the first direction (M); The substrate structure further comprises a first conductive column (3) disposed in the first conductive hole (9), wherein the first conductive column (3) is electrically connected to the first conductive portion (112).
6. The substrate structure according to claim 5, characterized in that: The substrate structure further comprises a conductive electrode (8) arranged on a side of the protective layer (2) away from the first main body (111), and the conductive electrode (8) is electrically connected to the first conductive column (3).
7. The substrate structure according to claim 6, wherein: The core plate (4) has a first surface (410) and a second surface (420) in the first direction (M); The substrate structure further includes: A first core layer circuit (5) is provided on a first surface (410) of the core plate (4) and on a surface of the first main body portion (111) on a side away from the second main body portion (121); A second core layer circuit (6) is arranged on the second surface (420) of the core plate (4) and on the surface of the protective layer (2) away from the first main body (111), and the second core layer circuit (6) includes the conductive electrode (8).
8. The substrate structure according to claim 7, wherein: Also includes: At least one build-up layer structure group (7), each of the build-up layer structure groups (7) comprising a first sub-build-up layer structure (710) and a second sub-build-up layer structure (720), the first sub-build-up layer structure (710) being located on a side of the first surface (410) away from the second surface (420), and the second sub-build-up layer structure (720) being located on a side of the second surface (420) away from the first surface (410); The first sub-build-up layer structure (710) comprises: a first sub-build-up layer board (711) and a first sub-build-up layer circuit (712) located on a side of the first sub-build-up layer board (711) away from the core board (4), wherein the first sub-build-up layer circuit (712) closest to the core board (4) is connected to the first core layer circuit (5); The second sub-build-up layer structure (720) comprises: a second sub-build-up layer board (721) and a second sub-build-up layer circuit (722) located on a side of the second sub-build-up layer board (721) away from the core board (4), wherein the second sub-build-up layer circuit (722) closest to the core board (4) is connected to the second core layer circuit (6).
9. The substrate structure according to claim 8, wherein: The chip assembly (1) is provided in at least one of the first sub-build-up boards (711); and / or The chip assembly (1) is provided in at least one of the second sub-build-up boards (721).
10. The substrate structure according to claim 1, wherein: The first conductive part (112) and the second conductive part (122) are bonded to each other by using one of hot pressing welding, ultrasonic welding, laser welding, conductive adhesive welding and micro welding.