Semiconductor device and light-emitting substrate

Abstract

The utility model provides a semiconductor device and a light-emitting substrate. The semiconductor device comprises a substrate, a first electrode assembly, a second electrode assembly and a light-emitting structure layer, the first electrode assembly or the second electrode assembly is arranged on the substrate, and the first electrode assembly and the second electrode assembly are arranged in a stacked mode in the direction perpendicular to the substrate. The first electrode assembly and / or the second electrode assembly includes a first electrode and a second electrode. The light emitting structure layer is disposed between the first electrode assembly and the second electrode assembly. The first electrode is in contact with the light-emitting structure layer, and the second electrode is arranged on the light-emitting structure layer in an insulating mode and extends along the circumferential edge of the light-emitting structure layer.

Description

Technical Field

[0001] This article relates to display technology, in particular to a semiconductor device and a light-emitting substrate. Background Art

[0002] Semiconductor light-emitting diode (LED) technology has developed over the past three decades, from initial solid-state lighting power supplies to display backlights and finally LED displays, laying a solid foundation for its wider application. With the advancement of chip manufacturing and packaging technologies, sub-millimeter light-emitting diode (Mini LED) and micro LED (Micro LED) displays have gradually become a hot technology.

[0003] At present, the external quantum efficiency (EQE) of micro-LEDs is not ideal, and the structure of micro-LEDs is not conducive to the detection of electrical and luminescent properties. Utility Model Content

[0004] An embodiment of the present application provides a semiconductor device, including:

[0005] substrate;

[0006] a first electrode assembly and a second electrode assembly, wherein the first electrode assembly or the second electrode assembly is disposed on the substrate, the first electrode assembly and the second electrode assembly are stacked in a direction perpendicular to the substrate, and the first electrode assembly and / or the second electrode assembly comprises a first electrode and a second electrode;

[0007] a light-emitting structure layer, disposed between the first electrode assembly and the second electrode assembly;

[0008] The first electrode contacts the light emitting structure layer, and the second electrode is insulated and disposed on the light emitting structure layer and extends along a circumferential edge of the light emitting structure layer.

[0009] In some exemplary embodiments, an insulating layer is further included, wherein the insulating layer is disposed between the second electrode and the light emitting structure layer, and an orthographic projection of the second electrode on the substrate is located within an orthographic projection of the insulating layer on the substrate.

[0010] In some exemplary embodiments, the insulating layer is disposed on the periphery of the first electrode and is in a ring shape.

[0011] In some exemplary embodiments, an orthographic projection of the insulating layer on the substrate is arranged to overlap with an orthographic projection of the second electrode on the substrate.

[0012] In some exemplary embodiments, the end of the insulating layer away from the first electrode is configured to extend toward a side away from the second electrode in a direction perpendicular to the substrate, and the insulating layer is configured to cover part or all of a sidewall of the light emitting structure layer.

[0013] In some exemplary embodiments, the dimension of the light emitting structure layer in a direction parallel to the substrate is configured to decrease linearly in a direction away from the substrate, and the insulating layer is configured to be trumpet-shaped in a direction perpendicular to the substrate.

[0014] In some exemplary embodiments, the second electrode is located outside the first electrode and forms a ring.

[0015] In some exemplary embodiments, the center of the first electrode is arranged to be collinear with the center of the second electrode in a direction perpendicular to the substrate.

[0016] In some exemplary embodiments, the first electrode and the second electrode are disposed in the same layer.

[0017] In some exemplary embodiments, a ratio of an area of ​​an orthographic projection of the second electrode on the substrate to an area of ​​an orthographic projection of the light emitting structure layer on the substrate is 5% to 20%.

[0018] In some exemplary embodiments, an edge of the second electrode close to the first electrode in a direction parallel to the substrate is set as an inner edge, and an edge of the second electrode far from the first electrode in a direction parallel to the substrate is set as an outer edge;

[0019] The maximum distance between the inner edge and the outer edge is set to L1, the maximum size of the light emitting structure layer in a direction parallel to the substrate is set to L2, and the ratio of L2 to L1 is set to be greater than or equal to 10.

[0020] In some exemplary embodiments, the first electrode assembly includes a first electrode and a second electrode, the second electrode assembly includes a third electrode, and the third electrode is in contact with the light emitting structure layer;

[0021] Alternatively, the second electrode assembly includes a first electrode and a second electrode, the first electrode assembly includes a third electrode, and the third electrode is in contact with the light emitting structure layer;

[0022] Alternatively, the first electrode assembly and the second electrode assembly both include a first electrode and a second electrode.

[0023] In some exemplary embodiments, the light emitting structure layer includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in a direction perpendicular to the substrate;

[0024] The first electrode is disposed on the first semiconductor layer and / or the second semiconductor layer, and the second electrode is disposed to be insulated from the first semiconductor layer and / or the second semiconductor layer.

[0025] The present invention provides a light-emitting substrate, comprising:

[0026] Back panel;

[0027] A plurality of semiconductor devices are arranged at intervals on the backplane, the semiconductor devices including a first electrode assembly, a second electrode assembly and a light-emitting structure layer, the first electrode assembly and the second electrode assembly are stacked in a direction perpendicular to the substrate, the first electrode assembly and / or the second electrode assembly include a first electrode and a second electrode; the light-emitting structure layer is arranged between the first electrode assembly and the second electrode assembly; the first electrode is in contact with the light-emitting structure layer, and the second electrode is insulated and arranged on the light-emitting structure layer and extends along the circumferential edge of the light-emitting structure layer.

[0028] In some exemplary embodiments, a filling layer is further included, wherein the filling layer is disposed on the back plate and fills the space between adjacent semiconductor devices.

[0029] In some exemplary embodiments, first electrodes of a plurality of the semiconductor devices are bonded to the backplane, and second electrodes of adjacent semiconductor devices are electrically connected.

[0030] In some exemplary embodiments, the plurality of semiconductor devices include a first device and a second device;

[0031] The first electrode assembly of the first device and the second electrode assembly of the second device are disposed on the back plate and both include a first electrode and a second electrode;

[0032] The second electrode assembly of the first device is electrically connected to the first electrode assembly of the second device.

[0033] The semiconductor device of the present embodiment includes a second electrode insulated from the light-emitting structure layer, which can reduce the electric field strength at the edge region, thereby reducing the probability of electron-hole edge recombination and improving the external quantum efficiency. The semiconductor device of the present embodiment can achieve contactless electrical detection.

[0034] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0036] Figure 1 is a top view of a semiconductor device according to this exemplary embodiment;

[0037] Figure 2 for Figure 1 AA cross-sectional diagram in FIG;

[0038] Figure 3 is a top view of another semiconductor device according to this exemplary embodiment;

[0039] Figure 4 is a top view of yet another semiconductor device according to this exemplary embodiment;

[0040] Figure 5 is a top view of another semiconductor device according to this exemplary embodiment;

[0041] Figure 6 is a schematic diagram of another semiconductor device according to this exemplary embodiment;

[0042] Figure 7 is a schematic diagram of another semiconductor device according to this exemplary embodiment;

[0043] Figure 8 is a schematic diagram of another semiconductor device according to this exemplary embodiment;

[0044] Figure 9 is a schematic diagram of another semiconductor device according to this exemplary embodiment;

[0045] Figure 10 is a diagram of electric field line distribution of the semiconductor device of this exemplary embodiment;

[0046] Figure 11 is a schematic diagram of the electric field intensity at the edge of the semiconductor device of this exemplary embodiment;

[0047] Figure 12 Schematic diagram of the electric field norm at position C1 of the semiconductor device of this exemplary embodiment;

[0048] Figure 13FIG1 is a schematic diagram of the y component of the electric field intensity at position C1 of the semiconductor device of this exemplary embodiment;

[0049] Figure 14 is a schematic diagram of a light-emitting substrate of this exemplary embodiment;

[0050] Figure 15 is a cross-sectional view of a light-emitting substrate of this exemplary embodiment;

[0051] Figure 16 is a schematic diagram of a method for preparing a light-emitting substrate according to this exemplary embodiment;

[0052] Figure 17 This is a first schematic diagram of preparing a light-emitting substrate according to this exemplary embodiment;

[0053] Figure 18 This is a second schematic diagram of preparing a light-emitting substrate according to this exemplary embodiment;

[0054] Figure 19 is a third schematic diagram of preparing a light-emitting substrate according to this exemplary embodiment;

[0055] Figure 20 is a fourth schematic diagram of preparing a light-emitting substrate according to this exemplary embodiment;

[0056] Figure 21 is a fifth preparation schematic diagram of a light-emitting substrate according to this exemplary embodiment;

[0057] Figure 22 is a sixth preparation schematic diagram of a light-emitting substrate according to this exemplary embodiment;

[0058] Figure 23 is a seventh preparation schematic diagram of a light-emitting substrate according to this exemplary embodiment;

[0059] Figure 24 FIG. 2 is a schematic diagram of another light-emitting substrate according to this exemplary embodiment. DETAILED DESCRIPTION

[0060] This application describes multiple embodiments, but this description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in this application. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0061] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0062] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0063] In some exemplary embodiments, a semiconductor device includes a substrate, a first electrode assembly, a second electrode assembly, and a light-emitting structure layer. The first electrode assembly or the second electrode assembly is disposed on the substrate, the first electrode assembly and the second electrode assembly are stacked in a direction perpendicular to the substrate, and the first electrode assembly and / or the second electrode assembly include a first electrode and a second electrode. The light-emitting structure layer is disposed between the first electrode assembly and the second electrode assembly. The first electrode contacts the light-emitting structure layer, and the second electrode is insulated and disposed on the light-emitting structure layer and extends along a circumferential edge of the light-emitting structure layer.

[0064] In some exemplary embodiments, the semiconductor device further includes an insulating layer disposed between the second electrode and the light emitting structure layer, and an orthographic projection of the second electrode on the substrate is located within an orthographic projection of the insulating layer on the substrate.

[0065] In some exemplary embodiments, one end of the insulating layer away from the first electrode is configured to extend perpendicularly to the substrate toward a side away from the second electrode, and the insulating layer is configured to cover part or all of a sidewall of the light emitting structure layer.

[0066] In some exemplary embodiments, a ratio of an orthographic projection area of ​​the second electrode on the substrate to an orthographic projection area of ​​the light emitting structure layer on the substrate is 5% to 20%.

[0067] In some exemplary embodiments, an edge of the second electrode close to the first electrode in a direction parallel to the substrate is set as an inner edge, and an edge of the second electrode far from the first electrode in a direction parallel to the substrate is set as an outer edge;

[0068] The maximum distance between the inner edge and the outer edge is set to L1, the maximum size of the light emitting structure layer in a direction parallel to the substrate is set to L2, and the ratio of L2 to L1 is set to be greater than or equal to 10.

[0069] Currently, the applicant has discovered that the edge effect of Micro LEDs can cause non-radiative recombination of electrons and holes at the edge of the sidewalls of the light-emitting structure, ultimately leading to a decrease in the external quantum efficiency of the semiconductor device. Electroluminescence detection is an important detection method that can evaluate the electrical and luminescence properties of Micro LEDs. Electroluminescence detection technology mainly includes contact-type detection, which records the electrical and luminescence properties by contacting the two electrodes of the Micro LED with a micro electrical probe and injecting current. Although this method is relatively mature, the detection efficiency is slow and may cause damage to the electrodes and surface of the Micro LED.

[0070] Figure 1 is a top view of a semiconductor device according to this exemplary embodiment. Figure 2 for Figure 1 AA cross-sectional view in FIG, this exemplary embodiment provides a semiconductor device, such as Figure 1 and Figure 2 As shown, the semiconductor device may include a substrate (not shown), a first electrode assembly 200, a second electrode assembly 300, and a light-emitting structure layer 100. The first electrode assembly 200 or the second electrode assembly 300 may be disposed on a substrate (not shown). The first and second electrode assemblies 200 and 300 may be stacked in a direction perpendicular to the substrate (not shown) (i.e., a first direction). The first electrode assembly 200 and / or the second electrode assembly 300 may include a first electrode 401 and a second electrode 402. The light-emitting structure layer 100 may be located between the first and second electrode assemblies 200 and 300. The first electrode 401 may contact the light-emitting structure layer 100, while the second electrode 402 may be insulated and disposed on the light-emitting structure layer 100 and extend along the circumferential edge of the light-emitting structure layer 100. The semiconductor device of this example has the second electrode 402 insulated from the light-emitting structure layer 100. This can reduce the electric field strength at the edge, thereby reducing the probability of electron-hole recombination at the edge and improving the external quantum efficiency. Furthermore, the semiconductor device can implement contactless electrical detection.

[0071] In some exemplary embodiments, Figure 1 and Figure 2As shown, the light-emitting structure layer 100 may include a first semiconductor layer 101, a quantum well layer 102, and a second semiconductor layer 103, stacked in a direction perpendicular to a substrate (not shown) (i.e., a first direction). The material of the first semiconductor layer 101 may include p-type gallium nitride (i.e., P-GaN), a semiconductor material that can be achieved by doping gallium nitride (GaN) with p-type dopants such as magnesium (Mg). The material of the second semiconductor layer 103 may include n-type gallium nitride (i.e., N-GaN), a III / V direct bandgap semiconductor material that can be achieved by doping gallium nitride (GaN) with Group V elements (such as phosphorus, arsenic, and antimony). The quantum well layer 102 may be a multilayer structure fabricated in a semiconductor material. The thickness of the semiconductor device can be the size of the semiconductor device in the first direction, and the thickness of the semiconductor device can be 1 micron to 10 microns. The thickness of the first semiconductor layer 101 can be the size of the first semiconductor layer 101 in the first direction, and the thickness of the first semiconductor layer 101 can be 100 nanometers to 500 nanometers. In this example, the thickness of the first semiconductor layer 101 can be 200 nanometers. The thickness of the quantum well layer 102 can be the size of the quantum well layer 102 in the first direction, and the thickness of the quantum well layer 102 can be 20 nanometers to 300 nanometers. In this example, the thickness of the quantum well layer 102 can be 100 nanometers. The thickness of the second semiconductor layer 103 can be the size of the second semiconductor layer 103 in the first direction, and the thickness of the second semiconductor layer 103 can be 1 micron to 3 microns. In this example, the thickness of the second semiconductor layer 103 can be 2 microns. The first electrode assembly 200 can be located on a side of the first semiconductor layer 101 away from the quantum well layer 102, and the second electrode assembly 300 can be located on a side of the second semiconductor layer 103 away from the quantum well layer 102.

[0072] In some exemplary embodiments, Figure 1 and Figure 2 As shown, the cross-section of the light-emitting structure layer 100 parallel to the substrate is circular, but is not limited thereto. For example, it may be rectangular, diamond-shaped, elliptical, triangular, pentagonal, etc. The light-emitting structure layer 100 stands upright along a first direction, and the sidewalls 104 of the light-emitting structure layer 100 may be the circumferential outer walls of the light-emitting structure layer 100. In some exemplary embodiments, the sidewalls 104 of the light-emitting structure layer 100 extend along the first direction, giving the light-emitting structure layer 100 an overall cylindrical shape. In some exemplary embodiments, the diameter of the light-emitting structure layer 100 may be between 10 and 100 microns. In this example, the diameter of the light-emitting structure layer 100 may be 20 microns.

[0073] In some exemplary embodiments, Figure 1 and Figure 2As shown, the semiconductor device further includes an insulating layer 500, which may be disposed between the second electrode 402 and the light emitting structure layer 100 to provide insulation between the second electrode 402 and the light emitting structure layer 100. The insulating layer 500 may include, but is not limited to, silicon dioxide (SiO2) and may include, for example, an insulating material such as silicon nitride (SiN).

[0074] In some exemplary embodiments, Figure 1 and Figure 2 As shown, the first electrode assembly 200 includes a first electrode 401 and a second electrode 402, and the second electrode assembly 300 includes a third electrode 403. The first electrode 401 can be disposed on the end surface of the first semiconductor layer 101 away from the quantum well layer 102, forming contact with the first semiconductor layer 101, and the first electrode 401 serves as the P electrode of the semiconductor device; the third electrode 403 can be disposed on the end surface of the second semiconductor layer 103 away from the quantum well layer 102 and cover the entire end surface of the second semiconductor layer 103 away from the quantum well layer 102, forming contact with the second semiconductor layer 103, and the third electrode 403 serves as the N electrode of the semiconductor device. The insulating layer 500 can be disposed on the end surface of the first semiconductor layer 101 away from the quantum well layer 102, and the second electrode 402 is located on the end surface of the insulating layer 500 away from the first semiconductor layer 101. The insulating layer 500 separates the second electrode 402 and the light-emitting structure layer 100, so that the second electrode 402 and the light-emitting structure layer 100 do not contact each other.

[0075] In some exemplary embodiments, Figure 1 and Figure 2 As shown, the orthographic projection of the second electrode 402 on the substrate (not shown) is located within the orthographic projection of the insulating layer 500 on the substrate. A first through-hole 501 may be provided in the center of the insulating layer 500, giving the insulating layer 500 an overall annular shape. The first electrode 401 is located within the first through-hole 501, with the insulating layer 500 surrounding the first electrode 401. The second electrode 402 may extend along the first semiconductor layer 101 and form a ring, such that the second electrode 402 is located outside the first electrode. In some exemplary embodiments, the orthographic projection of the insulating layer 500 on the substrate (not shown) may overlap with the orthographic projection of the second electrode 402 on the substrate.

[0076] In some exemplary embodiments, Figure 1 and Figure 2As shown, the first electrode 401 is centrally arranged on the light-emitting structure layer 100, that is, the center of the first electrode 401 and the center of the light-emitting structure layer 100 are collinear in the first direction. The center of the first electrode 401 can be the geometric center of the first electrode 401, and the center of the light-emitting structure layer 100 can be the geometric center of the light-emitting structure layer 100. Moreover, the center of the first electrode 401 can be collinear with the center of the second electrode 402 in the first direction, and the center of the second electrode 402 can be the geometric center of the second electrode 402. In some exemplary embodiments, the first electrode 401 can be circular, such that the center of the first electrode 401 and the center of the ring of the second electrode 402 are collinear in the first direction. In some exemplary embodiments, the first electrode 401 and the second electrode 402 are disposed in the same layer, that is, the first electrode 401 and the second electrode 402 can be formed by a patterning process using the same metal thin film.

[0077] In some exemplary embodiments, Figure 1 and Figure 2 As shown, the edge of the second electrode 402 parallel to the substrate (not shown) and closest to the first electrode 401 can be an inner edge 405, and the edge of the second electrode 402 parallel to the substrate (not shown) and away from the first electrode 401 can be an outer edge 406. The maximum distance between the inner edge 405 and the outer edge 406 can be a first distance (L1). The maximum dimension of the light-emitting structure layer 100 in the second or third direction can be a second distance (L2). The ratio of L2 to L1 is set to be greater than or equal to 10, making the width of the second electrode 402 narrower and preventing the second electrode 402 from affecting the light-emitting area. The second and third directions are both perpendicular to the first direction and perpendicular to each other. The distance from the first electrode 401 to the inner edge 405 in the second direction can be a third distance (L3). The distance from the edge of the first electrode 401 to the inner edge 405 can be equal to the third distance (L3) and the distance in each circumferential direction can be the same. The ratio of the area of ​​the orthographic projection of the second electrode 402 on the substrate (not shown in the figure) to the area of ​​the orthographic projection of the light-emitting structure layer 100 on the substrate (not shown in the figure) is 5% to 20%, which not only avoids the influence of the second electrode 402 on the light-emitting area, but also ensures that the second electrode 402 has a sufficiently large area for contactless electrical inspection.

[0078] Figure 3 is a top view of another semiconductor device according to this exemplary embodiment. Figure 4 is a top view of yet another semiconductor device according to this exemplary embodiment. Figure 5 is a top view of another semiconductor device according to this exemplary embodiment. In some exemplary embodiments, Figures 1 to 5As shown, the first electrode 401 is not limited to a circle, and can be, for example, a rectangle, triangle, ellipse, semicircle, diamond, pentagon, etc.; the second electrode 402 is not limited to a circular ring, and the ring structure of the second electrode 402 can be adjusted according to the shape of the light emitting structure layer 100. For example, if the light emitting structure layer 100 is a cube with a square cross section, the second electrode 402 can be a rectangular ring. In some exemplary embodiments, such as Figure 3 As shown, the first electrode 401 may be rectangular and the second electrode 402 may be a rectangular ring. In some exemplary embodiments, as shown in FIG. Figure 4 As shown, the first electrode 401 may be circular and the second electrode 402 may be a rectangular ring. In some exemplary embodiments, as shown in FIG. Figure 5 As shown, the first electrode 401 may be a rectangle, and the second electrode 402 may be a ring.

[0079] Figure 6 is another schematic diagram of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, as Figure 6 As shown, the second electrode assembly 300 may include a first electrode 401 and a second electrode 402, and the first electrode assembly 200 may include a third electrode 403. The third electrode 403 may be disposed on the end surface of the first semiconductor layer 101 away from the quantum well layer 102 and cover the entire end surface of the first semiconductor layer 101 away from the quantum well layer 102, forming contact with the first semiconductor layer 101. The third electrode 403 serves as the P electrode of the semiconductor device. The first electrode 401 may be disposed on the end surface of the second semiconductor layer 103 away from the quantum well layer 102, forming contact with the second semiconductor layer 103. The first electrode 401 serves as the N electrode of the semiconductor device. The insulating layer 500 may be disposed on the end surface of the second semiconductor layer 103 away from the quantum well layer 102. The second electrode 402 is located on the end surface of the insulating layer 500 away from the second semiconductor layer 103. The insulating layer 500 separates the second electrode 402 from the light emitting structure layer 100, so that the second electrode 402 and the light emitting structure layer 100 do not contact each other.

[0080] Figure 7 is another schematic diagram of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, Figure 7As shown, the first electrode assembly 200 and the second electrode assembly 300 may both include a first electrode 401 and a second electrode 402, that is, the first electrode assembly 200 includes a first electrode 401a and a second electrode 402a, and the second electrode assembly 300 includes a first electrode 401b and a second electrode 402b. The first electrode 401a may be disposed on an end surface of the first semiconductor layer 101 away from the quantum well layer 102, forming contact with the first semiconductor layer 101, and the first electrode 401a serves as the P electrode of the semiconductor device; the first electrode 401b may be disposed on an end surface of the second semiconductor layer 103 away from the quantum well layer 102, forming contact with the second semiconductor layer 103, and the first electrode 401b serves as the N electrode of the semiconductor device. The insulating layer 500 can be located on the first semiconductor layer 101 and the second semiconductor layer 103 respectively, that is, the insulating layer 500a can be located on the end surface of the first semiconductor layer 101 away from the quantum well layer 102, the second electrode 402a is located on the end surface of the insulating layer 500a away from the first semiconductor layer 101, and the insulating layer 500a separates the second electrode 402a and the light-emitting structure layer 100; the insulating layer 500b can be located on the end surface of the second semiconductor layer 103 away from the quantum well layer 102, the second electrode 402b is located on the end surface of the insulating layer 500b away from the second semiconductor layer 103, and the insulating layer 500b separates the second electrode 402b and the light-emitting structure layer 100.

[0081] Figure 8 is another schematic diagram of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, as Figure 8 As shown, one end of the insulating layer 500 away from the first electrode 401 extends in the first direction toward the side away from the second electrode 402 , so that the insulating layer 500 is barrel-shaped, and the insulating layer 500 can cover the sidewall 104 of the light emitting structure layer 100 .

[0082] Figure 9 is another schematic diagram of a semiconductor device according to this exemplary embodiment. In some exemplary embodiments, as Figure 9 As shown, in some exemplary embodiments, the dimension of the light-emitting structure layer 100 in a direction parallel to the substrate is configured to decrease linearly in a direction away from the substrate, so that the light-emitting structure layer 100 forms a right truncated cone, and the sidewall 104 of the light-emitting structure layer 100 can be an inclined curved surface. An end of the insulating layer 500 away from the first electrode 401 can extend in the first direction toward a side away from the second electrode 402. The insulating layer 500 can cover the sidewall 104 of the light-emitting structure layer 100, forming a trumpet shape.

[0083] In some exemplary embodiments, Figure 2As shown, the thickness of the first semiconductor layer 101 may be 200 nanometers, the thickness of the quantum well layer 102 may be 100 nanometers, the thickness of the second semiconductor layer 103 may be 2 micrometers, the value of the second distance (L2) may be 20 micrometers, and voltage is applied to the semiconductor device. Figure 10 is a diagram showing the electric field line distribution of the semiconductor device of this exemplary embodiment, Figure 11 is a schematic diagram of the electric field strength at the edge of the semiconductor device of this exemplary embodiment. Figure 11 In the figure, the horizontal axis is the size of the semiconductor device in the direction parallel to the substrate, the unit of size is micrometer, and the vertical axis is the electric field norm, which can be expressed as , Ex is the electric field intensity in the transverse direction, Ey is the electric field intensity in the longitudinal direction, the longitudinal direction may be the first direction, the transverse direction may be the second direction, the unit of the electric field norm is V / m, the line segment d0 is the electric field norm at the edge of the existing semiconductor device, and the line segment d1 may be the electric field norm at the edge of the semiconductor device of this example. In some exemplary embodiments, a positive voltage is applied to the second electrode 402. In this example, the voltage of the second electrode 402 is 10V, and a voltage of 0V is applied to both the first electrode 401 and the third electrode 403. The electric field lines are distributed as follows: Figure 10 As shown. Figure 10 and Figure 11 As shown, the electric field lines in the quantum well layer below the insulating layer are in the opposite direction, allowing holes to move along the electric field lines while electrons move in the opposite direction. Therefore, it can be assumed that electrons and holes below the insulating layer do not recombine, reducing the probability of electron-hole edge recombination. The probability of electron-hole edge recombination refers to the probability of electrons and holes meeting and recombining at the edge of a semiconductor material. Furthermore, the electric field strength at the edge of the semiconductor device in this example can be 3500 to 4000, which is much lower than the electric field strength at the edge of existing semiconductor devices (approximately 7500 to 10500).

[0084] In some exemplary embodiments, Figure 2 As shown, the voltage applied to the second electrode 402 changes, the first electrode 401 and the third electrode 403 are both applied with 0V voltage, and the monitoring Figure 3 The line C1 position in FIG. 4 is shown in FIG. 5 , wherein the voltage change of the second electrode 402 can vary from -5V to 5V. Figure 12 is a schematic diagram of the electric field norm at position C1 of the semiconductor device of this exemplary embodiment, Figure 13 is a schematic diagram of the y component of the electric field intensity at position C1 of the semiconductor device of this exemplary embodiment, Figure 12 and Figure 13 The horizontal coordinates are all in the second direction. Figure 12 The vertical axis is the electric field norm, Figure 13 The ordinate in is the y-axis component of the electric field intensity. Figure 2 、 Figure 12 and Figure 13 As shown, the electric field norm at the center of the conductor device decreases (i.e. Figure 12 The electric field norm data in the dotted box in the figure), but the y component of the electric field intensity at each voltage remains unchanged, that is, Figure 13 The y component of the electric field intensity at each voltage within the dashed box is the same. When the voltage at the second electrode 402 is less than 0V, the electric field is directed upward, and electrons and holes do not move to the edge. Therefore, by forming an insulating layer and the second electrode 402 at the edge, the problem of non-radiative recombination of electrons and holes at the edge can be solved. The larger the voltage difference between the applied voltage of the second electrode 402 and the first electrode 401, the better. When the second electrode 402 is at 0V, it can be assumed that the light-emitting structure layer below the second electrode 402 is non-luminescent.

[0085] Contactless electroluminescence detection technology is a method for detecting the performance of Micro LEDs, which has the characteristics of high efficiency and high accuracy. Contactless electroluminescence detection technology applies an AC electric field to make Micro LEDs emit light periodically, thereby realizing scanning, contactless electroluminescence detection of millions of Micro LED chips on the wafer. The working principle of contactless electroluminescence detection technology is that when the direction of the external electric field is directed from p-GaN to n-GaN, the electrons in the n-GaN region and the holes in the p-GaN region move in the direction of the quantum well by diffusion motion, and radiative recombination occurs in the quantum well. Contactless electroluminescence detection technology can avoid the problem of inflated yield rate caused by photoluminescence, and at the same time, there is no need to ensure the precise contact between the probe and the semiconductor device, so the inspection speed is the fastest. Contactless electroluminescence detection technology can realize batch detection of Micro LEDs, and will not apply any external force to the Micro LEDs, eliminating additional damage to the chip due to detection. Contactless electroluminescence detection can realize the detection of Micro LED chip arrays, and has high detection efficiency. In some exemplary embodiments, for example Figure 2 The semiconductor device shown is subjected to contactless electrical inspection. At this time, the voltage of the second electrode 402 may be 0V, and a high-frequency AC signal may be provided to the second electrode 402 via an external signal.

[0086] Figure 14 is a schematic diagram of a light-emitting substrate of this exemplary embodiment. Figure 15 is a cross-sectional view of a light emitting substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 14 and Figure 15As shown, the light-emitting substrate includes a backplane 600 and a plurality of semiconductor devices, wherein the plurality of semiconductor devices are spaced apart on the backplane 600, and the space between adjacent semiconductor devices is a first gap P0. The first electrode assemblies 200 of the plurality of semiconductor devices are correspondingly arranged on the backplane 600, wherein the first electrode 401 of the first electrode assembly 200 can be bonded to the key 601 on the backplane 600 to form a bond. The second electrode assemblies 300 of the plurality of semiconductor devices are interconnected so that the plurality of semiconductor devices share a common N electrode. The light-emitting substrate also includes a filling layer 700, which can be located on the backplane 600 and fill the space between adjacent semiconductor devices, that is, fill the first gap P0.

[0087] In some exemplary embodiments, Figure 14 and Figure 15 As shown, the plurality of semiconductor devices may include adjacent first and second devices P1 and P2, with the space between the first and second devices P1 and P2 being a first gap P0. The first electrodes 401 of the first and second devices P1 and P2 may both be bonded to the backplane 600. The second electrode 402-1 of the first device P1 and the second electrode 402-2 of the second device P2 may be connected via a first connecting wire 404. The second electrodes 402 of other adjacent semiconductor devices may also be connected via connecting wires, so that the second electrodes 402 of all semiconductor devices are connected together and can be simultaneously provided with a potential via a peripheral circuit board.

[0088] Figure 16 is a schematic diagram of a method for preparing a light-emitting substrate according to this exemplary embodiment. Figure 17 This is a first schematic diagram of preparing a light-emitting substrate according to this exemplary embodiment. Figure 18 is a second preparation schematic diagram of a light-emitting substrate of this exemplary embodiment, Figure 19 is a third schematic diagram of preparing a light-emitting substrate according to this exemplary embodiment. Figure 20 is a fourth preparation schematic diagram of a light-emitting substrate of this exemplary embodiment, Figure 21 is a fifth preparation schematic diagram of a light-emitting substrate of this exemplary embodiment, Figure 22 is a sixth preparation schematic diagram of a light-emitting substrate of this exemplary embodiment, Figure 23 FIG7 is a seventh schematic diagram of a light-emitting substrate of this exemplary embodiment. In some exemplary embodiments, a method for preparing a light-emitting substrate can be applied to, for example, FIG14 and FIG15. Figure 15 The light-emitting substrate shown in the figure has a preparation method comprising:

[0089] In step S1 , a stacked structure 900 is formed on a first substrate 801 .

[0090] In some exemplary embodiments, Figure 17As shown, a stacked structure 900 is formed on a first substrate 801, including: sequentially growing a first semiconductor film 901, a second semiconductor film 902, and a third semiconductor film 903 on the first substrate 801. The first substrate 801 may be a sapphire substrate. The material of the first semiconductor film 901 may include N-type gallium nitride, the material of the second semiconductor film 902 may include a III-V semiconductor material, a II-VI semiconductor material, a IV-VI semiconductor material, or a Group IV semiconductor material, and the material of the third semiconductor film 903 may include P-type gallium nitride. The first semiconductor film 901, the second semiconductor film 902, and the third semiconductor film 903 may constitute the stacked structure 900.

[0091] Step S2 , transferring the stacked structure 900 onto the second substrate 802 .

[0092] In some exemplary embodiments, transferring the stack structure 900 to the second substrate includes: moving the stack structure 900 to the second substrate 802 through transfer, wherein the first semiconductor film 901 of the stack structure 900 is located on the second substrate 802 .

[0093] Step S3 , etching to form the light emitting structure layer 100 .

[0094] In some exemplary embodiments, Figure 18 As shown, etching to form the light emitting structure layer 100 includes: etching the stacked structure 900 to form a notch 904 on the stacked structure 900 so that the stacked structure 900 is pixelated, and the notch 904 separates the plurality of light emitting structure layers 100 .

[0095] Step S4: depositing an insulating film 904.

[0096] In some exemplary embodiments, Figure 18 and Figure 19 As shown, depositing an insulating film 904 includes depositing an insulating film 904 on the light-emitting structure layer 100. The insulating film 904 may be made of silicon dioxide. The insulating film 904 covers the sidewalls of the light-emitting structure layer 100 and the end surface of the light-emitting structure layer 100 away from the second substrate 802. The space between adjacent light-emitting structure layers 100 may be a first gap P0. Furthermore, before depositing the insulating film 904, the sidewalls of the light-emitting structure layer 100 may be repaired.

[0097] Step S5: depositing a filling layer 700 .

[0098] In some exemplary embodiments, Figure 19 and Figure 20As shown, depositing a filling layer 700 includes: depositing the filling layer 700 on the second substrate 802, wherein the filling layer 700 can fill the space between adjacent light emitting structure layers 100. The material of the filling layer 700 may include silicon dioxide, and the end surface of the filling layer 700 away from the second substrate 802 may be flush with the end surface of the insulating film 904 away from the second substrate 802, so that the filling layer 700 smoothes the end surface away from the second substrate 802.

[0099] Step S6 , performing a patterning process on the insulating film 904 .

[0100] In some exemplary embodiments, Figure 20 and Figure 21 As shown, the insulating film 904 is patterned, including: etching the insulating film 904 to form an insulating pattern, the insulating pattern including the insulating layer 500 and the first through hole 501 , and the insulating layer 500 surrounds the first through hole 501 for accommodating the first electrode 401 .

[0101] Step S7 , forming the first electrode assembly 200 and the first connecting line 404 .

[0102] In some exemplary embodiments, Figure 21 and Figure 22 As shown, forming the first electrode assembly 200 and the first connecting line 404 includes: depositing a first conductive film, and then patterning the first conductive film, that is, etching the first conductive film to form the first electrode 401, the second electrode 402 and the first connecting line 404.

[0103] Step S8: bonding the backplane 600.

[0104] In some exemplary embodiments, Figure 22 and Figure 23 As shown, bonding the back plate 600 includes: flipping the structure formed in step S7 and then bonding it to the back plate 600. The first electrodes 401 can contact the keys 601 on the back plate 600 in a one-to-one correspondence to form a bond.

[0105] Step S9: forming a second electrode assembly.

[0106] In some exemplary embodiments, Figure 23 As shown, forming the second electrode assembly includes: depositing a second conductive film on the end surface of the light emitting structure layer 100 away from the back plate to form the second electrode assembly.

[0107] Figure 24 is a schematic diagram of another light-emitting substrate of this exemplary embodiment. In some exemplary embodiments, as Figure 24As shown, the plurality of semiconductor devices may include adjacent first and second devices P1 and P2. The space between the first and second devices P1 and P2 may be a first gap, and the first and second devices P1 and P2 may be connected in series. The first electrode assembly 200-1 of the first device P1 may be bonded to the backplate 600, and the second electrode assembly 300-1 of the first device P1 may be located on a side away from the backplate 600. The second electrode assembly 300-2 of the second device P2 may be bonded to the backplate 600, and the first electrode assembly 200-2 of the second device P2 may be located on a side away from the backplate 600. The first electrode assembly 200-1 of the first device P1 includes a first electrode 401-1 and a second electrode 402-1. The second electrode assembly 300-1 of the first device P1 includes a third electrode 403-1. The first electrode 401-1 of the first device P1 may be bonded to the backplate 600, and the third electrode 403-1 of the first device P1 may be located on a side away from the backplate 600. The second electrode assembly 300-2 of the second device P2 includes a first electrode 401-2 and a second electrode 402-2, the first electrode assembly 200-2 of the second device P2 includes a third electrode 403-2, the first electrode 401-2 of the second device P2 can be bonded to the backplate 600, and the third electrode 403-2 of the second device P2 can be on the side away from the backplate 600.

[0108] In some exemplary embodiments, Figure 24 As shown, on the side close to the backplane 600, the second electrode 402-1 in the first electrode assembly 200-1 of the first device P1 can be connected to the second electrode 402-1 in the second electrode assembly 300-1 of the second device P2 via a first connecting wire 404. On the side away from the backplane 600, the third electrode 403-1 in the second electrode assembly 300-1 of the first device P1 can be connected to the third electrode 402-2 in the first electrode assembly 200-2 of the second device P2 via a second connecting wire 407. When performing contactless electrical testing on the light-emitting substrate of this example, the first electrode of the first device P1 is grounded, and the first electrode of the second device P2 is connected to a sinusoidal signal, thereby enabling testing of two semiconductor devices at a time. This is not limited to two semiconductor devices; for example, multiple semiconductor devices can be connected in series, allowing simultaneous testing of multiple semiconductor devices during contactless electrical testing.

[0109] In some exemplary embodiments, a display device includes the aforementioned light-emitting substrate. The display device provided by the embodiments of the present disclosure can be applied to electronic devices, such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation systems, and in-vehicle displays. It can also be any product or component with a display function, such as a wearable device, such as a smartwatch, smart bracelet, smart glasses, smart headphones, smart clothing, and head-mounted displays.

[0110] An embodiment of the present application provides a light-emitting substrate, including a backplane and a plurality of semiconductor devices, wherein the plurality of semiconductor devices are arranged at intervals on the backplane, the semiconductor devices including a first electrode assembly, a second electrode assembly and a light-emitting structure layer, the first electrode assembly and the second electrode assembly are stacked in a direction perpendicular to the substrate, the first electrode assembly and / or the second electrode assembly including a first electrode and a second electrode; the light-emitting structure layer is arranged between the first electrode assembly and the second electrode assembly; the first electrode is in contact with the light-emitting structure layer, and the second electrode is insulated and arranged on the light-emitting structure layer and extends along the circumferential edge of the light-emitting structure layer.

[0111] In some exemplary embodiments, a filling layer is further included, wherein the filling layer is disposed on the back plate and fills the space between adjacent semiconductor devices.

[0112] In some exemplary embodiments, first electrodes of a plurality of semiconductor devices are bonded to a backplane, and second electrodes of adjacent semiconductor devices are electrically connected.

[0113] In some exemplary embodiments, the plurality of semiconductor devices include a first device and a second device. A first electrode assembly of the first device and a second electrode assembly of the second device are disposed on a backplane and both include a first electrode and a second electrode. The second electrode assembly of the first device and the first electrode assembly of the second device are electrically connected.

[0114] The present invention provides a method for preparing a light-emitting substrate, comprising:

[0115] A light-emitting structure layer, a first electrode assembly and a second electrode assembly are formed in sequence, the first electrode assembly and the second electrode assembly are stacked in a direction perpendicular to the substrate, and the first electrode assembly and / or the second electrode assembly include a first electrode and a second electrode; the light-emitting structure layer is arranged between the first electrode assembly and the second electrode assembly; the first electrode is in contact with the light-emitting structure layer, and the second electrode is insulated and arranged on the light-emitting structure layer and extends along the circumferential edge of the light-emitting structure layer.

[0116] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0117] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features being referred to. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include at least one of the features.

[0118] In the description of the present application, “a plurality of” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0119] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can mean mechanical connection or electrical connection; it can mean direct connection or indirect connection through an intermediate medium; it can mean internal communication between two elements or interaction between two elements, unless otherwise specified. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0120] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it can mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it can mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it can mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0121] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0122] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; a first electrode assembly and a second electrode assembly, wherein the first electrode assembly or the second electrode assembly is disposed on the substrate, the first electrode assembly and the second electrode assembly are stacked in a direction perpendicular to the substrate, and the first electrode assembly and / or the second electrode assembly comprises a first electrode and a second electrode; a light-emitting structure layer, disposed between the first electrode assembly and the second electrode assembly; The first electrode contacts the light emitting structure layer, and the second electrode is insulated and disposed on the light emitting structure layer and extends along a circumferential edge of the light emitting structure layer.

2. The semiconductor device according to claim 1, wherein The device further includes an insulating layer, which is arranged between the second electrode and the light emitting structure layer. The orthographic projection of the second electrode on the substrate is located within the orthographic projection of the insulating layer on the substrate.

3. The semiconductor device according to claim 2, wherein The insulating layer is arranged on the periphery of the first electrode and is in a ring shape.

4. The semiconductor device according to claim 3, wherein The orthographic projection of the insulating layer on the substrate is arranged to overlap with the orthographic projection of the second electrode on the substrate.

5. The semiconductor device according to claim 2, wherein One end of the insulating layer away from the first electrode is configured to extend in a direction perpendicular to the substrate toward a side away from the second electrode, and the insulating layer is configured to cover part or all of a side wall of the light emitting structure layer.

6. The semiconductor device according to claim 5, wherein The size of the light emitting structure layer in a direction parallel to the substrate is configured to decrease linearly in a direction away from the substrate, and the insulating layer is configured to be trumpet-shaped in a direction perpendicular to the substrate.

7. The semiconductor device according to claim 1, wherein The second electrode is located on the periphery of the first electrode and forms a ring.

8. The semiconductor device according to claim 7, wherein: The center of the first electrode is arranged to be collinear with the center of the second electrode in a direction perpendicular to the substrate.

9. The semiconductor device according to claim 7, wherein: The first electrode and the second electrode are arranged in the same layer.

10. The semiconductor device according to claim 7, wherein A ratio of an area of ​​an orthographic projection of the second electrode on the substrate to an area of ​​an orthographic projection of the light emitting structure layer on the substrate is 5% to 20%.

11. The semiconductor device according to claim 7, wherein An edge of the second electrode parallel to the substrate and close to the first electrode is set as an inner edge, and an edge of the second electrode parallel to the substrate and far from the first electrode is set as an outer edge; The maximum distance between the inner edge and the outer edge is set to L1, the maximum size of the light emitting structure layer in a direction parallel to the substrate is set to L2, and the ratio of L2 to L1 is set to be greater than or equal to 10.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that: The first electrode assembly includes a first electrode and a second electrode, the second electrode assembly includes a third electrode, and the third electrode is in contact with the light emitting structure layer; Alternatively, the second electrode assembly includes a first electrode and a second electrode, the first electrode assembly includes a third electrode, and the third electrode is in contact with the light emitting structure layer; Alternatively, the first electrode assembly and the second electrode assembly both include a first electrode and a second electrode.

13. The semiconductor device according to any one of claims 1 to 11, characterized in that: The light emitting structure layer includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked in a direction perpendicular to the substrate; The first electrode is disposed on the first semiconductor layer and / or the second semiconductor layer, and the second electrode is disposed to be insulated from the first semiconductor layer and / or the second semiconductor layer.

14. A light-emitting substrate, characterized in that: include: Back panel; A plurality of semiconductor devices are arranged at intervals on the backplane, the semiconductor devices including a first electrode assembly, a second electrode assembly and a light-emitting structure layer, the first electrode assembly and the second electrode assembly are stacked in a direction perpendicular to the substrate, the first electrode assembly and / or the second electrode assembly include a first electrode and a second electrode; the light-emitting structure layer is arranged between the first electrode assembly and the second electrode assembly; the first electrode is in contact with the light-emitting structure layer, and the second electrode is insulated and arranged on the light-emitting structure layer and extends along the circumferential edge of the light-emitting structure layer.

15. The light emitting substrate according to claim 14, wherein: A filling layer is also included, which is disposed on the back plate and fills the space between adjacent semiconductor devices.

16. The light-emitting substrate according to claim 14, wherein: The first electrodes of the plurality of semiconductor devices are bonded to the backplane, and the second electrodes of adjacent semiconductor devices are electrically connected.

17. The light-emitting substrate according to claim 14, wherein: The plurality of semiconductor devices include a first device and a second device; The first electrode assembly of the first device and the second electrode assembly of the second device are disposed on the back plate and both include a first electrode and a second electrode; The second electrode assembly of the first device is electrically connected to the first electrode assembly of the second device.

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