Testing machine and data receiving device
By introducing a data receiving device into the tester and using the comparison channel unit to realize time division multiplexing of the DR channel, the problem that the DR channel cannot be compared and detected is solved, and the test convenience is improved.
Patent Information
- Application Number
- CN202422598920.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2034-10-25
AI Technical Summary
The DR channel of a traditional tester only has a driving function and cannot perform comparative detection on the output level of the device under test, resulting in low test convenience.
A data receiving device is introduced into the tester. The comparison channel unit adopts time division multiplexing to receive the signals of the DR channel and the IO channel for comparison, and outputs the signals to the data processing module to realize the comparison function of the DR channel.
Without increasing the cost, the testing convenience of the test machine is improved to meet the increasingly higher testing requirements.
Smart Images
Figure CN223401004U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor testing technology, and in particular to a testing machine and a data receiving device. Background Art
[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of devices under test (DUTs), eliminating defective products and ensuring quality control before shipment. Traditional testers use a DR channel with only a drive function, unable to perform comparative testing on the DUT's output levels. This results in limited testing convenience. Utility Model Content
[0003] Based on this, it is necessary to provide a test machine and a data receiving device that can improve the convenience of testing in order to address the above problems.
[0004] In a first aspect, the present application provides a data receiving device, comprising a data processing module and a pin circuit module, wherein the pin circuit module includes a plurality of comparison channel units, the comparison channel units being connected to the data processing module and further connected to a device under test via a DR channel and an IO channel in the same group; the comparison channel units receiving signals from the DR channel / the IO channel in a time-division multiplexing manner for comparison, and outputting corresponding signals to the data processing module.
[0005] In one embodiment, the input even-numbered channels of the pin circuit module are connected to the device under test as IO channels, the input odd-numbered channels of the pin circuit module are connected to the device under test as DR channels, and the output even-numbered channels of the pin circuit module are connected to the data processing module.
[0006] In one embodiment, the comparison channel unit includes a differential comparator, an even comparator and an odd comparator. The input side of the differential comparator is connected to the device under test through a DR channel and an IO channel. The output side of the differential comparator is connected to the even comparator and the odd comparator. The even comparator is connected to the data processing module through an output even channel.
[0007] In one embodiment, the comparison channel unit further includes a PMU unit, and the PMU unit is connected to an IO channel on the input side of the differential comparator.
[0008] In one embodiment, the comparison channel unit further includes an internal control switch, and the PMU unit is connected to the IO channel on the input side of the differential comparator through the internal control switch.
[0009] In one embodiment, the data receiving device further includes a channel control switch connected in series between the DR channel and the IO channel.
[0010] In one embodiment, the data processing module is a PFGA, a CPU or an MCU.
[0011] In one embodiment, the number of the pin circuit modules is more than two.
[0012] A second aspect of the present application provides a testing machine, comprising the above-mentioned data receiving device.
[0013] In one embodiment, the testing machine further includes a communication device connected to the data receiving device.
[0014] The above-mentioned test machine and data receiving device, the comparison channel unit is connected to the device under test through the DR channel and the IO channel, and uses time division multiplexing to receive the signals of the DR channel / IO channel of the same group for comparison, and outputs the corresponding signals to the data processing module, so that the DR channel also has a comparison function, which improves the testing convenience at a low cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 is a structural block diagram of a data receiving device in one embodiment;
[0016] Figure 2 is a structural block diagram of a data receiving device in another embodiment;
[0017] Figure 3 FIG. 1 is a structural principle diagram of a data receiving device in one embodiment. DETAILED DESCRIPTION
[0018] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.
[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.
[0020] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.
[0021] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, operations, components, parts, or combinations thereof.
[0022] In current testers, the DR channel of a PE (Pin Electronic) chip only has a drive function, not a compare function, and is unable to detect the output level of the device under test (DUT). That is, compared to an IO (Input / Output) channel, which has both drive and compare functions, the DR channel only retains the drive function and lacks the compare function. Therefore, the FPGA resources used by a DR channel are approximately 50% of those of an IO channel. If all channels of the PE chip were designed as IO channels, more FPGA internal resources and IO pins would be required, requiring the use of expensive FPGAs, and even increasing the number of FPGAs, thereby increasing hardware costs. Based on this, the data receiving device provided in this application has a pin circuit module that includes several compare channel units. The compare channel units are connected to the device under test via the DR channels and IO channels in the same group, receive signals from the DR channels / IO channels in a time-division multiplexing manner, perform comparisons, and output the corresponding signals to the data processing module. This allows the DR channels to function as IO channels without increasing costs, meeting increasingly stringent testing requirements.
[0023] In one embodiment, Figure 1 As shown, a data receiving device is provided, including a data processing module 110 and a pin circuit module 120, wherein the pin circuit module 120 includes a plurality of comparison channel units 122, the comparison channel units 122 are connected to the data processing module 110, and the comparison channel units 122 are also connected to the device under test (DUT) through the DR channel and IO channel of the same group; the comparison channel units 122 use time division multiplexing to receive signals from the DR channel / IO channel for comparison, and output corresponding signals to the data processing module 110.
[0024] Specifically, the number of pin circuit modules 120 can be one or more, and each pin circuit module 120 includes one or more comparison channel units 122. The data processing module 110, which can utilize a device such as an FPGA, CPU, or MCU, receives the signals output by the comparison channel units 122 after comparison processing, and uses them to analyze parameter indicators of the device under test (DUT). The DR channels and IO channels between the comparison channel units 122 and the device under test (DUT) are grouped together, and the signals are accessed using time-division multiplexing for comparison processing.
[0025] There is no single way to configure DR channels and IO channels. For example, the even-numbered input channels of the pin circuit module 120 can be connected to the device under test (DUT) as IO channels, the odd-numbered input channels of the pin circuit module 120 can be connected to the device under test (DUT) as DR channels, and the even-numbered output channels of the pin circuit module 120 can be connected to the data processing module 110. Based on the positional relationship between the input and output channels of the pin circuit module 120, the even-numbered input channels can be used as IO channels and the odd-numbered input channels can be used as DR channels, with the IO channels and DR channels configured alternately. The comparison channel unit 122 is connected to the device under test (DUT) via the same group of DR channels and IO channels. Signals are input and compared using the principle of time division multiplexing. The odd-numbered input channels are not compared simultaneously with the even-numbered input channels of the same group, enabling the DR channels to perform comparison functions.
[0026] In one embodiment, Figure 2 As shown, the comparison channel unit 122 includes a differential comparator 221, an even comparator 222, and an odd comparator 223. The input side of the differential comparator 221 is connected to the device under test (DUT) via the DR channel and the IO channel. The output side of the differential comparator 221 is connected to the even comparator 222 and the odd comparator 223. The even comparator 222 is connected to the data processing module 110 via the output even channel. During the test process, high and low level comparison thresholds can be set for the even comparator 222 and the odd comparator 223 respectively. After the output signal of the device under test (DUT) is differentially compared by the differential comparator 221, the signal is output to the even comparator 222 and the odd comparator 223. The even comparator 222 and the odd comparator 223 convert the comparison results into digital signals and output them to the FPGA, thereby determining whether the output of the device under test (DUT) is normal.
[0027] Furthermore, the comparison channel unit 122 also includes a PMU (Power Management Unit) unit 224, which is connected to the IO channels on the input side of the differential comparator 221. After the even-numbered input channels of the pin circuit module 120 are set as IO channels and the odd-numbered input channels are set as DR channels, the differential comparators 221 of each comparison channel unit 122 in the pin circuit module 120 first perform a differential comparison of the voltages of the channels in the same group, and then output a signal to the even-numbered comparator 222 corresponding to the IO channel for comparison. When the DR channel requires the comparison function, the IO channel cannot use the comparison function. Specifically, the IO channel is disconnected, and the PMU unit 224 outputs a 0V voltage to the IO channel on the input side of the differential comparator 221, stabilizing the IO channel at 0V. The differential comparator 221 performs a differential comparison between the signal of the DR channel in the same group and the 0V voltage of the IO channel, and then outputs the voltage difference level to the even-numbered comparator 222, thereby implementing the comparison function of the DR channel. It is understood that in other embodiments, when the DR channel needs to use the comparison function, the IO channel can be simply disconnected without the PMU unit 224 outputting a 0V voltage, and the comparison function of the DR channel can also be implemented.
[0028] Furthermore, the comparison channel unit 122 also includes an internal control switch, through which the PMU unit 224 connects to the IO channel on the input side of the differential comparator 221. Furthermore, the data receiving device may also include a channel control switch connected in series with the DR channel and the IO channel. The internal control switch and the channel control switch control the on / off state of the corresponding channels, facilitating testing operations. The internal control switch and the channel control switch may be relays or other types of controlled switches.
[0029] Specifically, if Figure 3As shown, the multiple pin circuit modules 120 are: pin circuit module PE_0 to pin circuit module PE_X. Each pin circuit module 120 includes multiple comparison channel units 122. The first comparison channel unit 122 in each pin circuit module 120 includes a differential comparator 0 / 1_DIFF-COMP, an even comparator CHANNEL_0COMP, an odd comparator CHANNEL_1COMP and a PMU unit PMU_0. The differential comparator 0 / 1_DIFF-COMP is connected to the device under test (DUT) through the IO channel CHANNEL_0 and the DR channel CHANNEL_1. Channel control switches are connected in series to the IO channel CHANNEL_0 and the DR channel CHANNEL_1. The PMU unit PMU_0 is connected to the IO channel CHANNEL_0 through an internal control switch. The last comparison channel unit 122 in each pin circuit module 120 includes a differential comparator M / N_DIFF-COMP, an even comparator CHANNEL_MCOMP, an odd comparator CHANNEL_N COMP, and a PMU unit PMU_M. The differential comparator M / N_DIFF-COMP is connected to the device under test (DUT) through the IO channel CHANNEL_M and the DR channel CHANNEL_N. Channel control switches are connected in series between the IO channel CHANNEL_M and the DR channel CHANNEL_N. The PMU unit PMU_M is connected to the IO channel CHANNEL_M through an internal control switch.
[0030] In order to make the DR channel have the function of IO channel, it is necessary to use the differential comparator of the pin circuit module 120. Figure 3 This example uses IO channels CHANNEL_0 and DR channel CHANNEL_1 in Figure 1 to illustrate how to implement IO functions using differential comparators. The differential comparator 0 / 1_DIFF-COMP compares the voltages of adjacent channels in the same group and then outputs a differential-mode signal, DIFF, to the even-numbered comparator CHANNEL_0COMP and a common-mode signal, CM, to the odd-numbered comparator CHANNEL_1COMP. When the comparison function of DR channel CHANNEL_1 is required, the PMU unit PMU_0 outputs a 0V voltage, which is then connected to IO channel CHANNEL_0 via an internal control switch. The channel control switch in IO channel CHANNEL_0 is then disconnected. The device under test (DUT) outputs a signal to DR channel CHANNEL_1. The differential comparator 0 / 1_DIFF-COMP performs a differential comparison between the DR channel CHANNEL_1 signal and the 0V voltage of IO channel CHANNEL_0. The resulting voltage difference is then output to the even-numbered comparator CHANNEL_0COMP, implementing the comparison function for DR channel CHANNEL_1.
[0031] When a DR channel performs a comparison function, it cannot perform the comparison function simultaneously with the IO channels in the same group. Therefore, during the design process, the IO channels and DR channels of pin circuit module 120 are alternately configured, with the even-numbered channels of pin circuit module 120 configured as IO channels and the odd-numbered channels as DR channels. The differential comparator of pin circuit module 120 and the even-numbered comparator of the even-numbered channels are then used to enable the odd-numbered channels of pin circuit module 120 to function as IO channels. This design approach allows DR channels to function as IO channels, resulting in low cost, high utilization, good results, strong competitiveness, and strong market adaptability, making it very suitable for ATE manufacturers.
[0032] In one embodiment, a test machine is also provided, comprising the above-mentioned data receiving device. The test machine further comprises a communication device connected to the data receiving device, and a host computer connected to the communication device. The host computer may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, and portable wearable devices. The portable wearable devices may be smart watches, smart bracelets, head-mounted devices, etc. The data processing module in the data receiving device is connected to the host computer via the communication device. The data processing module may analyze the signal output by the pin circuit module, obtain the analysis result, and upload it to the host computer via the communication device; the data processing module may also upload the signal output by the pin circuit module to the host computer via the communication device, and the host computer may analyze the received signal to obtain the analysis result.
[0033] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0034] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.
Claims
1. A data receiving device, characterized in that: It includes a data processing module and a pin circuit module, wherein the pin circuit module includes several comparison channel units, the comparison channel units are connected to the data processing module, and the comparison channel units are also connected to the device under test through the DR channel and IO channel of the same group; the comparison channel units use time division multiplexing to receive the signals of the DR channel / the IO channel for comparison, and output corresponding signals to the data processing module.
2. The data receiving device according to claim 1, wherein: The input even-numbered channels of the pin circuit module are connected to the device under test as IO channels, the input odd-numbered channels of the pin circuit module are connected to the device under test as DR channels, and the output even-numbered channels of the pin circuit module are connected to the data processing module.
3. The data receiving device according to claim 2, wherein: The comparison channel unit includes a differential comparator, an even comparator and an odd comparator. The input side of the differential comparator is connected to the device under test through a DR channel and an IO channel. The output side of the differential comparator is connected to the even comparator and the odd comparator. The even comparator is connected to the data processing module through an output even channel.
4. The data receiving device according to claim 3, wherein: The comparison channel unit further includes a PMU unit, and the PMU unit is connected to an IO channel on the input side of the differential comparator.
5. The data receiving device according to claim 4, wherein: The comparison channel unit further includes an internal control switch, and the PMU unit is connected to the IO channel on the input side of the differential comparator through the internal control switch.
6. The data receiving device according to any one of claims 1 to 5, characterized in that: It also includes a channel control switch connected in series with the DR channel and the IO channel.
7. The data receiving device according to any one of claims 1 to 5, characterized in that: The data processing module is PFGA, CPU or MCU.
8. The data receiving device according to any one of claims 1 to 5, characterized in that: The number of the pin circuit modules is more than two.
9. A testing machine, characterized in that: The data receiving device comprises the data receiving device according to any one of claims 1 to 8.
10. The testing machine according to claim 9, characterized in that: The device further comprises a communication device connected to the data receiving device.