Ball grid array (BGA) packaging structure for universal serial bus (USB) 3x controller chip

Abstract

The utility model discloses a BGA packaging structure for a USB3x controller chip, which comprises a BGA substrate and a controller chip, the controller chip is welded at the upper end of the BGA substrate, the outer side of the controller chip is sealed through a plastic packaging layer, and the controller chip is electrically connected with each group of pins of the BGA substrate through bonding metal wires; the BGA substrate is connected with the USB connector; the BGA substrate comprises 60 groups of pins, the 60 groups of pins are uniformly arranged at the bottom of the BGA substrate in a 8 * 8 array, and four pin areas in the center of the array are reserved. According to the utility model, the layout is compact, the occupied space is saved, the pins which need to be externally connected with a filter capacitor or connected with a USB connector are all arranged at the edge position of the pin array, the wiring is smooth, the probability of via hole layer-changing wiring is reduced, and via hole parasitic inductance and capacitance are prevented from causing key signal wiring interference.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic equipment, and in particular to a BGA packaging structure for a USB3x controller chip. Background Art

[0002] USB3x (including USB3.1 Gen1 and USB3.1 Gen2) is the mainstream USB interface storage drive. Its portability and hot-swappable support make it more suitable for plug-and-play storage drive applications. Currently, the mainstream USB3x controller mainly uses the QFN (Quad Flat No-lead Package). The main reason for choosing the QFN package is cost. QFN packaging is a relatively mature and scalable packaging process that uses a lead frame as a carrier. However, as the technology develops, its limitations and shortcomings have become increasingly apparent, even restricting its development.

[0003] However, the QFN package uses an alloy lead frame and lacks a complete reference layer, making it impossible to accurately design equal lengths and control impedance. It is only suitable for products with lower frequencies and cannot meet the requirements of high-speed transmission products. The QFN tin-free ball is only suitable for smaller sizes. When the number of pins is greater than 50 and the size is greater than 6x6mm, coplanar flatness problems will occur, resulting in a decrease in soldering yield and problems such as poor solder creep, floating false solder joints, and parasitic solder beads.

[0004] Therefore, there is an urgent need for a new BGA packaging structure for USB3x controller chips. Utility Model Content

[0005] In view of the above problems, the present invention is proposed to provide a BGA packaging structure for a USB3x controller chip that overcomes the above problems or at least partially solves the above problems.

[0006] The utility model provides a BGA packaging structure for a USB 3x controller chip. The BGA packaging structure for a USB 3x controller chip includes: a BGA substrate and a controller chip. The controller chip is soldered to the upper end of the BGA substrate. The outer side of the controller chip is sealed by a plastic layer. The controller chip and each group of pins of the BGA substrate are electrically connected by bonding wires. The BGA substrate is connected to a USB connector.

[0007] The BGA substrate includes 60 groups of pins, which are evenly arranged in an 8*8 array at the bottom of the BGA substrate, with the central four pin areas of the array left empty; each group of pins on the BGA substrate is provided with a solder ball.

[0008] Optionally, among the 60 groups of pins of the BGA substrate, pin 11 is defined as RX-, pin 12 is defined as AVCCK, pin 13 is defined as TXP, pin 14 is defined as GND, pin 15 is defined as DM, pin 16 is defined as VCCF, pin 17 is defined as VBUS, and pin 18 is defined as VBUS;

[0009] Pin 21 is defined as RX+, pin 22 is defined as RX2+, pin 23 is defined as TXN, pin 24 is defined as VCCK, pin 25 is defined as DP, pin 26 is defined as GND, pin 27 is defined as VCCF, and pin 28 is defined as VCCK;

[0010] Pin 31 is defined as RX2-, pin 32 is defined as TXP2, pin 33 is defined as D0, pin 34 is defined as RB0, pin 35 is defined as GND, pin 36 is defined as GND, pin 37 is defined as LED, and pin 38 is defined as VCCK;

[0011] Pin 41 is defined as TXN2, pin 42 is defined as D2, pin 43 is defined as D1, pin 46 is defined as GND, pin 47 is defined as LX, and pin 48 is defined as GPIO0;

[0012] Pin 51 is defined as D3, pin 52 is defined as DQS, pin 53 is defined as VCCF, pin 56 is defined as CE5, pin 57 is defined as CE6, and pin 58 is defined as LX;

[0013] Pin 61 is defined as DQSn, pin 62 is defined as CE0, pin 63 is defined as CE2, pin 64 is defined as CE3, pin 65 is defined as VCCK, pin 66 is defined as CE4, pin 67 is defined as CE7, and pin 68 is defined as VCCK;

[0014] Pin 71 is defined as D4, pin 72 is defined as D6, pin 73 is defined as CE1, pin 74 is defined as RB1, pin 75 is defined as RE, pin 76 is defined as CLE, pin 77 is defined as WP, and pin 78 is defined as VCCF;

[0015] Pin 81 is defined as D5, pin 82 is defined as D7, pin 83 is defined as WE, pin 84 is defined as REn, pin 85 is defined as ALE, pin 86 is defined as VCCIO, pin 87 is defined as VREF, and pin 88 is defined as V1.2V.

[0016] Optionally, pin 12 is connected to a first filter capacitor.

[0017] Optionally, pin 17 and pin 18 are electrically connected, a third filter capacitor is provided between pin 17 and pin 18, and a resistor is connected in series between pin 18 and the power supply end of the USB connector.

[0018] Optionally, pin 47 and pin 58 are electrically connected, and pin 58 is connected to an inductor.

[0019] Optionally, pin 28 is connected to a fourth filter capacitor, and pin 28 is connected to the inductor.

[0020] Optionally, pin 16, pin 27 and pin 38 are electrically connected, and pin 16 is connected to a second filter capacitor.

[0021] Optionally, pin 76 and pin 87 are electrically connected.

[0022] Optionally, pin 88 is connected to a fifth filter capacitor.

[0023] Optionally, pin 86 is connected to a sixth filter capacitor.

[0024] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0025] The BGA packaging structure for a USB3x controller chip described in an embodiment of the present invention comprises a BGA substrate including 60 groups of pins, which are evenly arranged in an 8*8 array at the bottom of the BGA substrate. The four central pin areas of the array are left empty for via routing, resulting in a compact layout and saving space. Furthermore, pins on the BGA substrate that require external filter capacitors or USB connectors are located at the edge of the pin array, ensuring smooth wiring and reducing the probability of via layer switching. This avoids parasitic inductance and capacitance from causing interference with critical signal routing.

[0026] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1This is a side sectional view of the BGA packaging structure for the USB3x controller chip described in the present invention;

[0029] Figure 2 This is a top view of the BGA packaging structure for the USB3x controller chip described in the present invention;

[0030] Figure 3 This is a wiring diagram of the BGA substrate;

[0031] Figure 4 A reference diagram for defining each pin of the BGA substrate;

[0032] Figure 5 This is a reference schematic diagram comparing the areas of the BGA package structure and the QFN package for the USB3x controller chip described in the present invention.

[0033] Description of reference numerals:

[0034] 1. BGA substrate; 2. Controller chip; 3. Bonding wire; 4. Plastic layer; 5. Solder ball; 6. First filter capacitor; 7. Second filter capacitor; 8. Third filter capacitor; 9. Power supply terminal; 10. Fourth filter capacitor; 11. Inductor; 12. Fifth filter capacitor; 13. Sixth filter capacitor. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings.

[0036] In order to enable those skilled in the art to better understand the present invention, the following will be combined with the accompanying drawings of the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. The accompanying drawings show preferred embodiments of the present invention. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0037] Unless otherwise specified, various raw materials, instruments and equipment used in the present invention can be purchased from the market or prepared by existing methods.

[0038] Figure 1 This is a side sectional view of the BGA packaging structure for the USB3x controller chip described in the present invention. Figure 2 This is a top view of the BGA package structure for the USB3x controller chip described in the present invention, see Figure 1-2As shown, the BGA packaging structure for the USB3x controller chip includes a BGA substrate 1 and a controller chip 2. The controller chip 2 is a USB3x controller chip. The controller chip 2 is soldered to the upper end of the BGA substrate 1. The outer side of the controller chip 2 is sealed by a plastic sealing layer 4. The plastic sealing layer 4 is made by plastic sealing with plastic sealing glue. The controller chip 2 and each group of pins of the BGA substrate 1 are electrically connected through bonding metal wires 3; the BGA substrate 1 is connected to the USB connector.

[0039] Figure 3 This is the wiring diagram of BGA substrate 1, combined with Figure 3 As shown, the BGA substrate 1 includes 60 groups of pins, which are evenly arranged in an 8*8 array at the bottom of the BGA substrate 1. The central 4 pin areas of the array are left empty for via routing; each group of pins on the BGA substrate 1 is provided with a solder ball 5 to improve the soldering yield.

[0040] Figure 4 This is a reference diagram for defining each pin of the BGA substrate 1, combined with Figure 4 As shown, among the 60 groups of pins of the BGA substrate 1, pin 11 is defined as RX-, pin 12 is defined as AVCCK, pin 13 is defined as TXP, pin 14 is defined as GND, pin 15 is defined as DM, pin 16 is defined as VCCF, pin 17 is defined as VBUS, and pin 18 is defined as VBUS;

[0041] Pin 21 is defined as RX+, pin 22 is defined as RX2+, pin 23 is defined as TXN, pin 24 is defined as VCCK, pin 25 is defined as DP, pin 26 is defined as GND, pin 27 is defined as VCCF, and pin 28 is defined as VCCK;

[0042] Pin 31 is defined as RX2-, pin 32 is defined as TXP2, pin 33 is defined as D0, pin 34 is defined as RB0, pin 35 is defined as GND, pin 36 is defined as GND, pin 37 is defined as LED, and pin 38 is defined as VCCK;

[0043] Pin 41 is defined as TXN2, pin 42 is defined as D2, pin 43 is defined as D1, pin 46 is defined as GND, pin 47 is defined as LX, and pin 48 is defined as GPIO0;

[0044] Pin 51 is defined as D3, pin 52 is defined as DQS, pin 53 is defined as VCCF, pin 56 is defined as CE5, pin 57 is defined as CE6, and pin 58 is defined as LX;

[0045] Pin 61 is defined as DQSn, pin 62 is defined as CE0, pin 63 is defined as CE2, pin 64 is defined as CE3, pin 65 is defined as VCCK, pin 66 is defined as CE4, pin 67 is defined as CE7, and pin 68 is defined as VCCK;

[0046] Pin 71 is defined as D4, pin 72 is defined as D6, pin 73 is defined as CE1, pin 74 is defined as RB1, pin 75 is defined as RE, pin 76 is defined as CLE, pin 77 is defined as WP, and pin 78 is defined as VCCF;

[0047] Pin 81 is defined as D5, pin 82 is defined as D7, pin 83 is defined as WE, pin 84 is defined as REn, pin 85 is defined as ALE, pin 86 is defined as VCCIO, pin 87 is defined as VREF, and pin 88 is defined as V1.2V.

[0048] In the embodiment of the present invention, pins RX- and RX+, TXP and TXN, DM and DP are USB channel 1 data lines (the main interface), and their proximity to the main interface facilitates wiring design. Pins RX2- and RX2+, TXP2 and TXN2, DM and DP are USB channel 2 data lines (applied to Type COTG), and their wiring design direction is opposite to that of the main interface. However, the channel 1 USB3x data line (including pins RX-, RX+, TXP, TXN) and the channel 2 USB3x data line (including pins RX2-, RX2+, TXP2, TXN2) are controlled by the channel switching circuit built into the controller chip 2. Therefore, in the embodiment of the present invention, all pins corresponding to channel 1 and channel 2 are as close as possible to reduce the difficulty of BGA package substrate design and secondly reduce signal interference.

[0049] In addition, since the channel switching circuit power supply built into the controller chip 2 is pin AVCCK, it must be close to the channel switching circuit power supply. By adding a capacitor, that is, pin 12 (AVCCK) is connected to the first filter capacitor 6 to ensure stable power supply of the channel switching circuit.

[0050] Pins 17 and 18 (VBUS) are the main power supply and are electrically connected. A third filter capacitor 8 is connected between pins 17 and 18. A resistor (not shown) is connected in series between pin 18 and the power supply terminal 9 of the USB connector to mitigate surge interference and other issues. To facilitate application-side wiring design, the VBUS pin is located close to the main interface connector.

[0051] Pins 47 and 58 (LX) are the outputs of the built-in DC-to-DC (switching power supply). Pins 47 and 58 are electrically connected. Pin 58 is connected to inductor 11, which provides power (VCCK) to the controller core. After isolation via a ferrite bead, it also provides power (AVCCK) to the built-in channel switching circuitry. Inductor 11 should be placed close to LX, with sufficient routing space reserved to maximize the power supply trace width to ensure high current flow and minimize heat generation.

[0052] Pins 16, 27, and 38 (VCCF) are the core power supplies of the flash memory chip, powered by the built-in LDO (Low Dropout Regulator) of the controller chip 2. Pins 16, 27, and 38 are electrically connected, and pin 16 is connected to the second filter capacitor 7.

[0053] Pin 26, pin 35, pin 36, and pin 46 (GND) are electrically connected.

[0054] The pin 28 (VCCK) is connected to the fourth filter capacitor 10 , and the pin 28 is also connected to the inductor 11 .

[0055] Pin 88 (V1.2V) is the 1.2V output of the built-in LDO of the controller chip 2, which mainly provides power for the flash memory chip 10. Pin 88 is connected to the fifth filter capacitor 12.

[0056] Pin 86 (VCCIO) connected to controller chip 2 is used to detect the flash memory chip IO power supply and is connected to the sixth filter capacitor 13. Pins 76 and 87 are electrically connected, and pin 87 (VREF) provides a reference voltage for pins DQS, DQSn, RE, and REn. The pins corresponding to DQS, DQSn, RE, and REn are all located at the edge of the array to reserve space for capacitors, allowing for connection to the corresponding filter capacitors.

[0057] Pins D0-D7, DQS, DQSn, RE, REn, CLE, and ALE are all located at the outer edge of the array, allowing for direct routing on the same layer. This reduces the likelihood of routing through vias and layer changes, preventing parasitic inductance and capacitance from vias, which can interfere with routing of critical signals. Other pins, such as CE0-CE7 and GND, can be placed near the center of the BGA, allowing for layer changes through vias.

[0058] In the embodiment of the present utility model, the first filter capacitor 6, the second filter capacitor 7, the third filter capacitor 8, the fourth filter capacitor 10, the fifth filter capacitor 12, the sixth filter capacitor 13 and the seventh filter capacitor are all conventional active capacitors for providing filtering function.

[0059] It should be noted that in the embodiment of the present invention, the pins 11-88 of the BGA substrate 1 are only used to illustrate the location of each pin and the corresponding pin function definition. According to actual application requirements, in other implementations, the serial number or name corresponding to each pin can also be adaptively adjusted.

[0060] The BGA packaging structure for the USB3x controller chip described in this utility model has the following advantages compared to the prior art:

[0061] 1. The BGA substrate 1 includes 60 groups of pins, which are evenly arranged in an 8*8 array at the bottom of the BGA substrate 1. At the same time, the central 4 pin areas of the array are left empty for via routing, which is compact and saves space. Figure 5 As shown, the structure of this embodiment reduces the area of ​​the conventional QFN package by 60%;

[0062] 2. For the pins on the BGA substrate 1 that need to be connected to external filter capacitors or USB connectors, they are all set at the edge of the pin array, which makes the wiring smooth, reduces the probability of via layer switching, and avoids the parasitic inductance and capacitance of the vias, which may cause interference with the wiring of key signals;

[0063] 3. BGA substrate 1 has a complete reference layer, which can accurately control impedance and equal length, and support ONFI high-speed transmission.

[0064] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0065] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various invention aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed approach should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims, the invention aspects lie in less than all of the features of the individual embodiments previously disclosed. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0066] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A BGA packaging structure for a USB3x controller chip, characterized in that: The BGA packaging structure for a USB 3x controller chip includes: a BGA substrate and a controller chip. The controller chip is soldered to the upper end of the BGA substrate. The outer side of the controller chip is sealed by a plastic layer. The controller chip and each group of pins of the BGA substrate are electrically connected via bonding wires. The BGA substrate is connected to a USB connector. The BGA substrate includes 60 groups of pins, which are evenly arranged in an 8*8 array at the bottom of the BGA substrate, with the central four pin areas of the array left empty; each group of pins on the BGA substrate is provided with a solder ball.

2. The BGA package structure for a USB3x controller chip according to claim 1, wherein: Among the 60 groups of pins of the BGA substrate, pin 11 is defined as RX-, pin 12 is defined as AVCCK, pin 13 is defined as TXP, pin 14 is defined as GND, pin 15 is defined as DM, pin 16 is defined as VCCF, pin 17 is defined as VBUS, and pin 18 is defined as VBUS; Pin 21 is defined as RX+, pin 22 is defined as RX2+, pin 23 is defined as TXN, pin 24 is defined as VCCK, pin 25 is defined as DP, pin 26 is defined as GND, pin 27 is defined as VCCF, and pin 28 is defined as VCCK; Pin 31 is defined as RX2-, pin 32 is defined as TXP2, pin 33 is defined as D0, pin 34 is defined as RB0, pin 35 is defined as GND, pin 36 is defined as GND, pin 37 is defined as LED, and pin 38 is defined as VCCK; Pin 41 is defined as TXN2, pin 42 is defined as D2, pin 43 is defined as D1, pin 46 is defined as GND, pin 47 is defined as LX, and pin 48 is defined as GPIO0; Pin 51 is defined as D3, pin 52 is defined as DQS, pin 53 is defined as VCCF, pin 56 is defined as CE5, pin 57 is defined as CE6, and pin 58 is defined as LX; Pin 61 is defined as DQSn, pin 62 is defined as CE0, pin 63 is defined as CE2, pin 64 is defined as CE3, pin 65 is defined as VCCK, pin 66 is defined as CE4, pin 67 is defined as CE7, and pin 68 is defined as VCCK; Pin 71 is defined as D4, pin 72 is defined as D6, pin 73 is defined as CE1, pin 74 is defined as RB1, pin 75 is defined as RE, pin 76 is defined as CLE, pin 77 is defined as WP, and pin 78 is defined as VCCF; Pin 81 is defined as D5, pin 82 is defined as D7, pin 83 is defined as WE, pin 84 is defined as REn, pin 85 is defined as ALE, pin 86 is defined as VCCIO, pin 87 is defined as VREF, and pin 88 is defined as V1.2V.

3. The BGA packaging structure for a USB3x controller chip according to claim 1, wherein: Pin 12 is connected to a first filter capacitor.

4. The BGA package structure for a USB3x controller chip according to claim 1, wherein: Pin 17 and pin 18 are electrically connected, a third filter capacitor is connected between pin 17 and pin 18, and a resistor is connected in series between pin 18 and the power supply end of the USB connector.

5. The BGA packaging structure for a USB3x controller chip according to claim 1, wherein: Pin 47 and pin 58 are electrically connected, and pin 58 is connected to an inductor.

6. The BGA packaging structure for a USB3x controller chip according to claim 5, characterized in that: Pin 28 is connected to a fourth filter capacitor, and pin 28 is also connected to the inductor.

7. The BGA packaging structure for a USB3x controller chip according to claim 1, wherein: Pin 16 , pin 27 , and pin 38 are electrically connected, and pin 16 is connected to a second filter capacitor.

8. The BGA packaging structure for a USB3x controller chip according to claim 1, wherein: Pin 76 and pin 87 are electrically connected.

9. The BGA packaging structure for a USB3x controller chip according to claim 1, wherein: Pin 88 is connected to a fifth filtering capacitor.

10. The BGA packaging structure for a USB3x controller chip according to claim 1, wherein: Pin 86 is connected to a sixth filtering capacitor.

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