Ball grid array (BGA) packaging structure for universal serial bus (USB) 2.0 controller chip

Abstract

The utility model discloses a ball grid array (BGA) packaging structure for a universal serial bus (USB) 2.0 controller chip, which comprises a BGA substrate, the USB 2.0 controller chip is welded at the upper end of the BGA substrate and is subjected to plastic packaging treatment through plastic packaging glue, the USB 2.0 controller chip is electrically connected with the BGA substrate through a bonding metal wire, and the BGA substrate is electrically connected with a USB connector; the BGA substrate comprises 32 groups of pins, the 32 groups of pins are uniformly arranged at the bottom of the BGA substrate in an 8 * 4 array, and the BGA substrate comprises four groups of CE pins. According to the utility model, the BGA substrate comprises 32 groups of pins, and the 32 groups of pins are uniformly arranged at the bottom of the BGA substrate in an 8 * 4 array, so that the layout is compact, and the occupied space is saved; and meanwhile, the BGA substrate comprises four groups of CE pins, so that more flash memory chips can be supported to increase the capacity.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic equipment, in particular to a BGA packaging structure for a USB2.0 controller chip. Background Art

[0002] USB2.0's simple and fast connection, no need for external power supply and good compatibility are the main reasons why USB2.0 storage drives have continued to exist. In particular, compatibility allows them to be widely used on various devices, reducing the difficulty of developing compatibility for application devices.

[0003] USB 2.0 controller chips initially used QFP 48P (Quad Flat Package) packaging. However, due to cost optimization and miniaturization requirements, TSSOP 28P (Thin Shrink Small Outline Package) and QFN 32P (Quad Flat No-lead Package) were gradually adopted.

[0004] Currently, these two packages have the following advantages and disadvantages:

[0005] The advantages of TSSOP28P are simple packaging process, low cost, and high soldering yield. The disadvantages are the use of alloy lead frame, poor signal quality, easy deformation of pins, and large size.

[0006] The advantages of QFN32P are its small size and high pin density. However, its disadvantages are also obvious. It also uses alloy lead frames, lacks a complete reference layer, has poor signal quality, and has a high soldering failure rate. The coplanarity and tin amount need to be accurately calculated, which can easily lead to problems such as poor solder creep, floating false solder joints, and parasitic solder beads. Figure 3 );

[0007] Moreover, TSSOP 28P and QFN 32P have 32 pins but only two CE (chip enable) pins, which cannot support more flash memory chips, limiting the capacity increase. In addition, TSSOP 28P and QFN 32P occupy a large area and have high space requirements. Utility Model Content

[0008] In view of the above problems, the present invention is proposed to provide a BGA packaging structure for a USB 2.0 controller chip that overcomes the above problems or at least partially solves the above problems.

[0009] The utility model provides a BGA packaging structure for a USB 2.0 controller chip, the BGA packaging structure for a USB 2.0 controller chip comprising: a BGA substrate, the USB 2.0 controller chip being soldered to the upper end of the BGA substrate and being plastic-sealed with a plastic sealant, the USB 2.0 controller chip being electrically connected to the BGA substrate via bonding metal wires, and the BGA substrate being electrically connected to a USB connector;

[0010] The BGA substrate includes 32 groups of pins, which are evenly arranged in an 8*4 array on the bottom of the BGA substrate. The BGA substrate includes four groups of CE pins.

[0011] Optionally, among the 32 groups of pins of the BGA substrate, pin 1 is defined as WE, pin 2 is defined as LED, pin 3 is defined as GND, pin 4 is defined as DP, pin 5 is defined as DM, pin 6 is defined as GND, pin 7 is defined as VCCF, pin 8 is defined as VBUS, pin 9 is defined as DQS, pin 10 is defined as CE0, pin 11 is defined as CE1, pin 12 is defined as GND, pin 13 is defined as GND, pin 14 is defined as RB, pin 15 is defined as VBUS, pin 16 is defined as VCCIO, pin 17 is defined as CLE, pin 18 is defined as D0, pin 19 is defined as D2, pin 20 is defined as WP, pin 21 is defined as D4, pin 22 is defined as D6, pin 23 is defined as CE3, pin 24 is defined as VCCIO, pin 25 is defined as ALE, pin 26 is defined as D1, pin 27 is defined as D3, pin 28 is defined as RD\RE, pin 29 is defined as D5, pin 30 is defined as D7, pin 31 is defined as CE2, and pin 32 is defined as VCCF.

[0012] Optionally, pin 4 is connected to a first filter capacitor; pin 5 is connected to a second filter capacitor.

[0013] Optionally, pin 3, pin 6, pin 12, and pin 13 are electrically connected, and pin 6 is connected to a third filter capacitor.

[0014] Optionally, pin 7 is connected to a third filtering capacitor.

[0015] Optionally, pin 8 and pin 15 are electrically connected, and pin 15 is connected to a fourth filter capacitor.

[0016] Optionally, a resistor is connected in series between pin 8 and the power supply terminal of the USB 2.0 connector.

[0017] Optionally, pin 16 and pin 24 are connected to a sixth filter capacitor.

[0018] Optionally, pin 32 is connected to a fifth filtering capacitor.

[0019] Optionally, the BGA substrate is respectively equipped with a first built-in capacitor, a second built-in capacitor, a third built-in capacitor, a fourth built-in capacitor, and a fifth built-in capacitor; the first built-in capacitor and the second built-in capacitor are connected to the USB2.0 controller chip; the third built-in capacitor is connected to pin 16 and pin 24; the fourth built-in capacitor is connected to pin 8 and pin 15; and the fifth built-in capacitor is connected to pin 7 and pin 32.

[0020] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages:

[0021] The BGA packaging structure for a USB2.0 controller chip described in an embodiment of the present invention has a BGA substrate including 32 groups of pins, which are evenly arranged in an 8*4 array at the bottom of the BGA substrate. The layout is compact and space is saved. At the same time, the BGA substrate includes four groups of CE pins, thereby supporting more flash memory chips to increase capacity.

[0022] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 This is a structural diagram of the BGA packaging structure for the USB2.0 controller chip described in the present invention;

[0025] Figure 2 This is a schematic diagram showing the principle of connecting the BGA substrate to the USB connector.

[0026] Figure 3 This is the distribution diagram of each pin on the BGA substrate;

[0027] Figure 4 for Figure 3 Reference distribution diagram of the serial numbers corresponding to each pin on the BGA substrate;

[0028] Figure 5This is a reference schematic diagram comparing the area of ​​the BGA packaging structure for USB2.0 controller chips described in the present invention with that of the prior art.

[0029] Description of reference numerals:

[0030] 1. BGA substrate; 2. USB2.0 controller chip; 3. USB connector; 4. Resistor; 11. First built-in capacitor; 12. Second built-in capacitor; 13. Third built-in capacitor; 14. Fourth built-in capacitor; 15. Fifth built-in capacitor; 16. First filter capacitor; 17. Second filter capacitor; 18. Third filter capacitor; 19. Fourth filter capacitor; 20. Fifth filter capacitor; 21. Sixth filter capacitor. DETAILED DESCRIPTION

[0031] Exemplary embodiments of the present disclosure will be described below in more detail with reference to the accompanying drawings.

[0032] In order to enable those skilled in the art to better understand the present invention, the following will be combined with the accompanying drawings of the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. The accompanying drawings show preferred embodiments of the present invention. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0033] Unless otherwise specified, various raw materials, instruments and equipment used in the present invention can be purchased from the market or prepared by existing methods.

[0034] Figure 1 This is a schematic diagram of the BGA packaging structure for the USB2.0 controller chip described in the present invention. Figure 2 This is a schematic diagram showing the principle of connecting the BGA substrate 1 and the USB connector 3. Figure 1 As shown, the BGA packaging structure for the USB 2.0 controller chip includes a BGA substrate 1, the USB 2.0 controller chip is soldered to the upper end of the BGA substrate 1 and is plastic-sealed with a plastic sealant, the USB 2.0 controller chip and the BGA substrate 1 are electrically connected via bonding wires, and the BGA substrate 1 is electrically connected to the USB connector 3; Figure 2 This is the distribution diagram of each pin on the BGA substrate 1. Figure 3 for Figure 2The serial number corresponding to each pin on the BGA substrate 1 is shown in the reference distribution diagram. The BGA substrate 1 includes 32 groups of pins, which are evenly arranged in an 8*4 array on the bottom of the BGA substrate 1. The BGA substrate 1 includes four groups of CE pins (i.e., CE0, CE1, CE2, and CE3), so that more flash memory chips can be supported to increase capacity.

[0035] Figure 3 This is the distribution diagram of each pin on the BGA substrate 1. Figure 4 for Figure 3 The reference distribution diagram of the serial numbers corresponding to the pins on the BGA substrate 1 is combined with Figure 3-4 As shown, among the 32 groups of pins of the BGA substrate 1, pin 1 is defined as WE, pin 2 is defined as LED, pin 3 is defined as GND, pin 4 is defined as DP, pin 5 is defined as DM, pin 6 is defined as GND, pin 7 is defined as VCCF, pin 8 is defined as VBUS, pin 9 is defined as DQS, pin 10 is defined as CE0, pin 11 is defined as CE1, pin 12 is defined as GND, pin 13 is defined as GND, pin 14 is defined as RB, pin 15 is defined as VBUS, pin 16 is defined as VCCIO, pin 17 is defined as CLE, pin 18 is defined as D0, pin 19 is defined as D2, pin 20 is defined as WP, pin 21 is defined as D4, pin 22 is defined as D6, pin 23 is defined as CE3, pin 24 is defined as VCCIO, pin 25 is defined as ALE, pin 26 is defined as D1, pin 27 is defined as D3, pin 28 is defined as RD\RE, pin 29 is defined as D5, pin 30 is defined as D7, pin 31 is defined as CE2, and pin 32 is defined as VCCF.

[0036] In this embodiment of the present invention, pins 4 (DP) and 5 (DM) are the data lines of the USB 2.0 controller chip 22, centered near the main interface of the USB connector 3 to facilitate wiring design. Pin 4 connects to the first filter capacitor 16, and pin 5 connects to the second filter capacitor 17. Furthermore, a ground connection surrounds pins 4 (DP) and 5 (DM), defining the outer edges of pins 4 (DP) and 5 (DM) as GND, including pins 3, 6, 12, and 13. This prevents plug-in crosstalk, which could affect signal stability and even damage the USB 2.0 controller chip 22.

[0037] In the embodiment of the present invention, pin 3 , pin 6 , pin 12 and pin 13 are electrically connected, and pin 6 is connected to the third filter capacitor 18 .

[0038] In the embodiment of the present invention, pin 7 is connected to the third filter capacitor 18 .

[0039] In an embodiment of the present invention, pin 8 and pin 15 are electrically connected, and pin 15 is connected to a fourth filter capacitor 19; pin 8 and pin 15 are VBUS, serving as the main power supply. To facilitate the wiring design of the application end, pin 8 is close to the power supply end (DC5V) of the USB2.0 connector. In an embodiment of the present invention, a resistor 4 is connected in series between pin 8 and the power supply end of the USB2.0 connector to solve problems such as surge interference.

[0040] In the embodiment of the present invention, the pin 16 and the pin 24 are connected to the sixth filter capacitor 21 .

[0041] In the embodiment of the present invention, the pin 32 is connected to the fifth filter capacitor 20 .

[0042] In an embodiment of the present invention, in order to save application design space and reduce the number of external capacitors used, the BGA substrate 1 can also be equipped with multiple built-in filter capacitors. For example, the BGA substrate 1 is equipped with a first built-in capacitor 11, a second built-in capacitor 12, a third built-in capacitor 13, a fourth built-in capacitor 14, and a fifth built-in capacitor 15.

[0043] Specifically, the first built-in capacitor 11 and the second built-in capacitor 12 are connected to the USB2.0 controller chip 22, and are used for the BGA substrate 1 to provide power to the USB2.0 controller chip 22 based on VCCK. Since no external output is required, there is no need to retain the VCCK pin. The saved pin can be used to increase the CE pin to support more flash memory chips to increase capacity. The built-in filter capacitor also achieves the purpose of saving wiring area.

[0044] The third built-in capacitor 13 is connected to pin 16 and pin 24, and VCCIO is the IO power supply of the flash memory chip; the fourth built-in capacitor 14 is connected to pin 8 and pin 15, and VBUS is the main power supply; the fifth built-in capacitor 15 is connected to pin 7 and pin 32, and VCCF is the core power supply of the flash memory chip.

[0045] The first filter capacitor 16, the second filter capacitor 17, the third filter capacitor 18, the fourth filter capacitor 19, the fifth filter capacitor 20, the sixth filter capacitor 21, the first built-in capacitor 11, the second built-in capacitor 12, the third built-in capacitor 13, the fourth built-in capacitor 14, and the fifth built-in capacitor 15 are all conventional filter capacitors used to provide filtering function.

[0046] It should be noted that in the embodiment of the present invention, the pins 1-32 of the BGA substrate 1 are only used to illustrate the location of each pin and the corresponding pin function definition. According to actual application requirements, in other implementations, the serial number or name corresponding to each pin can also be adaptively adjusted.

[0047] Compared with the prior art, the BGA packaging structure for USB 2.0 controller chip described in this utility model has the following advantages:

[0048] 1. The BGA substrate 1 includes 32 groups of pins, which are evenly arranged in an 8*4 array at the bottom of the BGA substrate 1. The layout is compact and saves space. Figure 5 As shown, the structure of this embodiment reduces the area by 76% compared to the traditional TSSOP28P and by 13.5% compared to the traditional QSN32P.

[0049] 2. The BGA substrate 1 includes four sets of CE pins, thereby supporting more flash memory chips to increase capacity;

[0050] 3. The built-in filter capacitor further reduces the layout area;

[0051] 4. Pins on the BGA substrate 1 that require external filter capacitors or are connected to the USB connector 3, such as pin 4, pin 5, pin 6, pin 7, pin 8, pin 16, pin 24, pin 32, etc., are all arranged on the outermost side of the pin array to facilitate wiring;

[0052] 5. Pins such as D0-D7, DQS, RD / RE, CLE, ALE, CE, and RB are staggered in order and can be directly wired on the same layer, reducing the probability of via layer switching and avoiding parasitic inductance and capacitance of vias, which may cause interference in the wiring of key signals.

[0053] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0054] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various invention aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed approach should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims, the invention aspects lie in less than all of the features of the individual embodiments previously disclosed. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0055] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims.

Claims

1. A BGA packaging structure for a USB2.0 controller chip, characterized in that: The BGA packaging structure for a USB 2.0 controller chip includes: a BGA substrate, the USB 2.0 controller chip is soldered to the upper end of the BGA substrate and is plastic-sealed with a plastic sealant, the USB 2.0 controller chip and the BGA substrate are electrically connected via bonding wires, and the BGA substrate is electrically connected to a USB connector; The BGA substrate includes 32 groups of pins, which are evenly arranged in an 8*4 array on the bottom of the BGA substrate. The BGA substrate includes four groups of CE pins.

2. The BGA packaging structure for a USB 2.0 controller chip according to claim 1, wherein: Among the 32 groups of pins of the BGA substrate, pin 1 is defined as WE, pin 2 is defined as LED, pin 3 is defined as GND, pin 4 is defined as DP, pin 5 is defined as DM, pin 6 is defined as GND, pin 7 is defined as VCCF, pin 8 is defined as VBUS, pin 9 is defined as DQS, pin 10 is defined as CE0, pin 11 is defined as CE1, pin 12 is defined as GND, pin 13 is defined as GND, pin 14 is defined as RB, pin 15 is defined as VBUS, pin 16 is defined as VCCIO, pin 17 is defined as CLE, pin 18 is defined as D0, pin 19 is defined as D2, pin 20 is defined as WP, pin 21 is defined as D4, pin 22 is defined as D6, pin 23 is defined as CE3, pin 24 is defined as VCCIO, pin 25 is defined as ALE, pin 26 is defined as D1, pin 27 is defined as D3, pin 28 is defined as RD\RE, pin 29 is defined as D5, pin 30 is defined as D7, pin 31 is defined as CE2, and pin 32 is defined as VCCF.

3. The BGA packaging structure for a USB 2.0 controller chip according to claim 2, wherein: Pin 4 is connected to a first filter capacitor; pin 5 is connected to a second filter capacitor.

4. The BGA packaging structure for a USB 2.0 controller chip according to claim 2, wherein: Pin 3 , pin 6 , pin 12 , and pin 13 are electrically connected, and pin 6 is connected to a third filter capacitor.

5. The BGA packaging structure for a USB 2.0 controller chip according to claim 2, wherein: Pin 7 is connected to the third filter capacitor.

6. The BGA packaging structure for a USB 2.0 controller chip according to claim 2, wherein: Pin 8 and pin 15 are electrically connected, and pin 15 is connected to a fourth filter capacitor.

7. The BGA packaging structure for a USB 2.0 controller chip according to claim 2, wherein: A resistor is connected in series between pin 8 and the power supply terminal of the USB 2.0 connector.

8. The BGA packaging structure for a USB 2.0 controller chip according to claim 2, wherein: Pin 16 and pin 24 are connected to a sixth filtering capacitor.

9. The BGA packaging structure for a USB 2.0 controller chip according to claim 2, wherein: Pin 32 is connected to the fifth filtering capacitor.

10. The BGA packaging structure for a USB 2.0 controller chip according to claim 2, wherein: The BGA substrate is respectively equipped with a first built-in capacitor, a second built-in capacitor, a third built-in capacitor, a fourth built-in capacitor, and a fifth built-in capacitor; the first built-in capacitor and the second built-in capacitor are connected to the USB2.0 controller chip; the third built-in capacitor is connected to pin 16 and pin 24; the fourth built-in capacitor is connected to pin 8 and pin 15; and the fifth built-in capacitor is connected to pin 7 and pin 32.

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