Layout structure suitable for high-speed ADC in UWB SOC

Abstract

The utility model discloses a layout structure suitable for a high-speed ADC in a UWB SOC, comprising a gate voltage bootstrapped switch module, a capacitor array module, a comparator array module and a logic control module, the gate voltage bootstrapped switch module is electrically connected with the capacitor array module, the capacitor array module comprises a first node and a second node, the first node is electrically connected with the comparator array module, and the second node is electrically connected with the comparator array module. The output of the first node and the output of the second node are electrically connected with the input of the comparator array module, the comparator array module comprises a first group of comparator units and a second group of comparator units, and the comparator array module is electrically connected with the logic control module. According to the utility model, the input offset of the comparator in the ADC is reduced, and the dynamic performance of the ADC is greatly improved.

Description

Technical Field

[0001] The utility model relates to the technical field of UWB chips, in particular to a layout structure suitable for a high-speed ADC in a UWB SOC. Background Art

[0002] Ultra-wideband (UWB) is applicable to a wide range of wireless systems. UWB can be traced back to telegraph systems, including the famous transatlantic pulse signal transmission in 1901. The technology subsequently found some applications in radar, primarily for military purposes. In 2002, the FCC approved regulations designating the 3.1-10.6 GHz frequency band for commercial use and the 22-29 GHz band for automotive systems. UWB positioning technology uses pulse signals with extremely low power spectral density and narrow pulse width to transmit data. These signals offer high temporal resolution and strong spatial penetration, enabling centimeter-level ranging and positioning accuracy in line-of-sight environments.

[0003] A System on Chip (SOC) is a highly integrated, dedicated chip that combines hardware and software designs on a single die. UWB communication is a relatively complex system, and currently, SOC solutions are the mainstream. A typical UWB communication SOC chip includes an always-on timer module (AON), a microprocessor core module (Core), a digital baseband (DBB), a memory module (Memory), a power supply module (PMU), a system clock module (BBPLL), a radio frequency carrier clock module (RFPLL), a transmitter (TX), and a receiver (RX).

[0004] The high-speed ADC (Analog to Digital Converter) is located in the RX module of the UWB communication SoC chip. Its function is to convert the analog signals received by the RX module into digital signals. The performance of the high-speed ADC is crucial to the RX module. In high-speed systems using advanced process technologies, the optimal performance of the circuit design is often limited by the parasitic capacitance and resistance in the layout.

[0005] Therefore, it is necessary to provide a layout structure suitable for high-speed ADC in UWB SOC to solve the above problems. Utility Model Content

[0006] In view of the problems and shortcomings of the prior art, the present invention provides a layout structure suitable for a high-speed ADC in a UWB SOC, which reduces the offset of the comparator input in the ADC and greatly improves the dynamic performance of the ADC.

[0007] The technical solution adopted by the present invention to solve the above-mentioned technical problems is to provide a layout structure suitable for a high-speed ADC in a UWB SOC. The layout structure includes a gate voltage bootstrap switch module, a capacitor array module, a comparator array module, and a logic control module. The gate voltage bootstrap switch module is electrically connected to the capacitor array module. The capacitor array module includes a first node and a second node. The outputs of the first node and the second node are respectively electrically connected to the input of the comparator array module. The comparator array module includes a first group of comparator units and a second group of comparator units. The comparator array module is electrically connected to the logic control module.

[0008] Preferably, the first group of comparator units includes a first comparator, a second comparator, a third comparator and a first spare comparator;

[0009] The second group of comparator units includes a fourth comparator, a fifth comparator, a sixth comparator and a second spare comparator.

[0010] Preferably, the first comparator, the second comparator, the third comparator, the fourth comparator, the fifth comparator, the sixth comparator, the first spare comparator and the second spare comparator are all of equal size.

[0011] Preferably, the output of the first node is electrically connected to the inputs of the first comparator, the second comparator, the third comparator, the first spare comparator, the fourth comparator, the fifth comparator, the sixth comparator and the second spare comparator through a first connecting line;

[0012] The output of the second node is electrically connected to the inputs of the first comparator, the second comparator, the third comparator, the first spare comparator, the fourth comparator, the fifth comparator, the sixth comparator and the second spare comparator through a second connection line.

[0013] Preferably, the first group of comparator units is arranged at the upper part of the comparator array module, the second group of comparator units is arranged at the lower part of the comparator array module, the first connecting line and the second connecting line are arranged in the middle position between the first group of comparator units and the second group of comparator units, and the first comparator and the fourth comparator, the second comparator and the fifth comparator, the third comparator and the sixth comparator, and the first standby comparator and the second standby comparator are respectively arranged symmetrically up and down with the first connecting line and the second connecting line as the center.

[0014] Preferably, the first connection line and the second connection line are symmetrically arranged, and the lengths of the lines from the first node and the second node to each of the comparators are equal.

[0015] Preferably, the first connecting line and the second connecting line are both multi-section symmetrical branch lines.

[0016] The positive progress effect of this utility model is:

[0017] The present invention provides a layout structure suitable for a high-speed ADC in a UWB SOC. The structure includes a gate voltage bootstrap switch module, a capacitor array module, a comparator array module, and a logic control module. The gate voltage bootstrap switch module is electrically connected to the capacitor array module. The capacitor array module includes a first node and a second node. The outputs of the first node and the second node are respectively electrically connected to the input of the comparator array module. The comparator array module includes a first group of comparator units and a second group of comparator units. The comparator array module is electrically connected to the logic control module. This reduces the offset of the comparator input in the ADC and greatly improves the dynamic performance of the ADC.

[0018] Furthermore, in order to ensure environmental symmetry, a first spare comparator and a second spare comparator are added, and the first group of comparator units and the second group of comparator units are symmetrically arranged with the first connecting line and the second connecting line as the center, and the sizes of the comparators are equal.

[0019] Furthermore, in order to ensure the symmetry of the routing length, multi-node symmetrical branch routing is adopted, thereby ensuring that the input offset of each comparator is less than one-fifth of the LSB under the routing layout of equal length and equal environment, thereby ensuring the dynamic range of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0021] Figure 1 The figure is a schematic diagram of a layout structure of a high-speed ADC suitable for a UWB SOC according to a preferred embodiment. DETAILED DESCRIPTION

[0022] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0023] The technical solution of the present utility model is described in detail below with reference to specific embodiments.

[0024] This embodiment provides a layout structure suitable for a high-speed ADC in a UWB SOC, which can reduce the offset of the comparator input in the ADC and greatly improve the dynamic performance of the ADC.

[0025] This embodiment provides a layout structure suitable for a high-speed ADC in a UWB SOC, which includes a gate voltage bootstrap switch module 1 , a capacitor array module 2 , a comparator array module 3 and a logic control module 4 .

[0026] like Figure 1 As shown, the gate voltage bootstrap switch module 1 is electrically connected to the capacitor array module 2. The capacitor array module 2 includes a first node 21 and a second node 22. The outputs of the first node 21 and the second node 22 are respectively electrically connected to the inputs of the comparator array module 3. The comparator array module 3 includes a first group of comparator units 31 and a second group of comparator units 32. The comparator array module 3 is electrically connected to the logic control module 4.

[0027] The first comparator unit 31 includes a first comparator 311 , a second comparator 312 , a third comparator 313 and a first spare comparator 314 ; the second comparator unit 32 includes a fourth comparator 321 , a fifth comparator 322 , a sixth comparator 323 and a second spare comparator 324 .

[0028] In this embodiment, the output of the first node 21 is electrically connected to the inputs of the first comparator 311, the second comparator 312, the third comparator 313, the first standby comparator 314, the fourth comparator 321, the fifth comparator 322, the sixth comparator 323 and the second standby comparator 324 through the first connection line 5; the output of the second node 22 is electrically connected to the inputs of the first comparator 311, the second comparator 312, the third comparator 313, the first standby comparator 314, the fourth comparator 321, the fifth comparator 322, the sixth comparator 323 and the second standby comparator 324 through the second connection line 6.

[0029] To ensure symmetry in the environment of the comparator array module 3, the first comparator 311, the second comparator 312, the third comparator 313, the fourth comparator 321, the fifth comparator 322, the sixth comparator 323, the first backup comparator 314, and the second backup comparator 324 are all of equal size. Furthermore, the first group of comparator units 31 is located at the top of the comparator array module 3, the second group of comparator units 32 is located at the bottom of the comparator array module 3, the first connecting line 5 and the second connecting line 6 are located between the first and second groups of comparator units 31 and 32, and the first and fourth comparators 311 and 321, the second and fifth comparators 312 and 322, the third and sixth comparators 313 and 323, and the first and second backup comparators 314 and 324 are symmetrically arranged vertically around the first and second connecting lines 5 and 6, respectively.

[0030] To ensure symmetry in the routing of the comparator array module 3, the first connection line 5 and the second connection line 6 are both multi-section symmetrical branch lines. Furthermore, the routing of the first connection line 5 and the second connection line 6 is symmetrical, and the lengths of the lines from the first node 21 and the second node 22 to each comparator are equal.

[0031] The present invention provides a layout structure suitable for a high-speed ADC in a UWB SOC. The layout structure includes a gate voltage bootstrap switch module, a capacitor array module, a comparator array module, and a logic control module. The gate voltage bootstrap switch module is electrically connected to the capacitor array module. The capacitor array module includes a first node and a second node. The outputs of the first node and the second node are respectively electrically connected to the input of the comparator array module. The comparator array module includes a first group of comparator units and a second group of comparator units. The comparator array module is electrically connected to the logic control module. This reduces the offset of the comparator input in the ADC and greatly improves the dynamic performance of the ADC.

[0032] Furthermore, in order to ensure environmental symmetry, a first spare comparator and a second spare comparator are added, and the first group of comparator units and the second group of comparator units are symmetrically arranged with the first connecting line and the second connecting line as the center, and the sizes of the comparators are equal.

[0033] Furthermore, to ensure trace length symmetry, multi-node symmetrical branch routing was used. Simulation results show that, with equal-length and equal-environment traces, the input offset of each comparator is guaranteed to be less than one-fifth of the Least Significant Bit (LSB), thus ensuring the dynamic range of the ADC. The LSB is used to measure ADC performance. If the noise or offset of a module is less than one-half LSB, it is considered to have no impact on ADC performance.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A layout structure suitable for high-speed ADC in UWB SOC, characterized by: It includes a gate voltage bootstrap switch module, a capacitor array module, a comparator array module and a logic control module. The gate voltage bootstrap switch module is electrically connected to the capacitor array module. The capacitor array module includes a first node and a second node. The outputs of the first node and the second node are respectively electrically connected to the input of the comparator array module. The comparator array module includes a first group of comparator units and a second group of comparator units. The comparator array module is electrically connected to the logic control module.

2. A layout structure suitable for high-speed ADC in UWB SOC according to claim 1, characterized in that: The first group of comparator units includes a first comparator, a second comparator, a third comparator and a first spare comparator; The second group of comparator units includes a fourth comparator, a fifth comparator, a sixth comparator and a second spare comparator.

3. A layout structure suitable for high-speed ADC in UWB SOC according to claim 2, characterized in that: The first comparator, the second comparator, the third comparator, the fourth comparator, the fifth comparator, the sixth comparator, the first spare comparator, and the second spare comparator are all of equal size.

4. The layout structure suitable for high-speed ADC in UWB SOC according to claim 2, characterized in that: The output of the first node is electrically connected to the inputs of the first comparator, the second comparator, the third comparator, the first spare comparator, the fourth comparator, the fifth comparator, the sixth comparator and the second spare comparator through a first connecting line; The output of the second node is electrically connected to the inputs of the first comparator, the second comparator, the third comparator, the first spare comparator, the fourth comparator, the fifth comparator, the sixth comparator and the second spare comparator through a second connection line.

5. A layout structure suitable for a high-speed ADC in a UWB SOC according to claim 4, wherein the first group of comparator units is arranged at the upper portion of the comparator array module, the second group of comparator units is arranged at the lower portion of the comparator array module, the first connecting line and the second connecting line are arranged midway between the first and second groups of comparator units, and the first and fourth comparators, the second and fifth comparators, the third and sixth comparators, and the first and second standby comparators are symmetrically arranged vertically with the first and second connecting lines as the center, respectively.

6. A layout structure suitable for high-speed ADC in UWB SOC according to claim 4, characterized in that: The first connection line and the second connection line are symmetrically arranged, and the lengths of the lines from the first node and the second node to each of the comparators are equal.

7. The layout structure suitable for high-speed ADC in UWB SOC according to claim 4, characterized in that: The first connecting line and the second connecting line are both multi-section symmetrical branch lines.

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