485 communication transceiver circuit capable of preventing reverse connection

Abstract

The utility model provides a receiving and transmitting circuit capable of preventing reverse connection, which comprises a comparator U1, an integrating circuit, a control circuit and a bus switching circuit, and is characterized in that the comparator U1 is connected with a signal line 485A and a signal line 485B, the comparator U1 is connected with the integrating circuit, and the integrating circuit and the comparator U1 are used for cooperatively judging the access state of the signal line 485A and the signal line 485B; the integrating circuit is connected with the control circuit. The output end of the control circuit is connected with the signal line 485A and the signal line 485B through the bus switching circuit. The control circuit is used for controlling the bus switching circuit to realize bus switching according to the information of the integrating circuit and the comparator U1; by automatically identifying the A and B signal lines of the 485 bus and completing switching, normal communication can be ensured under the conditions of positive connection and reverse connection, and the problem of abnormal communication caused by reverse connection of 485A and 485B of equipment is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of serial communication, and mainly relates to a transceiver circuit capable of preventing reverse connection. Background Art

[0002] The RS485 bus is a widely used serial communication standard. Its signals are transmitted using differential signals (485A and 485B). The differential voltage on signal lines 485A and 485B is used to identify signals 0 and 1. The standard stipulates that for a logic 1, the voltage on VAB is (-2 to -6V); for a logic 0, the voltage on VAB is (+2 to +6V).

[0003] Devices connected to the 485 bus network must be connected in accordance with 485A to 485A, 485B to 485B (such as Figure 1 When a device is connected to the bus backwards, for example, 485A and 485B are connected reversed, the bus will receive a 1 when the connected device sends a 0, and a 0 when it sends a 1. This prevents normal communication with other devices and can even affect communication on the entire bus, paralyzing the communication network. To address this issue, we propose a transceiver circuit that prevents reverse connection. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the present invention provides a 485 communication transceiver circuit that can prevent reverse connection. It has the advantages of automatically identifying the A and B signal lines of the 485 bus and completing the switching, ensuring normal communication in both forward and reverse connection conditions, and solving the problem in the prior art of abnormal communication caused by the device being reversely connected to the bus.

[0005] A 485 communication transceiver circuit capable of preventing reverse connection, comprising a comparator U1, a comparator U2, a bidirectional three-state gate circuit U3, a bidirectional three-state gate circuit U4, a bidirectional three-state gate circuit U5, a bidirectional three-state gate circuit U6, an inverter U7 and a bus transceiver U8; the positive electrode of the comparator U1 is connected to the A end of the three-state gate circuit U4 and the A end of U6 respectively; the negative electrode of the comparator U1 is connected to the A end of the three-state gate circuit U3 and the A end of U5 respectively; the output end of the comparator U1 is connected to one end of a resistor R1; the other end of the resistor R1 is connected to the resistor R1, and the output end of the comparator U1 is connected to the resistor R1. Capacitor C1 is connected to the positive terminal of comparator U2; the other end of capacitor C1 is connected to GND; one end of adjustable resistor RP1 is connected to VCC, and the other end of adjustable resistor RP1 is connected to GND; the negative terminal of comparator U2 is connected to the movable end of adjustable resistor RP1; the output end of comparator U2 is respectively connected to the enable end OE of U3, the enable end OE of U4 and the input end of inverter U7; the output end of inverter U7 is respectively connected to the enable end OE of U5 and the enable end OE of U6; the B end of tri-state gate circuit U3 is connected to the B end of bus transceiver U8;

[0006] The B terminal of the tri-state gate circuit U4 is connected to the A terminal of the bus transceiver U8; the B terminal of the tri-state gate circuit U5 is connected to the A terminal of the bus transceiver U8; the B terminal of the tri-state gate circuit U6 is connected to the B terminal of the bus transceiver U8; the direction control terminal DIR of the tri-state gate circuits U3, U4, U5 and U6 is connected to the DE terminal of the bus transceiver U8; the DE terminal of the bus transceiver U8 is short-circuited with the RE# terminal;

[0007] Furthermore, the comparator U1 and the comparator U2 are LM393PE4.

[0008] Furthermore, the model of the tri-state gate circuit is 74HC245G.

[0009] Furthermore, the model of the bus transceiver U8 is MAX485ECSA+.

[0010] Furthermore, the inverter U7 is of model 74HC04.

[0011] The beneficial effects of the present invention are:

[0012] The present invention uses an integrator circuit and comparator to determine the connection status of the 485A and 485B lines, thereby promptly detecting whether 485A and 485B are connected reversely, thus avoiding communication problems caused by reverse connection, which may even affect the entire bus communication. The bus switching circuit is composed of bidirectional three-state gate circuits U3-U6 and inverter U7, and the comparator output is used to control the bus switching circuit to complete bus switching. Based on automatic recognition, the A and B signal lines of the 485 bus are automatically identified and switched, ensuring normal communication in both forward and reverse connection situations. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram of the connection between the RS485 bus and the device;

[0014] Figure 2 This is the principle diagram of the anti-reverse receiving and transmitting circuit of the utility model;

[0015] Figure 3 This is a working principle diagram of the utility model when it is correctly connected;

[0016] Figure 4 This is a diagram showing the working principle of the utility model during reverse access. DETAILED DESCRIPTION

[0017] A 485 communication transceiver circuit capable of preventing reverse connection includes a comparator U1, a comparator U2, a bidirectional tri-state gate circuit U3, a bidirectional tri-state gate circuit U4, a bidirectional tri-state gate circuit U5, a bidirectional tri-state gate circuit U6, an inverter U7, and a bus transceiver U8;

[0018] The positive electrode of the comparator U1 is connected to the A terminal of the tri-state gate circuit U4 and the A terminal of U6 respectively;

[0019] The negative electrode of the comparator U1 is connected to the A terminal of the tri-state gate circuit U3 and the A terminal of U5 respectively;

[0020] The output end of the comparator U1 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the capacitor C1 and the positive electrode of the comparator U2 respectively; the other end of the capacitor C1 is connected to GND;

[0021] One end of the adjustable resistor RP1 is connected to VCC, and the other end of the adjustable resistor RP1 is connected to GND; the negative electrode of the comparator U2 is connected to the movable end of the adjustable resistor RP1;

[0022] The output terminal of the comparator U2 is connected to the enable terminal OE of U3, the enable terminal OE of U4 and the input terminal of the inverter U7 respectively;

[0023] The output end of the inverter U7 is connected to the enable end OE of U5 and the enable end OE of U6 respectively;

[0024] The B terminal of the tri-state gate circuit U3 is connected to the B terminal of the bus transceiver U8;

[0025] The B terminal of the tri-state gate circuit U4 is connected to the A terminal of the bus transceiver U8;

[0026] The B terminal of the tri-state gate circuit U5 is connected to the A terminal of the bus transceiver U8;

[0027] The B terminal of the tri-state gate circuit U6 is connected to the B terminal of the bus transceiver U8;

[0028] The direction control terminals DIR of the tri-state gate circuits U3, U4, U5 and U6 are connected to the DE terminal of the bus transceiver U8;

[0029] The DE terminal and RE# terminal of bus transceiver U8 are short-circuited;

[0030] The comparator U1 and comparator U2 are LM393PE4;

[0031] The model of the tri-state gate circuit is 74HC245G;

[0032] The model of the bus transceiver U8 is MAX485ECSA+;

[0033] The model of the inverter U7 is 74HC04;

[0034] When in use, the comparator U1 is connected to the signal line 485A and the signal line 485B on the RS485 bus.

[0035] The present invention will be further described below with reference to the accompanying drawings and examples.

[0036] The present invention provides the following technical solution: a transceiver circuit capable of preventing reverse connection, comprising a comparator U1 and an integrating circuit, wherein the comparator U1 is connected to a signal line 485A and a signal line 485B on an RS485 bus (e.g. Figure 2 As shown), the comparator U1 is connected to the integration circuit. The integration circuit and the comparator U1 are used to cooperate in judging the access status of the signal line 485A and the signal line 485B. When there is a device communicating on the bus, the bus state will switch between 0 and 1 according to the data; when there is no device sending data on the bus, it is in an idle state, and the bus maintains a high level. During data communication, a large amount of data shows a statistical characteristic that 0 and 1 appear with equal probability. When idle, the bus is always at a high level (1), so the probability of 1 appearing is greater overall. Using this characteristic, an integration circuit composed of R1 and C1 can be used to maintain the access status of the 485A and 485B lines. The access status of the 485A and 485B lines can be judged by the comparator U2 connected later. The high level output of U2 indicates that the 485A and 485B lines are correctly connected to the bus; the low level output of U2 indicates that the 485A and 485B lines are reversely connected to the bus. The output of the comparator U2 is used to control the switching circuit to complete the bus switching.

[0037] Preferably, it also includes a control circuit and a bus switching circuit, the integration circuit is connected to the control circuit, and the output end of the control circuit is connected to the signal line 485A and the signal line 485B through the bus switching circuit; the control circuit is used to control the bus switching circuit to realize bus switching according to the information of the integration circuit and the comparator U1.

[0038] Preferably, the output pin of the comparator U1 is connected to the integration circuit composed of R1 and C1. AB When V > 0, U1 outputs high level to charge the integration circuit. AB When up is less than 0, U1 outputs a low level and the integration circuit discharges.

[0039] Preferably, it further comprises a potentiometer RP1 and a comparator U2. The potentiometer RP1 is used to set a threshold value and is combined with the comparator U2 to form a control circuit for adjusting sensitivity.

[0040] Preferably, the bus switching circuit includes bidirectional three-state gate circuits U3, U4, U5, U6 (74HC245) and an inverter U7 (74HC04);

[0041] The output end of the comparator U2 is connected to the enable control ends of the three-state gate circuits U3 and U4; the output end of the comparator U2 is connected to the enable control ends of the three-state gate circuits U5 and U6 through the inverter U7.

[0042] Preferably, when the signal line 485A and the signal line 485B are correctly connected to the bus (e.g. Figure 3 As shown), comparator U1 outputs a high level when idle, which is maintained by the integration circuit and then outputs a high level through comparator U2. At this time, U3 and U4 are cut off, and the high level of comparator U2 outputs a low level through inverter U7. At this time, U5 and U6 are turned on, and the DE terminal is connected to the 485 transceiver control terminal (as shown). Figure 1 When 485 receives data, DE is low, and the control data is transmitted from the bidirectional three-state A end to the B end; when 485 sends data, DE is high, and the control data is transmitted from the bidirectional three-state B end to the A end, completing the correct access of 485A and 485B.

[0043] Preferably, when the signal line 485A and the signal line 485B are connected to the bus in reverse (e.g. Figure 4 As shown), the signal line 485A and the signal line 485B are reversely connected to the two comparison input terminals of the comparator U1, and output a low level when idle, which is maintained by the integration circuit, and then outputs a low level through the comparator U2. At this time, U3 and U4 are turned on, and the low level of the comparator U2 outputs a high level through the inverter U7. U5 and U6 are cut off. The reversed signal line 485A and the signal line 485B are correctly connected to the subsequent receiving circuit after switching through U3 and U4. The DE terminal is connected to the 485 transceiver control terminal (as shown Figure 1 When 485 receives data, DE is low, and the control data is transmitted from the bidirectional three-state A end to the B end; when 485 sends data, DE is high, and the control data is transmitted from the bidirectional three-state B end to the A end, completing the correct access of 485A and 485B.

[0044] The present invention will be further described below with reference to the accompanying drawings and examples.

[0045] like Figure 2 As shown, a transceiver circuit capable of preventing reverse connection includes a comparator U1 and an integration circuit. Comparator U1 is connected to signal lines 485A and 485B on the RS485 bus, and compares the bus potential difference. The integration circuit composed of R1 and C1 is used to identify and maintain the circuit bus status. Comparator U1 is connected to the integration circuit, and the integration circuit and comparator U1 are used to cooperate in determining the connection status of signal lines 485A and 485B. The output pin of comparator U1 is connected to the integration circuit composed of R1 and C1. When V AB When V > 0, U1 outputs high level to charge the integration circuit. AB When up is less than 0, U1 outputs a low level and the integration circuit discharges.

[0046] Potentiometer RP1 is used to set the threshold and, together with comparator U2, forms a control circuit for adjusting sensitivity. Bidirectional tri-state gates U3, U4, U5, and U6, along with inverter U7, form the bus switching circuit, implementing the bus switching function. The integrator circuit is connected to the control circuit, whose output is connected to signal lines 485A and 485B via the bus switching circuit. The control circuit controls the bus switching circuit to implement bus switching based on information from the integrator circuit and comparator U1.

[0047] The output end of the comparator U2 is connected to the enable control ends of the three-state gate circuits U3 and U4; the output end of the comparator U2 is connected to the enable control ends of the three-state gate circuits U5 and U6 through the inverter U7.

[0048] The switching principle is as follows: When a device is communicating on the bus, the bus state switches between 0 and 1 based on the data. When no device is sending data, the bus is in an idle state, during which the bus remains high. During data communication, large amounts of data exhibit a statistical characteristic: 0 and 1 appear with equal probability. During the idle state, the bus remains high, so the probability of 1 appearing is generally higher. This characteristic can be exploited using an integrator circuit and comparator to determine the connection status of the 485A and 485B lines. The comparator output then controls the switching circuit to complete the bus switching.

[0049] The switching process is as follows:

[0050] 1. RS485 bus signal line 485A and signal line 485B are connected to comparator U1. When V AB When V AB When up < 0, U1 outputs low level.

[0051] 2. The output pin of comparator U1 is connected to the integrator circuit formed by R1 and C1. When U1 outputs a high level, the integrator circuit is charged, and when comparator U1 outputs a low level, the integrator circuit is discharged. As described in the switching principle, since comparator U1 outputs a high level during idle time, the charging and discharging opportunities are equal during communication, so the integrator circuit remains in a high state. Through a threshold comparator U2, a comparison state is output: when connected correctly, comparator U2 outputs a high level; when connected incorrectly, comparator U2 outputs a low level.

[0052] 3. The output of comparator U2 is connected to the enable control terminals of tri-state gates U3 and U4; the output is also connected to the enable control terminals of tri-state gates U5 and U6 through inverter U7. Therefore, when comparator U2 outputs a high level, tri-state gates U3 and U4 are turned off, while tri-state gates U5 and U6 are turned on. When comparator U2 outputs a low level, tri-state gates U3 and U4 are turned on, while tri-state gates U5 and U6 are turned off.

[0053] 4. When the circuit is correctly connected to the bus, Figure 3 As shown, the comparator outputs a high level when idle, which is maintained by the integration circuit and then outputs a high level through the threshold comparator U2. At this time, U3 and U4 are cut off, and the high level of comparator U2 outputs a low level through the inverter U7. At this time, U5 and U6 are turned on, and the correct access of 485A and 485B can be completed. At the same time, considering that RS485 is a half-duplex communication, the 485 transceiver control terminal DE is used to control the transmission direction of the bidirectional tri-state gate. When 485 is receiving, DE is low, and the tri-state gate data A is transmitted to B; when 485 is sending, DE is high, and the tri-state gate data B is transmitted to A.

[0054] 5. When the circuit is connected to the bus in reverse, such as Figure 4 As shown, at this time, since 485A and 485B are reversely connected to the two comparison input terminals of the comparator, they output a low level when idle, which is maintained by the integration circuit. Then, after passing through the threshold comparator U2, it outputs a low level. At this time, U3 and U4 are turned on, and the low level of comparator U2 outputs a high level through the inverter U7. At this time, U5 and U6 are turned off. At this time, the reverse-connected 485A and 485B are correctly connected to the subsequent receiving circuit after switching through U3 and U4. The control function of DE is the same as that of forward access.

Claims

1. A 485 communication transceiver circuit that can prevent reverse connection, characterized by: The device comprises a comparator U1, a comparator U2, a bidirectional three-state gate circuit U3, a bidirectional three-state gate circuit U4, a bidirectional three-state gate circuit U5, a bidirectional three-state gate circuit U6, an inverter U7 and a bus transceiver U8; the positive electrode of the comparator U1 is connected to the A end of the three-state gate circuit U4 and the A end of U6 respectively; the negative electrode of the comparator U1 is connected to the A end of the three-state gate circuit U3 and the A end of U5 respectively; the output end of the comparator U1 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the capacitor C1 and the positive electrode of the comparator U2 respectively; the other end of the capacitor C1 is connected to GND; one end of the adjustable resistor RP1 is connected to VCC, and the other end of the adjustable resistor RP1 is connected to GND; the negative electrode of the comparator U2 is connected to the movable end of the adjustable resistor RP1 The output end of the comparator U2 is connected to the enable end OE of U3, the enable end OE of U4 and the input end of the inverter U7 respectively; the output end of the inverter U7 is connected to the enable end OE of U5 and the enable end OE of U6 respectively; the B end of the three-state gate circuit U3 is connected to the B end of the bus transceiver U8; the B end of the three-state gate circuit U4 is connected to the A end of the bus transceiver U8; the B end of the three-state gate circuit U5 is connected to the A end of the bus transceiver U8; the B end of the three-state gate circuit U6 is connected to the B end of the bus transceiver U8; the direction control end DIR of the three-state gate circuits U3, U4, U5 and U6 is connected to the DE end of the bus transceiver U8; the DE end of the bus transceiver U8 is short-circuited with the RE# end.

2. A 485 communication transceiver circuit capable of preventing reverse connection according to claim 1, characterized in that: The comparator U1 and the comparator U2 are LM393PE4.

3. The 485 communication transceiver circuit capable of preventing reverse connection according to claim 1, characterized in that: The model of the tri-state gate circuit is 74HC245G.

4. The 485 communication transceiver circuit capable of preventing reverse connection according to claim 1, characterized in that: The model of the bus transceiver U8 is MAX485ECSA+.

5. The 485 communication transceiver circuit capable of preventing reverse connection according to claim 1, characterized in that: The model of the inverter U7 is 74HC04.

Images