Automatic transceiving high-reliability 485 bus communication circuit

Abstract

The utility model discloses an automatic transceiving high-reliability 485 bus communication circuit, which comprises an automatic receiving and transmitting mode switching circuit, a chip U13, a high-frequency interference suppression circuit, a ground surge protection circuit and a differential signal surge and short-circuit protection circuit, the output end of the automatic receiving and transmitting mode switching circuit is connected to the signal input end of the chip U13, the output end of the chip U13 is connected to the input end of the high-frequency interference suppression circuit, and the output end of the high-frequency interference suppression circuit is connected to the input end of the ground surge protection circuit. According to the high-reliability 485 bus communication circuit capable of automatically transmitting and receiving, a receiving mode and a transmitting mode can be automatically switched during 485 communication, and the high-speed communication requirement can be met; the 485 bus surge and short circuit protection function is achieved, and a 485 circuit cannot be damaged when surge and short circuit occur on a 485 bus; the high-frequency interference resistance is high, and stable operation is still achieved in a scene with large high-frequency interference.

Description

Technical Field

[0001] The utility model relates to the technical field of 485 bus communication, in particular to a high-reliability 485 bus communication circuit for automatic transmission and reception. Background Art

[0002] As core components of new energy products, power electronic converters must possess strong maintainability, high reliability, and robust interference resistance to operate stably in complex external environments. New energy products often require information transmission for logical analysis, status display, and energy scheduling, making communication circuits essential.

[0003] A. 485 communication is widely used as a wired communication method with low cost, long communication distance, and stable communication signals. When used as a bus, 485 communication often adopts half-duplex communication mode, meaning that both reception and transmission share the same line. This requires manual control of the receive and transmit modes. In high-speed communication scenarios, this switching control is difficult, and software programming is complex and prone to errors. Furthermore, 485 communication is often used in long-distance communication scenarios, with long lines, and surge and short-circuit conditions must be considered. Furthermore, power electronic converters are composed of high-frequency switching devices and high-frequency inductors and capacitors, which are subject to significant high-frequency interference. Therefore, 485 communication circuits must have a certain degree of resistance to high-frequency interference to ensure a good communication data waveform. The following problems need to be solved: 485 bus communication requires manual switching of the receive and transmit modes, which is difficult to control at high speeds. Surges and short circuits on the 485 bus can damage the 485 circuits, and normal communication cannot be achieved in situations with high high-frequency interference. To address this, a high-reliability 485 bus communication circuit with automatic transmission and reception is proposed. Utility Model Content

[0004] The purpose of the utility model is to provide a high-reliability 485 bus communication circuit with automatic reception and transmission, which can automatically switch between reception and transmission modes, has surge and short-circuit protection functions, and has strong anti-high-frequency interference capabilities, which can greatly improve the reliability of communication and solve the problems raised in the above-mentioned background technology.

[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solutions: a high-reliability 485 bus communication circuit for automatic reception and transmission, comprising an automatic switching receiving and transmitting mode circuit, a chip U13, a high-frequency interference suppression circuit, a ground surge protection circuit, and a differential signal surge and short-circuit protection circuit, wherein the output end of the automatic switching receiving and transmitting mode circuit is connected to the signal input end of the chip U13, the output end of the chip U13 is connected to the input end of the high-frequency interference suppression circuit, the output end of the high-frequency interference suppression circuit is connected to the input end of the ground surge protection circuit, and the output end of the ground surge protection circuit is connected to the input end of the differential signal surge and short-circuit protection circuit.

[0006] Preferably, the automatic switching receiving and transmitting mode circuit includes a trigger U12, a transistor Q9, a transistor Q7, a transistor Q8, and a trigger U9, wherein the 2nd pin of the trigger U12 is connected to the SCI-TX2 signal terminal input, the 4th pin of the trigger U12 is connected in series with a resistor R163 and then connected to the base of the transistor Q9, the emitter of the transistor Q9 is grounded, the source of the transistor Q9 is connected to the input end of the resistor R161, the output end of the resistor R161 is connected to the base of the transistor Q7, the emitter of the transistor Q7 is connected to the emitter of the transistor Q8 and then grounded, the source of the transistor Q7 is connected to the base of the transistor Q8, and the source of the transistor Q8 is connected to the input end of the resistor R161. The first pin of the optocoupler U15 is connected to pin 2 of the optocoupler U15, pin 1 of the optocoupler U15 is connected to the +5V power input, pin 4 of the optocoupler U15 is connected to pin 2 of the trigger U9, and to pin 4 of the chip U13, pin 3 of the optocoupler U15 is grounded, pin 5 of the trigger U9 is connected to the power input, pin 3 of the trigger U9 is grounded, pin 4 of the trigger U9 is connected to the input of the diode D19, and to pin 3 of the chip U13, the output of the diode D19 is connected to pin 2 of the chip U13, and to the input of the capacitor C105 and to the input of the resistor R166, the output of the capacitor C105 is connected to the output of the resistor R166 and then grounded.

[0007] Preferably, pin 1 of the chip U13 is connected to pin 2 of the optocoupler U14, pin 1 of the optocoupler U14 is connected to the power input, pin 4 of the optocoupler U14 is connected to the output end of the diode D23, and the input end of the diode D23 is connected to the SCI-RX2 signal input.

[0008] Preferably, the high-frequency interference suppression circuit includes a resistor R83, a resistor R84, a resistor R29, a resistor R30, a capacitor C37, a capacitor C107 and a capacitor C108, the input end of the resistor R83 is connected to pin 7 of the chip U13, the input end of the resistor R84 is connected to pin 6 of the chip U13, the output end of the resistor R84 is connected to the output end of the resistor R30 and to the input end of the capacitor C107, the input end of the resistor R30 is connected to the VCC5V power input, and the output end of the capacitor C107 is grounded; pin 8 of the chip U13 is connected to the VCC5V power input and to the input end of the capacitor C37, the output end of the capacitor C37 is connected to the input end of the resistor R29 and to the input end of the capacitor C108, the output end of the resistor R29 is connected to the output end of the capacitor C108 and then to the output end of the resistor R93.

[0009] Preferably, the ground surge protection circuit includes a diode D17 and a diode D18, the input end of the diode D17 is connected to the output end of the resistor R84, the input end of the diode D18 is connected to the input end of the resistor R83, and the output ends of the diode D17 and the diode D18 are connected and then grounded.

[0010] Preferably, the surge and short-circuit protection circuit of the differential signal includes a resettable fuse F5, a resettable fuse F6 and a gas discharge tube F7. The input end of the resettable fuse F5 is connected to the output end of the resistor R83, the input end of the resettable fuse F6 is connected to the output end of the resistor R84, the output end of the resettable fuse F5 is connected to the 485-B signal terminal output and connected to pin 1 of the gas discharge tube F7, and the output end of the resettable fuse F6 is connected to the 485-A signal terminal output and connected to pin 3 of the gas discharge tube F7.

[0011] Compared with the prior art, the beneficial effects of the present invention are:

[0012] This high-reliability 485 bus communication circuit with automatic reception and transmission can automatically switch between receiving and transmitting modes during 485 communication to meet high-speed communication requirements. It has 485 bus surge and short-circuit protection functions, and surges and short circuits on the 485 bus will not damage the 485 circuit. It has strong anti-high-frequency interference capabilities and can still operate stably in scenarios with large high-frequency interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a schematic diagram showing the connection between the automatic switching receiving and transmitting mode circuit and the chip U13 of the present invention;

[0014] Figure 2 This is a schematic diagram of the connection principle of the chip U13, high-frequency interference suppression circuit, ground surge protection circuit, and differential signal surge and short-circuit protection circuit of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0016] See also Figure 1-2 A high-reliability 485 bus communication circuit for automatic reception and transmission includes an automatic switching reception and transmission mode circuit, a chip U13, a high-frequency interference suppression circuit, a ground surge protection circuit, and a differential signal surge and short-circuit protection circuit. The output end of the automatic switching reception and transmission mode circuit is connected to the signal input end of the chip U13, the output end of the chip U13 is connected to the input end of the high-frequency interference suppression circuit, the output end of the high-frequency interference suppression circuit is connected to the input end of the ground surge protection circuit, and the output end of the ground surge protection circuit is connected to the input end of the differential signal surge and short-circuit protection circuit.

[0017] Wherein: the automatic switching receiving and transmitting mode circuit includes a trigger U12, a transistor Q9, a transistor Q7, a transistor Q8, and a trigger U9. The 2nd pin of the trigger U12 is connected to the SCI-TX2 signal terminal input. The 4th pin of the trigger U12 is connected in series with a resistor R163 and then connected to the base of the transistor Q9. The emitter of the transistor Q9 is grounded. The source of the transistor Q9 is connected to the input end of the resistor R161. The output end of the resistor R161 is connected to the base of the transistor Q7. The emitter of the transistor Q7 is connected to the emitter of the transistor Q8 and then grounded. The source of the transistor Q7 is connected to the base of the transistor Q8. The source of the transistor Q8 is connected to the To pin 2 of the optocoupler U15, pin 1 of the optocoupler U15 is connected to the +5V power input, pin 4 of the optocoupler U15 is connected to pin 2 of the trigger U9 and to pin 4 of the chip U13, pin 3 of the optocoupler U15 is grounded, pin 5 of the trigger U9 is connected to the power input, pin 3 of the trigger U9 is grounded, pin 4 of the trigger U9 is connected to the input end of the diode D19 and to pin 3 of the chip U13, the output end of the diode D19 is connected to pin 2 of the chip U13, and to the input end of the capacitor C105 and to the input end of the resistor R166, the output end of the capacitor C105 is connected to the output end of the resistor R166 and then grounded.

[0018] Among them: Pin 1 of chip U13 is connected to Pin 2 of optocoupler U14, Pin 1 of optocoupler U14 is connected to the power input, Pin 4 of optocoupler U14 is connected to the output end of diode D23, and the input end of diode D23 is connected to the SCI-RX2 signal interrupt input.

[0019] Among them: the high-frequency interference suppression circuit includes resistor R83, resistor R84, resistor R29, resistor R30, capacitor C37, capacitor C107 and capacitor C108, the input end of resistor R83 is connected to pin 7 of chip U13, the input end of resistor R84 is connected to pin 6 of chip U13, the output end of resistor R84 is connected to the output end of resistor R30 and the input end of capacitor C107, the input end of resistor R30 is connected to the VCC5V power input, and the output end of capacitor C107 is grounded; pin 8 of chip U13 is connected to the VCC5V power input and to the input end of capacitor C37, the output end of capacitor C37 is connected to the input end of resistor R29 and to the input end of capacitor C108, the output end of resistor R29 is connected to the output end of capacitor C108 and then to the output end of resistor R93.

[0020] The ground surge protection circuit includes a diode D17 and a diode D18. The input end of the diode D17 is connected to the output end of the resistor R84. The input end of the diode D18 is connected to the input end of the resistor R83. The output ends of the diode D17 and the diode D18 are connected and then grounded.

[0021] Among them: the surge and short-circuit protection circuit of the differential signal includes a resettable fuse F5, a resettable fuse F6 and a gas discharge tube F7. The input end of the resettable fuse F5 is connected to the output end of the resistor R83, the input end of the resettable fuse F6 is connected to the output end of the resistor R84, the output end of the resettable fuse F5 is connected to the 485-B signal terminal output and connected to pin 1 of the gas discharge tube F7, and the output end of the resettable fuse F6 is connected to the 485-A signal terminal output and connected to pin 3 of the gas discharge tube F7.

[0022] The SCI_TX2 and SCI_RX2 are ground communication signals sent by the controller. Since they are low-active, they are pulled up to VCC3.3V+ through resistors R56 and R55 respectively. The communication circuit requires a certain current when the level is flipped, generally 20 to 100mA. VCC3.3V+ supplies transient current to GND through capacitors C40 and C41, which has a certain filtering effect. After SCI_TX2 and SCI_RX2 pass through the 485 isolation chip U13, they are converted into differential signals 485_A and 485_B, VCC_5V_CAN Similar to VCC3.3V+, transient current is supplied to GND_5V_CAN through capacitors C36 and C37, which has a certain filtering effect; +5V is similar to VCC_5V_CAN, transient current is supplied to GND through capacitors C122 and C123, which has a certain filtering effect. Resistors R83 and R84 mainly play the role of series current limiting. Capacitor C107 filters the signal between 485_A and GND_5V_CAN, and capacitor C108 filters the signal between 485_B and GND_5V_CAN.

[0023] When SCI_TX2 is low, it means that data is being sent. SCI_TX2 is converted to high through trigger U12. The base of transistor Q9 is high, and transistor Q9 is turned on. When processing digital signals, the transistor can be approximately equivalent to a switch tube. The base B of transistor Q7 is pulled down to GND through resistor R161 through the collector C and emitter E of transistor Q9, which is a low level. Transistor Q7 is cut off, and +5V is supplied to the base B of transistor Q8 through resistor R164. Transistor Q8 is turned on, and the cathode 2 of the diode of optocoupler U15 is connected to the cathode 2 of the diode. The collector C and emitter E of the transistor Q8 are pulled down to GND, which is a low level. The optocoupler U15 is turned on, and the 4th and 3rd pins of the optocoupler U15 are connected to GND_5V_CAN, which is a low level. The data is sent to the 4th pin D of the chip U13, the input pin 2 of the trigger U9 is low, the output pin 4 is high, the 3rd pin DE of the chip U13 is high, and the 2nd pin / RE of the chip U13 is high. The chip U13 is in the sending mode at this time. After the above analysis, it can be seen that when data needs to be sent, the circuit can automatically switch to the sending mode.

[0024] When SCI_TX2 is high, it means that no data is sent. At this time, data can be received from the 485 bus. SCI_TX2 is converted to low through U12, and the base of transistor Q9 is low. Transistor Q9 is cut off. +5V supplies power to base B of transistor Q7 through resistors R167 and R161, transistor Q7 is turned on, and base B of transistor Q8 is pulled down to GND through collector C and emitter E of transistor Q7, which is a low level. Transistor Q8 is cut off, cathode 2 of optocoupler U15 is pulled up to +5V through resistor R166, which is a high level, optocoupler U15 is cut off, and pin 4 of optocoupler U15 is connected to VCC_5V_CAN through resistor R169, which is a high level. Input pin 2 of trigger U9 is high, output pin 4 is low, pin 3 DE of chip U13 is low, pin 2 / RE of chip U13 is low, and chip U13 is in receiving mode at this time. When there is data on the bus, pin 1 R of chip U13 is at a low level, and pin 1 and pin 2 of optocoupler U14 are connected to GND_5V_CAN through diode D20, which is a low level. Optocoupler U14 is turned on. At this time, SCI_RX2 is pulled down to GND through diode D23 and pin 4 and pin 3 of optocoupler U14, which is a low level, and SCI_RX2 reads the data on the bus; because the effective level of SCI_RX2 is low, diodes D20 and D23 play an anti-reverse and protection role. SCI_RX2 is straightened to VCC3.3V+ through R56. When there is no data on the 485 bus, it is a high level. After the above analysis, it can be seen that when data reception is required, the circuit can automatically switch to the receiving mode.

[0025] When the signal between 485_A and GND_5V_CAN exceeds the withstand voltage of diode D17 (the parameter of GND_5V_CAN level value can be selected by 2 times the normal 485_A), 485_A clamps the level to zero level through diode D17, thereby protecting the remaining circuit components; when the signal between 485_B and GND_5V_CAN exceeds the withstand voltage of diode D18 (the parameter of CAN_5V_GND level value can be selected by 2 times the normal 485_B), 485_B clamps the level to zero level through diode D18, thereby protecting the remaining circuit components.

[0026] The resettable fuse F5, the resettable fuse F6 and the gas discharge tube F7 form a surge and short-circuit protection circuit for the differential signal. When there is a surge voltage, the gas discharge tube F7 can be closed to protect the front-end circuit. The gas discharge tube F7 adopts a 3-pin package, and the middle pin is connected to PE to further filter high-frequency interference.

[0027] This high-reliability 485 bus communication circuit for automatic transceiver, chip U13 mainly converts the ground-based SCI_TX2 and SCI_RX2 signals into differential 485_A and 485_B signals. When the input level of pin 2 - / RE of chip U13 is low, chip U13 is in receive mode and reads bus data through pin 1 - R (low level is valid); when the input level of pin 3 - DE of chip U13 is high, chip U13 is in transmit mode and transmits data through pin 4 - D (low level is valid); the automatic switching logic is as follows : When SCI_TX2 is at a low level, there is data to be sent. The DE pin is set high through trigger U12, transistor Q9, transistor Q7, transistor Q8, trigger U9, etc., and SCI_TX2 can send data to the bus through the D pin; when SCI_TX2 is at a high level, there is no data to be sent. The DE pin is set low through trigger U9, etc., / RE is valid, and SCI_RX2 can receive data from the bus through the R pin. Since the optocoupler and transistor are both high-frequency devices, automatic mode switching can be achieved during high-speed communication.

[0028] Optocouplers U14 and U15 are used to isolate the primary and secondary sides. The power supply for the isolated primary side is +5V and GND, and the power supply for the isolated secondary side is VCC_5V_CAN and GND_5V_CAN. When a surge voltage exists between 485_A and 485_B and GND_5V_CAN, diodes D17 and D18 form an energy discharge path to avoid overvoltage damage to chip U13. Triggers U9 and U12 with inverting buffer functions with Schmitt trigger inputs are used to convert changing input signals into clearly defined, jitter-free output signals, and have a certain ability to resist high-frequency interference. When a short circuit occurs between the differential signals, the self-resettable fuses F5 and F6 can be used to disconnect and protect the front-end circuit. When a surge voltage occurs between the differential signals, the gas discharge tube F7 can be used to close and protect the front-end circuit.

[0029] The above is only a preferred specific implementation method of the present invention, but the protection scope of the present invention is not limited to this. Any technician familiar with the technical field within the technical scope disclosed by the present invention can make equivalent replacements or changes based on the technical solution and utility model concept of the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A high-reliability 485 bus communication circuit for automatic transmission and reception, comprising a circuit for automatically switching between receiving and transmitting modes, a chip U13, a high-frequency interference suppression circuit, a ground surge protection circuit, and a differential signal surge and short-circuit protection circuit, characterized in that: The output end of the automatic switching receiving and transmitting mode circuit is connected to the signal input end of the chip U13, the output end of the chip U13 is connected to the input end of the high-frequency interference suppression circuit, the output end of the high-frequency interference suppression circuit is connected to the input end of the ground surge protection circuit, and the output end of the ground surge protection circuit is connected to the input end of the differential signal surge and short-circuit protection circuit.

2. The high-reliability 485 bus communication circuit for automatic transmission and reception according to claim 1, characterized in that: The automatic switching receiving and transmitting mode circuit includes a trigger U12, a transistor Q9, a transistor Q7, a transistor Q8, and a trigger U9. Pin 2 of the trigger U12 is connected to the SCI-TX2 signal terminal input. Pin 4 of the trigger U12 is connected in series with a resistor R163 and then connected to the base of the transistor Q9. The emitter of the transistor Q9 is grounded. The source of the transistor Q9 is connected to the input end of the resistor R161. The output end of the resistor R161 is connected to the base of the transistor Q7. The emitter of the transistor Q7 is connected to the emitter of the transistor Q8 and then grounded. The source of the transistor Q7 is connected to the base of the transistor Q8. The source of the transistor Q8 is connected to the input end of the resistor R161. To pin 2 of the optocoupler U15, pin 1 of the optocoupler U15 is connected to the +5V power input, pin 4 of the optocoupler U15 is connected to pin 2 of the trigger U9 and to pin 4 of the chip U13, pin 3 of the optocoupler U15 is grounded, pin 5 of the trigger U9 is connected to the power input, pin 3 of the trigger U9 is grounded, pin 4 of the trigger U9 is connected to the input end of the diode D19 and to pin 3 of the chip U13, the output end of the diode D19 is connected to pin 2 of the chip U13, and to the input end of the capacitor C105 and to the input end of the resistor R166, the output end of the capacitor C105 is connected to the output end of the resistor R166 and then grounded.

3. The high-reliability 485 bus communication circuit for automatic transmission and reception according to claim 1, characterized in that: Pin 1 of the chip U13 is connected to pin 2 of the optocoupler U14, pin 1 of the optocoupler U14 is connected to the power input, pin 4 of the optocoupler U14 is connected to the output end of the diode D23, and the input end of the diode D23 is connected to the SCI-RX2 signal input.

4. The high-reliability 485 bus communication circuit for automatic transmission and reception according to claim 1, characterized in that: The high-frequency interference suppression circuit includes a resistor R83, a resistor R84, a resistor R29, a resistor R30, a capacitor C37, a capacitor C107 and a capacitor C108. The input end of the resistor R83 is connected to pin 7 of the chip U13, the input end of the resistor R84 is connected to pin 6 of the chip U13, the output end of the resistor R84 is connected to the output end of the resistor R30 and the input end of the capacitor C107, the input end of the resistor R30 is connected to the VCC5V power input, and the output end of the capacitor C107 is grounded; pin 8 of the chip U13 is connected to the VCC5V power input and to the input end of the capacitor C37, the output end of the capacitor C37 is connected to the input end of the resistor R29 and to the input end of the capacitor C108, the output end of the resistor R29 is connected to the output end of the capacitor C108 and then to the output end of the resistor R93.

5. The high-reliability 485 bus communication circuit for automatic transmission and reception according to claim 1, characterized in that: The ground surge protection circuit includes a diode D17 and a diode D18. The input end of the diode D17 is connected to the output end of the resistor R84. The input end of the diode D18 is connected to the input end of the resistor R83. The output ends of the diode D17 and the diode D18 are connected and then grounded.

6. The high-reliability 485 bus communication circuit for automatic transmission and reception according to claim 1, characterized in that: The surge and short-circuit protection circuit of the differential signal includes a resettable fuse F5, a resettable fuse F6 and a gas discharge tube F7. The input end of the resettable fuse F5 is connected to the output end of the resistor R83, the input end of the resettable fuse F6 is connected to the output end of the resistor R84, the output end of the resettable fuse F5 is connected to the 485-B signal terminal output and to pin 1 of the gas discharge tube F7, and the output end of the resettable fuse F6 is connected to the 485-A signal terminal output and to pin 3 of the gas discharge tube F7.

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