Semiconductor device
By using a heavily doped layer formed by a deposition process as the plate layer in DRAM devices and combining the substrate with the semiconductor structure, the problems of weak storage capacity and low integration of storage capacitors are solved, and efficient utilization of storage capacitors and high integration of devices are achieved.
Patent Information
- Application Number
- CN202422544782.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-10-03
- Estimated Expiration
- 2034-10-21
AI Technical Summary
The storage capacity of storage capacitors in existing DRAM devices is relatively weak, and it is difficult to improve the integration of the devices.
A heavily doped layer formed by a deposition process is used as the plate layer of the storage capacitor. The base and semiconductor structure in the substrate structure are combined to avoid damage from the ion implantation process, thereby improving the storage capacity of the storage capacitor. The storage capacitor is also set between the base and semiconductor structure in the substrate structure to avoid occupying a large space.
The storage capacity of the storage capacitor is improved, the integration of the device is improved, the storage capacitor is prevented from occupying a large space, and the performance of the device is enhanced.
Smart Images
Figure CN223415187U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the field of semiconductor integrated circuit manufacturing and relates to a semiconductor device. Background Art
[0002] Dynamic Random Access Memory (DRAM) is widely used in computers, servers, and various electronic devices due to its advantages of fast read and write speed, low cost, and high storage density. Its basic storage unit consists of a storage capacitor and a transistor. Usually, the storage capacitor is integrated into the substrate on one side of the transistor, such as Figure 1 As shown in FIG, it is a schematic diagram of the structure of a DRAM device, including a transistor structure 01, a substrate 02, a deep trench 021, a lower electrode 03, a dielectric layer 04 and an upper electrode 05. A deep trench is first formed in the substrate, and then the lower electrode of the storage capacitor is formed on the surface of the substrate on the inner wall of the trench by ion implantation. Then, a dielectric layer and a polysilicon upper electrode filling the trench are formed in the deep trench. However, the doping concentration of the lower electrode formed by the storage capacitor of this structure is difficult to control, and the lower electrode is easily damaged. In addition, the area of the storage capacitor and the distance between the upper and lower electrodes of the storage capacitor are also limited by the process and device size, and the storage capacity of the storage capacitor is relatively weak. In order to improve the storage capacity of the storage capacitor, the storage capacitor is also separately set above the substrate, such as Figure 2 As shown in FIG, a schematic diagram of the structure of another DRAM device is shown, but separately making a storage capacitor above the substrate requires a large space, which significantly reduces the integration of the device.
[0003] Therefore, there is an urgent need to find a semiconductor device that can improve the storage capacity of the storage capacitor while increasing the device integration. Summary of the Invention
[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor device for solving the problem in the prior art that it is difficult to improve the storage capacity of the storage capacitor while improving the integration of the device.
[0005] To achieve the above-mentioned and other related purposes, the present invention provides a semiconductor device, comprising:
[0006] The substrate structure comprises at least a laminated structure and an isolation dielectric layer covering an upper surface of the laminated structure, wherein the laminated structure comprises a first electrode layer, an intermediate dielectric layer, and a second electrode layer stacked in sequence;
[0007] a semiconductor structure located on an upper surface of the isolation dielectric layer, the semiconductor structure comprising a third electrode, a fourth electrode, and a gate structure, wherein the gate structure controls the on / off electrical connection between the third electrode and the fourth electrode;
[0008] a first electrode, one end of which is electrically connected to the first electrode layer, and at least a portion of the other end of the first electrode is located outside the substrate structure;
[0009] A second electrode has one end electrically connected to the second electrode layer, and the other end of the second electrode is at least partially located outside the substrate structure and electrically connected to the fourth electrode.
[0010] Optionally, the substrate structure further includes a base, and the first electrode layer is located above the base.
[0011] Optionally, the substrate structure further includes a first isolation layer covering the upper surface of the base, and the stacked structure covers the upper surface of the first isolation layer.
[0012] Optionally, the first electrode layer and the second electrode layer have the same doping concentration; and the first electrode layer and the second electrode layer have different thicknesses.
[0013] Optionally, the semiconductor structure also includes a first conductive type epitaxial layer, a second conductive type first region and a second conductive type second region and a fifth electrode located on the upper surface of the epitaxial layer, the third electrode, the fourth electrode and the gate structure are located on the upper surface of the epitaxial layer, the first region and the second region are located on two opposite sides of the gate structure, the third electrode is electrically connected to the first region, the fourth electrode is electrically connected to the second region, and the fifth electrode is electrically connected to the gate structure.
[0014] Optionally, the gate structure includes a fifth electrode and a gate dielectric layer and a gate conductive layer stacked in sequence, wherein one end of the gate conductive layer close to the first region extends above the first region, and one end of the gate conductive layer close to the second region extends above the second region.
[0015] Optionally, the epitaxial layer is further provided with a second isolation layer that passes through the epitaxial layer, the isolation dielectric layer and the stacked structure, the second isolation layer includes a first isolation portion and a second isolation portion connected in sequence, the first isolation portion and the second isolation portion are connected end to end in sequence and surround the area where the first region and the second region are located, and the second isolation layer is separated from the first region and the second region by a preset distance.
[0016] Optionally, the first electrode includes a first conductive plug passing through the epitaxial layer, the isolation dielectric layer, the second electrode layer and the intermediate dielectric layer, and the second electrode includes a second conductive plug passing through the epitaxial layer and the isolation dielectric layer, the first conductive plug is insulated from the epitaxial layer and the second electrode layer, and the second conductive plug is insulated from the epitaxial layer.
[0017] Optionally, the semiconductor device is further provided with a first interconnection layer electrically connected to the first electrode, a second interconnection layer electrically connected to the second electrode and the fourth electrode, a third interconnection layer electrically connected to the third electrode, and a fourth interconnection layer electrically connected to the fifth electrode.
[0018] Optionally, the semiconductor device is further provided with an interlayer dielectric layer covering the upper surface of the semiconductor structure, and the first electrode and the second electrode both penetrate the interlayer dielectric layer.
[0019] As described above, the semiconductor device of the present invention uses a heavily doped layer formed by a deposition process as the plate layer of the storage capacitor, so that the doped ions in the plate layer are evenly distributed, avoiding damage to the plate layer by the ion implantation process, ensuring the quality of the first plate layer and the second plate layer, and improving the storage capacity of the storage capacitor. At the same time, by arranging the storage capacitor between the base and the semiconductor structure in the substrate structure, the storage capacitor avoids occupying a large space, thereby improving the integration of the device and having high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 Shown is a structural diagram of a DRAM device.
[0021] Figure 2 Shown is a schematic diagram of the structure of another DRAM device.
[0022] Figure 3 Shown is a schematic structural diagram of a semiconductor device of the present invention.
[0023] Explanation of Figure Numbers
[0024] 01 Transistor Structure
[0025] 02 Substrate
[0026] 021 Deep Groove
[0027] 03 Lower electrode
[0028] 04 Dielectric layer
[0029] 05 Upper electrode
[0030] 1 Substrate structure
[0031] 11 base
[0032] 12 Laminated structure
[0033] 121 first plate layer
[0034] 122 Intermediate dielectric layer
[0035] 123 Second plate layer
[0036] 13 Isolation dielectric layer
[0037] 14 Second isolation layer
[0038] 2 Semiconductor structure
[0039] 21 epitaxial layer
[0040] 22 Gate structure
[0041] 221 gate dielectric layer
[0042] 222 gate conductive layer
[0043] 223 Isolation Side Wall
[0044] 23 First contact layer
[0045] 24 Second contact layer
[0046] 25 Third contact layer
[0047] 26 Fourth contact layer
[0048] 27 Fifth contact layer
[0049] 3 interlayer dielectric layer
[0050] 4 Insulation layer
[0051] 41 First Interconnection Layer
[0052] 42 Second interconnect layer
[0053] 43 Third Interconnection Layer
[0054] 44 Fourth interconnection layer
[0055] 5. First electrode
[0056] 51 first conductive plug
[0057] 52 third conductive plug
[0058] 53 first dielectric layer
[0059] 6 Second electrode
[0060] 61 second conductive plug
[0061] 62 fourth conductive plug
[0062] 63 second dielectric layer
[0063] 7 Third electrode
[0064] 8 Fourth electrode
[0065] 9 Fifth electrode DETAILED DESCRIPTION
[0066] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different perspectives and applications without departing from the spirit of the present invention.
[0067] See also Figure 3 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components relevant to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be arbitrarily changed, and the component layout may also be more complex.
[0068] This embodiment provides a semiconductor device such as Figure 3 As shown, it is a schematic structural diagram of the semiconductor device, including a substrate structure 1, a semiconductor structure 2, a first electrode and a second electrode, wherein the substrate structure 1 includes at least a stacked structure 12 and an isolation dielectric layer 13 covering the upper surface of the stacked structure 12, and the stacked structure 12 includes a first electrode layer 121, an intermediate dielectric layer 122, and a second electrode layer 123 stacked in sequence; the semiconductor structure 2 is located on the upper surface of the isolation dielectric layer 13, and the semiconductor structure has a third electrode 7, a fourth electrode 8 and a gate structure 22, and the gate structure 22 controls the on and off of the electrical connection between the third electrode 7 and the fourth electrode 8; one end of the first electrode 5 is electrically connected to the first electrode layer 121, and the other end of the first electrode 5 is at least partially located outside the substrate structure 1; one end of the second electrode 6 is electrically connected to the second electrode layer 123, and the other end of the second electrode 6 is at least partially located outside the substrate structure 1 and electrically connected to the fourth electrode 8.
[0069] As an example, the substrate structure 1 further includes a base 11 , and the first electrode layer 121 is located above the base 11 .
[0070] Specifically, the substrate 11 is a process platform for manufacturing semiconductor devices. While ensuring the performance of the device, the thickness, size and shape of the substrate 11 can be selected according to actual conditions.
[0071] Specifically, the material of the substrate 11 includes silicon, diamond, sapphire, gallium nitride, silicon carbide or other suitable materials. In this embodiment, an intrinsic silicon layer is used as the substrate 11.
[0072] Specifically, the stacked structure 12 is stacked on top of the substrate 11. In the stacked structure 12, the first electrode layer 121 comprises a heavily doped silicon layer or other suitable conductive material layer; the intermediate dielectric layer 122 comprises silicon oxide, silicon oxynitride, or other suitable dielectric material; and the second electrode layer 123 comprises a heavily doped silicon layer or other suitable conductive material layer. In this embodiment, both the first electrode layer 121 and the second electrode layer 123 are heavily doped silicon layers formed by a deposition process. The doping type of the heavily doped silicon layers can be both N-type or both P-type, or one layer can be N-type and the other P-type.
[0073] As an example, the doping concentrations of the first electrode layer 121 and the second electrode layer 123 are the same.
[0074] Specifically, while ensuring the performance of the semiconductor device, the doping concentration of the first electrode layer 121 may also be different from the doping concentration of the second electrode layer 123 .
[0075] As an example, the first electrode layer 121 and the second electrode layer 123 have different thicknesses.
[0076] Specifically, while ensuring the performance of the semiconductor device, the thickness of the first electrode layer 121 and the second electrode layer 123 may also be the same. In this embodiment, the first electrode layer 121 and the second electrode layer 123 have the same doping concentration and the same thickness.
[0077] Specifically, the first electrode layer 121, the intermediate dielectric layer 122 and the second electrode layer 123 together constitute a storage capacitor. The thickness and dielectric properties of the intermediate dielectric layer 122 will affect the capacitance of the capacitor structure. While ensuring the performance of the semiconductor device, the thickness of the intermediate dielectric layer 122 can be selected according to actual conditions.
[0078] As an example, the substrate structure 1 further includes a first isolation layer covering the upper surface of the base 11 , and the stacked structure 12 covers the upper surface of the first isolation layer.
[0079] Specifically, the provision of the first isolation layer ensures insulation between the substrate 11 and the first electrode layer 121 in the stacked structure 12, thereby preventing the substrate 11 from affecting the capacitance of the capacitor structure. In this embodiment, since the substrate 11 is an intrinsic silicon layer, there is no need to provide a first isolation layer between the substrate 11 and the stacked structure 12.
[0080] As an example, the semiconductor structure 2 also includes a first conductive type epitaxial layer 21, a second conductive type first region and a second conductive type second region and a fifth electrode located on the upper surface of the epitaxial layer 21, a third electrode 7, a fourth electrode 8 and a gate structure 22 are located on the upper surface of the epitaxial layer 21, the first region and the second region are located on two sides of the gate structure 22 opposite to each other, the third electrode 7 is electrically connected to the first region, the fourth electrode 8 is electrically connected to the second region, and the fifth electrode 9 is electrically connected to the gate structure 22.
[0081] Specifically, the first conductive type includes one of N type and P type, the second conductive type includes one of N type and P type, and the first conductive type is opposite to the second conductive type.
[0082] Specifically, the first region is the source region of the device, the second region is the drain region of the device, the contact type between the first region and the third electrode 7 is ohmic contact, and the contact type between the second region and the fourth electrode 8 is ohmic contact.
[0083] Specifically, epitaxial layer 21 covers the upper surface of substrate structure 1. The doping concentrations of the first and second regions are greater than that of epitaxial layer 21. While ensuring device performance, the thickness and doping concentration of epitaxial layer 21 can be selected based on actual conditions. The doping concentration, thickness, and shape of the first region can also be selected based on actual conditions. The doping concentration, thickness, and shape of the second region can also be selected based on actual conditions. Thickness here refers to the distance between the lower and upper surfaces of each portion.
[0084] Specifically, the method of forming the epitaxial layer 21 includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0085] As an example, the epitaxial layer 21 is further provided with a second isolation layer 14 that penetrates the epitaxial layer 21 , the isolation dielectric layer 13 and the stacked structure 12 .
[0086] As an example, the second isolation layer 14 includes a first isolation portion and a second isolation portion connected in sequence, the first isolation portion and the second isolation portion are connected end to end in sequence and surround the areas where the first and second regions are located, and the second isolation layer 14 is separated from the first and second regions by a preset distance.
[0087] Specifically, in order to avoid using an ion implantation process to form the first electrode layer 121 and the second electrode layer 123 , the intermediate dielectric layer 122 is usually formed after forming the epitaxial layer 21 and before forming the first region and the second region.
[0088] Specifically, forming the intermediate dielectric layer 122 includes the following steps: forming a first electrode layer 121, a first sacrificial layer, a second electrode layer 123, a second sacrificial layer and an epitaxial layer 21 stacked in sequence on the upper surface of the substrate 11; forming a patterned first photoresist layer on the upper surface of the epitaxial layer 21, and etching the epitaxial layer 21, the second sacrificial layer, the second electrode layer 123, the first sacrificial layer and the first electrode layer 121 in sequence based on the patterned first photoresist layer to obtain a first trench; removing the first photoresist layer and forming a support layer filling the first trench; and forming the support layer. Next, a patterned second photoresist layer is formed on the upper surface of the epitaxial layer 21. A second trench is formed based on the patterned second photoresist layer, penetrating the epitaxial layer 21, the second sacrificial layer, the second plate layer 123, the first sacrificial layer, and the first plate layer 121. The first and second sacrificial layers are removed simultaneously. The second photoresist layer is then removed, and an intermediate dielectric layer 122 is formed to fill the gap between the first plate layer 121 and the second plate layer 123. An isolation dielectric layer 13 is formed to fill the gap between the second plate layer 123 and the epitaxial layer 21, and a second isolation portion is formed to fill the second trench. The gap here refers to the gap created after removing the sacrificial layer.
[0089] Specifically, the material of the first sacrificial layer includes silicon germanium or other materials with a high etching selectivity ratio with the first plate layer 121, the second plate layer 123 and the epitaxial layer 21; the material of the second sacrificial layer includes silicon germanium or other materials with a high etching selectivity ratio with the first plate layer 121, the second plate layer 123 and the epitaxial layer 21. Preferably, SiGe with a high etching selectivity ratio of 1:300 with silicon is used. x Ge y The layers serve as the first sacrificial layer and the second sacrificial layer.
[0090] Specifically, forming a patterned first photoresist layer, forming a patterned second photoresist layer, removing the first photoresist layer and removing the second photoresist layer are all photoresist coating, drying, exposure, development and stripping processes commonly used in the photolithography process, which will not be repeated here.
[0091] Specifically, the method of forming the first trench includes dry etching, wet etching or other suitable methods, that is, etching the epitaxial layer 21, the second sacrificial layer, the second electrode layer 123, the first sacrificial layer and the first electrode layer 121 respectively by dry etching or wet etching.
[0092] Specifically, the material of the support layer includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials.
[0093] Specifically, the method of forming the support layer includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0094] Specifically, during the formation of the second trench, the etching method for each film layer includes dry etching, wet etching, or other suitable methods; the removal method for the first sacrificial layer includes wet etching or other suitable methods; and the removal method for the second sacrificial layer includes wet etching or other suitable methods. In this embodiment, oxalic acid is used as a wet etchant to simultaneously remove the first and second sacrificial layers.
[0095] Specifically, the method for simultaneously forming the intermediate dielectric layer 122 , the isolation dielectric layer 13 and the second isolation portion includes atomic layer deposition or other suitable methods.
[0096] Specifically, after forming the second isolation portion, the intermediate dielectric layer 122 and the isolation dielectric layer 13 , the process further includes removing the support layer and forming the first isolation portion filling the first trench.
[0097] Specifically, the method of removing the support layer includes dry etching, wet etching or other suitable methods; the method of forming the first isolation portion includes chemical vapor deposition, physical vapor deposition or other suitable methods.
[0098] Specifically, the first isolation portion and the second isolation portion are made of the same material. The support layer is removed and the first isolation portion is formed with the same material as the second isolation portion to reduce the stress difference between the first isolation portion and the second isolation portion.
[0099] Specifically, while ensuring the performance of the device, the support layer may also be retained, that is, the support layer may be used as the first isolation portion.
[0100] As an example, the first electrode 5 includes a first conductive plug 51 that penetrates the epitaxial layer 21, the isolation dielectric layer 13, the second electrode layer 123 and the intermediate dielectric layer 122, and the second electrode 6 includes a second conductive plug 61 that penetrates the epitaxial layer 21 and the isolation dielectric layer 13. The first conductive plug 51 is insulated from the epitaxial layer 21 and the second electrode layer 123, and the second conductive plug 61 is insulated from the epitaxial layer 21.
[0101] Specifically, forming the first conductive plug 51 includes the following steps: forming a first contact hole penetrating the epitaxial layer 21, the isolation dielectric layer 13, the second plate layer 123 and the intermediate dielectric layer 122 in the area surrounded by the second isolation layer 14; forming a first dielectric layer 53 covering the inner wall of the first contact hole and forming a first conductive plug 51 filling the first contact hole.
[0102] Specifically, forming the second conductive plug 61 includes the following steps: forming a second contact hole penetrating the epitaxial layer 21 and the isolation dielectric layer 13 in the area surrounded by the second isolation layer 14; forming a second dielectric layer 63 covering the inner wall of the second contact hole and forming a second conductive plug 61 filling the second contact hole, and the second conductive plug 61 is spaced a preset distance from the first conductive plug 51.
[0103] Specifically, while ensuring device performance, the opening size and opening shape of the first contact hole can be selected according to actual conditions; the thickness of the first dielectric layer 53 can be selected according to actual conditions; the opening size and opening shape of the second contact hole can be selected according to actual conditions; and the thickness of the second dielectric layer 63 can be selected according to actual conditions.
[0104] Specifically, the first conductive plug 51 is electrically connected to the first electrode layer 121, and the second conductive plug 61 is electrically connected to the second electrode layer 123. The first dielectric layer 53 is used to insulate the first conductive plug 51 from the epitaxial layer 21 exposed on the inner wall of the first contact hole and the first electrode layer 121. The second dielectric layer 63 is used to insulate the second conductive plug 61 from the epitaxial layer 21 exposed on the inner wall of the second contact hole. The material of the first dielectric layer 53 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials; the material of the second dielectric layer 63 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials.
[0105] Specifically, the material of the first conductive plug 51 includes polysilicon, TiN, W or other suitable conductive materials; the material of the second conductive plug 61 includes polysilicon, TiN, W or other suitable conductive materials.
[0106] Specifically, after forming the first conductive plug 51 and the second conductive plug 61 , the gate structure 22 , the first region, and the second region are formed in sequence.
[0107] As an example, the gate structure 22 includes a gate dielectric layer 221 and a gate conductive layer 222 stacked in sequence. The end of the gate conductive layer 222 close to the first region extends above the first region, and the end of the gate conductive layer 222 close to the second region extends above the second region.
[0108] Specifically, the gate structure 22 is further provided with an isolation spacer 223 covering the sidewalls of the gate conductive layer 222 and the gate dielectric layer 221 . The thickness of the isolation spacer 223 can be selected according to actual conditions while ensuring device performance.
[0109] Specifically, after the first conductive plug 51 and the second conductive plug 61 are formed, a gate structure 22 is formed on the upper surface of the epitaxial layer 21 in the area between the first conductive plug 51 and the second conductive plug 61, and the gate structure 22 is spaced apart from the first conductive plug 51 and the second conductive plug 61; after the gate structure 22 is formed, a first region and a second region are formed on the upper surface of the epitaxial layer 21 on both sides of the gate structure 22 in the direction of the first conductive plug 51 pointing to the second conductive plug 61, the first region is located on a side of the gate structure 22 close to the first conductive plug 51 and is spaced apart from the first conductive plug 51, and the second region is located on a side of the gate structure 22 close to the second conductive plug 61 and is spaced apart from the second conductive plug 61.
[0110] Specifically, while ensuring device performance, the distance between the gate structure 22 and the first conductive plug 51 can be selected according to actual conditions; the distance between the second conductive plug 61 and the gate structure 22 can also be selected according to actual conditions.
[0111] Specifically, the method for forming the first region includes ion implantation or other suitable methods; the method for forming the second region includes ion implantation or other suitable methods. In this embodiment, an ion implantation process is used to simultaneously form a doped region located on the upper surface of the epitaxial layer 21. After the ion implantation is completed, a well-pull process is performed to extend the sidewall of the first region proximate to the second region to directly below the gate conductive layer 222, and the sidewall of the second region proximate to the first region to directly below the gate conductive layer 222.
[0112] As an example, the semiconductor device is further provided with an interlayer dielectric layer 3 covering the upper surface of the semiconductor structure 2 , and both the first electrode 5 and the second electrode 6 penetrate the interlayer dielectric layer 3 .
[0113] Specifically, the first electrode 5 also includes a third conductive plug 52 electrically connected to the first conductive plug 51, the second electrode 6 also includes a fourth conductive plug 62 electrically connected to the second conductive plug 61, the third conductive plug 52 penetrates the interlayer dielectric layer 3 and is electrically connected to the first conductive plug 51, the fourth conductive plug 62 penetrates the interlayer dielectric layer 3 and is electrically connected to the second conductive plug 61, the third electrode 7 penetrates the interlayer dielectric layer 3 and is electrically connected to the first region, the fourth electrode 8 penetrates the interlayer dielectric layer 3 and is electrically connected to the second region, and the fifth electrode 9 penetrates the interlayer dielectric layer 3 above the gate structure 22 and is electrically connected to the gate conductive layer 222.
[0114] Specifically, while ensuring device performance, the thickness of the interlayer dielectric layer 3 can be selected according to actual conditions; the cross-sectional size and cross-sectional shape of the third conductive plug 52 can be selected according to actual conditions; the cross-sectional size and cross-sectional shape of the fourth conductive plug 62 can be selected according to actual conditions; the cross-sectional size and cross-sectional shape of the third electrode 7 can be selected according to actual conditions; the cross-sectional size and cross-sectional shape of the fourth electrode 8 can be selected according to actual conditions; and the cross-sectional size and cross-sectional shape of the fifth electrode 9 can be selected according to actual conditions.
[0115] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride or other suitable dielectric materials; the material of the third conductive plug 52 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials; the material of the fourth conductive plug 62 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials; the material of the third electrode 7 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials; the material of the fourth electrode 8 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials; the material of the fifth electrode 9 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum or other suitable conductive materials.
[0116] Specifically, the upper surfaces of the first region, the second region and the gate conductive layer 222 are further provided with a first contact layer 23, a second contact layer 24 and a third contact layer 25, respectively. The first contact layer 23 is used to reduce the contact resistance between the third electrode 7 and the first region, the second contact layer 24 is used to reduce the contact resistance between the fourth electrode 8 and the second region, and the third contact layer 25 is used to reduce the contact resistance between the fifth electrode 9 and the gate conductive layer 222.
[0117] Specifically, a fourth contact layer 26 is provided on the upper surface of the first conductive plug 51 to reduce the contact resistance between the first conductive plug 51 and the third conductive plug 52 , and a fifth contact layer 27 is provided on the upper surface of the second conductive plug 61 to reduce the contact resistance between the second conductive plug 61 and the fourth conductive plug 62 .
[0118] Specifically, the first contact layer 23 is made of metal silicide, titanium nitride, or other suitable materials; the second contact layer 24 is made of metal silicide, titanium nitride, or other suitable materials; the third contact layer 25 is made of metal silicide, titanium nitride, or other suitable materials; the fourth contact layer 26 is made of metal silicide, titanium nitride, or other suitable materials; and the fifth contact layer 27 is made of metal silicide, titanium nitride, or other suitable materials. Preferably, in this embodiment, the first contact layer 23, the second contact layer 24, and the third contact layer 25 are metal silicide layers generated by a reaction between a metal layer and silicon on the surface of the epitaxial layer 21 and the gate conductive layer 222.
[0119] Specifically, while ensuring device performance, the thickness of each contact layer (the first contact layer 23 , the second contact layer 24 , the third contact layer 25 , the fourth contact layer 26 and the fifth contact layer 27 ) can be selected according to actual conditions.
[0120] As an example, the semiconductor device is also provided with a first interconnection layer 41 electrically connected to the first electrode 5, a second interconnection layer 42 electrically connected to the second electrode 6 and the fourth electrode 8, a third interconnection layer 43 electrically connected to the third electrode 7, and a fourth interconnection layer 44 electrically connected to the fifth electrode 9.
[0121] Specifically, the semiconductor device further includes an insulating layer 4 covering the interlayer dielectric layer 3 and the exposed upper surfaces of the electrodes. The first interconnection layer 41 , the second interconnection layer 42 , the third interconnection layer 43 and the fourth interconnection layer 44 respectively penetrate the insulating layer 4 .
[0122] Specifically, while ensuring device performance, the cross-sectional size and cross-sectional shape of each interconnection layer (first interconnection layer 41, second interconnection layer 42, third interconnection layer 43 and fourth interconnection layer 44) can be selected according to actual conditions; the distance between the first interconnection layer 41, second interconnection layer 42, third interconnection layer 43 and fourth interconnection layer 44 can be selected according to actual conditions.
[0123] Specifically, the material of the first interconnection layer 41 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum, platinum or other suitable conductive materials; the material of the second interconnection layer 42 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum, platinum or other suitable conductive materials; the material of the third interconnection layer 43 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum, platinum or other suitable conductive materials; the material of the fourth interconnection layer 44 includes titanium nitride, tungsten, titanium, gold, silver, copper, nickel, aluminum, platinum or other suitable conductive materials.
[0124] Specifically, in a semiconductor device, the electrical connection between the third electrode 7 and the fourth electrode 8 is usually controlled by the fifth electrode 9 in the semiconductor structure, and then the fourth electrode 8 is electrically connected to the second electrode 6 electrically connected to the second electrode layer 123. At the same time, the first electrode 5 electrically connected to the first electrode layer 121 is separated and insulated from the third electrode 7 of the semiconductor structure, so that the storage capacitor composed of the first electrode layer 121, the intermediate dielectric layer 122 and the second electrode layer 123 is connected in series with the semiconductor structure 2, and then the semiconductor structure is used as a switch of the storage capacitor to control access to the storage capacitor, and the first electrode 5 and the third electrode 7 can be connected to appropriate potential points according to the actual needs of the capacitor to facilitate writing and reading of stored information.
[0125] Specifically, by adopting the heavily doped layers formed by the deposition process as the first electrode layer 121 and the second electrode layer 123, respectively, the problems of uneven distribution of doped particles and damage to the electrode layer in the electrode layer made by the ion implantation process are avoided, the quality of the first electrode layer 121 and the second electrode layer 123 is ensured, the storage capacity of the storage capacitor is improved, and the performance of the device is enhanced. At the same time, it also avoids the problem of difficulty in obtaining a thinner top silicon in the bonding process.
[0126] Specifically, by disposing the storage capacitor composed of the first electrode layer 121, the intermediate dielectric layer 122 and the second electrode layer 123 below the semiconductor structure 2, the storage capacitor is prevented from occupying a large space, the size of the device is reduced, and the integration of the device is improved.
[0127] In summary, the semiconductor device of the present invention improves the device structure by placing the storage capacitor composed of the first plate layer, the intermediate dielectric layer, and the second plate layer between the substrate and the device in the semiconductor structure, thereby avoiding the storage capacitor from occupying a large space, reducing the size of the device, and improving the device integration. At the same time, because the heavily doped layers formed by the deposition process serve as the first plate layer and the second plate layer, respectively, the quality of the first plate layer and the second plate layer is guaranteed, the storage capacity of the storage capacitor is improved, and the performance of the device is enhanced. Therefore, the present invention effectively overcomes the various shortcomings of the existing technology and has high industrial utilization value.
[0128] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed in the present invention are intended to be covered by the claims of the present invention.
Claims
1. A semiconductor device, characterized in that: include: The substrate structure comprises at least a laminated structure and an isolation dielectric layer covering an upper surface of the laminated structure, wherein the laminated structure comprises a first electrode layer, an intermediate dielectric layer, and a second electrode layer stacked in sequence; a semiconductor structure located on an upper surface of the isolation dielectric layer, the semiconductor structure comprising a third electrode, a fourth electrode, and a gate structure, wherein the gate structure controls the on / off electrical connection between the third electrode and the fourth electrode; a first electrode, one end of which is electrically connected to the first electrode layer, and the other end of which is at least partially located outside the substrate structure; A second electrode has one end electrically connected to the second electrode layer, and the other end of the second electrode is at least partially located outside the substrate structure and electrically connected to the fourth electrode.
2. The semiconductor device according to claim 1, wherein: The substrate structure further includes a base, and the first electrode layer is located above the base.
3. The semiconductor device according to claim 2, wherein: The substrate structure further includes a first isolation layer covering the upper surface of the base, and the stacked structure covers the upper surface of the first isolation layer.
4. The semiconductor device according to claim 1, wherein: The doping concentration of the first electrode layer and the second electrode layer is the same; the thickness of the first electrode layer and the second electrode layer is different.
5. The semiconductor device according to claim 1, wherein: The semiconductor structure also includes a first conductive type epitaxial layer, a second conductive type first region and a second conductive type second region and a fifth electrode located on the upper surface of the epitaxial layer. The third electrode, the fourth electrode and the gate structure are located on the upper surface of the epitaxial layer. The first region and the second region are located on two opposite sides of the gate structure. The third electrode is electrically connected to the first region, the fourth electrode is electrically connected to the second region, and the fifth electrode is electrically connected to the gate structure.
6. The semiconductor device according to claim 5, wherein: The gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence. An end of the gate conductive layer close to the first region extends above the first region, and an end of the gate conductive layer close to the second region extends above the second region.
7. The semiconductor device according to claim 5, wherein: The epitaxial layer is also provided with a second isolation layer that passes through the epitaxial layer, the isolation dielectric layer and the stacked structure. The second isolation layer includes a first isolation portion and a second isolation portion that are connected in sequence. The first isolation portion and the second isolation portion are connected end to end in sequence and surround the areas where the first region and the second region are located, and the second isolation layer is separated from the first region and the second region by a preset distance.
8. The semiconductor device according to claim 5, wherein: The first electrode includes a first conductive plug that penetrates the epitaxial layer, the isolation dielectric layer, the second electrode layer and the intermediate dielectric layer; the second electrode includes a second conductive plug that penetrates the epitaxial layer and the isolation dielectric layer; the first conductive plug is insulated from the epitaxial layer and the second electrode layer; and the second conductive plug is insulated from the epitaxial layer.
9. The semiconductor device according to claim 5, wherein: The semiconductor device is further provided with a first interconnection layer electrically connected to the first electrode, a second interconnection layer electrically connected to the second electrode and the fourth electrode, a third interconnection layer electrically connected to the third electrode, and a fourth interconnection layer electrically connected to the fifth electrode.
10. The semiconductor device according to claim 1, wherein: The semiconductor device is further provided with an interlayer dielectric layer covering the upper surface of the semiconductor structure, and the first electrode and the second electrode both penetrate the interlayer dielectric layer.