Intelligent substation system-level time characteristic test system

Abstract

The utility model discloses an intelligent substation system-level time characteristic test system, which relates to the technical field of power system automation and comprises a data communication module, a signal conditioning module, a filter module, a converter module, a processor module, a time interval detector, a tested clock module, a to-be-tested substation interface module and a power supply module. The data communication module is connected with the standard clock through a network and is synchronized with the standard clock through the network, meanwhile, interference is filtered out through the filter module, the time difference of the standard clock is calculated according to regional changes, and therefore the accuracy of the clock module is more accurately tested, time deviation is visually displayed in a waveform display mode, and the accuracy of the clock module is improved. Therefore, time unification of the power grid is ensured, the power grid is enabled to operate more stably, and the system has popularization and application values.

Description

Technical Field

[0001] The utility model relates to the technical field of power system automation, in particular to a system-level time characteristic testing system for an intelligent substation. Background Art

[0002] A substation is a location within a power system that transforms voltage and current, receives electricity, and distributes it. The substation within a power plant is a step-up substation, whose function is to boost the voltage of electricity generated by the generator and feed it into the high-voltage grid.

[0003] In power systems, automation devices in smart substations, such as protection and measurement and control systems, monitor and control the entire substation's primary and secondary equipment. They also offer time-sensitive testing capabilities, including remote control holdover time, remote signaling anti-shake, and SOE resolution. With the development of smart grids, an increasing number of new smart substations are being built. The reliability and performance of these devices directly impacts the safe operation of substations, making testing of smart substation automation devices crucial.

[0004] In the existing technology, mobile substations are usually composed of modular substations. However, after the modular substation is moved or during the movement, signal interference, position changes, etc. may cause grid time inconsistency, and the economical and stable operation of the grid cannot be guaranteed. Therefore, there is room for improvement. Utility Model Content

[0005] The purpose of the present invention is to provide a system-level time characteristic test system for an intelligent substation in view of the defects and deficiencies of the prior art, so as to solve the problems of inconvenient and low-precision testing of intelligent substation automation devices in the prior art.

[0006] To achieve the above objectives, the present invention provides the following technical solutions:

[0007] A system-level time characteristic test system for an intelligent substation includes a data communication module, a signal conditioning module, a filter module, a converter module, a processor module, a time interval detector, a clock module to be tested, an interface module for a substation to be tested, and a power supply module. The data communication module receives a standard clock signal through a network. The signal output end of the data communication module is connected to the signal input end of the filter module. The signal output end of the filter module is connected to the signal input end of the signal converter module. The signal output end of the converter module is connected to the signal input end of the processor module. The signal output end of the processor module is connected to the input end of the clock module to be tested. The signal output end of the clock module to be tested is connected to the signal input end of the clock module to be tested. The output end is connected to the signal input end of the time interval detector, and the signal transmission end of the time interval detector is connected to the time signal feedback end of the processor module; the substation interface module and the power supply module to be tested are respectively connected to the processor module; the processor module includes a high-stable crystal oscillator module, an FPGA main control module, a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface and an HDMI interface, the high-stable crystal oscillator module is connected to the FPGA main control module, and the FPGA main control module is connected to the data processing center through the SB transmission module and the serial port module respectively, and the USB interface, the gigabit network interface and the HDMI interface are respectively connected to the data processing center.

[0008] As a further preferred solution of the intelligent substation system-level time characteristic test system of the utility model, the data communication module includes a radio frequency switch circuit and a wireless radio frequency chip, and the radio frequency switch circuit is connected to the wireless radio frequency chip.

[0009] As a further preferred solution of the system-level time characteristic test system of an intelligent substation of the utility model, the signal conditioning module includes three-phase voltage, voltage transformer, three-phase current, current transformer, sampling amplifier circuit, low-pass filter circuit, and sampling and holding module; the three-phase voltage is connected to the sampling amplifier circuit through the voltage transformer, the three-phase current is connected to the sampling amplifier circuit through the current transformer, and the sampling amplifier circuit is connected to the sampling and holding module through the low-pass filter circuit.

[0010] As a further preferred solution of a system-level time characteristic test system for an intelligent substation of the present invention, the power supply module includes a high-frequency drive circuit and a gallium nitride high-power device and a filter module connected thereto. The high-frequency drive circuit includes a low-voltage difference linear regulator, a waveform generation circuit, a level shifting module, a dead time processing circuit and a non-overlapping module, and a delay calibration circuit. The output end of the low-voltage difference linear regulator is respectively connected to the input end of the level shifting module and the input end of the dead time processing circuit and the non-overlapping module. The output end of the waveform generation circuit is connected to the input end of the dead time processing circuit and the non-overlapping module. The output end of the dead time processing circuit and the non-overlapping module is connected to the input end of the delay calibration circuit.

[0011] As a further preferred embodiment of the present invention, a system-level time characteristic test system for a smart substation, the radio frequency switch circuit includes a radio frequency RF terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a radio frequency ANT terminal, a voltage V CTRL Terminal and voltage V CTRI The radio frequency (RF) terminal is respectively connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4. The other end of the fifth resistor R5 is respectively connected to the source of the third NMOS transistor Q3, the drain of the second NMOS transistor Q2, and one end of the third resistor R3. The other end of the third resistor R3 is respectively connected to the source of the second NMOS transistor Q2 of the first NMOS transistor Q1, the drain of the first NMOS transistor Q1, and one end of the first resistor R1. The other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and is grounded. The base of the first NMOS transistor Q1 is connected to the anode of the first diode, the cathode of the first diode is respectively connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2. The other end of the second resistor R2 is respectively connected to one end of the fourth resistor R4 and the voltage V CTRIThe gate of the fourth NMOS transistor Q4 is connected to the cathode of the fourth diode D4 and one end of the eighth resistor R8, and the other end of the seventh resistor R7 is connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and the drain of the first and second NMOS transistors Q5. One end of the ninth resistor R9 and the gate of the fifth NMOS transistor Q5 are respectively connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the base of the fifth diode D5. The source of the fifth NMOS transistor Q5 is respectively connected to the other end of the ninth resistor R9, one end of the eleventh resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is respectively connected to one end of the twelfth resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the base of the sixth diode D6. The other end of the twelfth resistor R12 is connected to the other end of the eighth resistor R8. The other end of the tenth resistor R10 is connected to the voltage V CTRL The source of the sixth NMOS transistor Q6 is connected to the other end of the eleventh resistor R11 and the radio frequency ANT terminal respectively.

[0012] As a further preferred solution of the system-level time characteristic test system of an intelligent substation of the utility model, the high-stable crystal oscillator module includes a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69 and a voltage VCC end. The 8-interface of the control chip 7N10.000MBP is connected to one end of the resistor R22, and the other end of the resistor R22 is respectively connected to one end of the capacitor C45, the 9-interface of the control chip 7N10.000MBP, one end of the resistor R23 and the voltage VCC end. The other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is grounded. The 10-interface of the control chip 7N10.000MBP is connected to one end of the capacitor C69, and the other end of the capacitor C69 is grounded.

[0013] As a further preferred solution of the intelligent substation system-level time characteristic testing system of the utility model, the dead time processing circuit and the non-overlapping module include a level comparison circuit, a non-overlapping processing module, and a bias circuit processing module, and the bias circuit processing module is connected to the level comparison circuit through the non-overlapping processing module.

[0014] As a further preferred solution of the intelligent substation system-level time characteristic testing system of the utility model, the level shifting module includes a signal delay calibration unit and a shifting level processing unit, the level comparison circuit is connected to the signal delay calibration unit, and the signal delay calibration unit is connected to the shifting level processing unit.

[0015] Compared with the prior art, the above technical solution adopted by the present invention has the following technical effects:

[0016] The utility model discloses a system-level time characteristic test system for an intelligent substation, comprising a data communication module, a signal conditioning module, a filter module, a converter module, a processor module, a time interval detector, a clock module to be tested, an interface module for the substation to be tested and a power supply module; the data communication module is connected to a standard clock via a network and synchronized with the standard clock via the network; at the same time, interference is filtered out by the filter module, and the time difference of the standard clock is calculated according to regional changes, so as to more accurately test the accuracy of the clock module; the time deviation is then intuitively displayed in a waveform display mode, which is convenient for staff to monitor, thereby ensuring the time uniformity of the power grid and making the power grid run more stably, and having the value of popularization and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application, but do not constitute an improper limitation of the present invention. In the drawings:

[0018] Figure 1 This is a structural principle diagram of a system-level time characteristic test system for an intelligent substation according to the present utility model;

[0019] Figure 2 This is a schematic diagram of the structure of the processor module of the present utility model;

[0020] Figure 3 This is a schematic diagram of the structure of the signal conditioning module of the utility model;

[0021] Figure 4 This is a structural schematic diagram of the power supply module of the utility model;

[0022] Figure 5 This is a circuit diagram of the radio frequency switch circuit of the utility model;

[0023] Figure 6 This is the circuit diagram of the high-stable crystal oscillator module of the utility model;

[0024] Figure 7 This is a schematic diagram of the dead time processing circuit and non-overlapping module of the utility model;

[0025] Figure 8 This is a structural principle diagram of the level shifting module of the utility model. DETAILED DESCRIPTION

[0026] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The exemplary embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention:

[0028] A system-level time characteristic test system for smart substations, such as Figure 1 As shown, it includes a data communication module, a signal conditioning module, a filter module, a converter module, a processor module, a time interval detector, a clock module to be tested, an interface module for a substation to be tested, and a power supply module. The data communication module receives a standard clock signal through a network. The signal output end of the data communication module is connected to the signal input end of the filter module, the signal output end of the filter module is connected to the signal input end of the signal converter module, the signal output end of the converter module is connected to the signal input end of the processor module, the signal output end of the processor module is connected to the input end of the clock module to be tested, the signal output end of the clock module to be tested is connected to the signal input end of the time interval detector, and the signal transmission end of the time interval detector is connected to the time signal feedback end of the processor module; the interface module for the substation to be tested and the power supply module are respectively connected to the processor module;

[0029] The data communication module is connected to the standard clock through the network and synchronized with the standard clock through the network. At the same time, the filter module filters out interference and calculates the time difference of the standard clock according to regional changes, so as to more accurately test the accuracy of the clock module. The waveform display method is then used to intuitively display the time deviation, which is convenient for staff to monitor, thereby ensuring the time uniformity of the power grid and making the power grid run more stably. It has the value of promotion and application.

[0030] like Figure 2 As shown, the processor module includes a high-stable crystal oscillator module, an FPGA main control module, a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface and an HDMI interface. The high-stable crystal oscillator module is connected to the FPGA main control module, and the FPGA main control module is connected to the data processing center through the SB transmission module and the serial port module respectively. The USB interface, gigabit network interface and HDMI interface are respectively connected to the data processing center.

[0031] The FPGA master control module uses Xilinx's Artix-7 series FPGA as the main control chip. The FPGA core board serves as the core component of the entire track dynamic and static combined rapid detection multi-source data acquisition system. This submodule mainly completes the processing of high-speed signal interfaces such as Gigabit Ethernet, USB3.0, and HDMI, AD conversion control and data transmission, high-precision time base establishment data synchronization acquisition, encoder data synchronization acquisition and other core tasks, and is connected to the interface board through connectors.

[0032] The data processing center uses NVIDIA's Jetson TX2. This device uses the PPS pulses and NEMA data output by a highly stable crystal oscillator to establish a high-precision time base, leveraging the advantages of FPGA high-speed parallelism. NVIDIA's Jetson TX2 serves as the data processing and fusion center. The TX2 communicates with the host computer via a Gigabit Ethernet interface, receiving control commands from the host computer and communicating with the FPGA chip on the FPGA core board via a serial port. The FPGA then synchronously collects sensor data via a USB transmission module.

[0033] The data communication module includes a radio frequency switch circuit and a wireless radio frequency chip, and the radio frequency switch circuit is connected to the wireless radio frequency chip. Figure 3 As shown, the signal conditioning module includes three-phase voltage, voltage transformer, three-phase current, current transformer, sampling amplifier circuit, low-pass filter circuit, and sampling and holding module; the three-phase voltage is connected to the sampling amplifier circuit through the voltage transformer, the three-phase current is connected to the sampling amplifier circuit through the current transformer, and the sampling amplifier circuit is connected to the sampling and holding module through the low-pass filter circuit.

[0034] like Figure 4 As shown, the power supply module includes a high-frequency drive circuit and a gallium nitride high-power device and a filter module connected thereto. The high-frequency drive circuit includes a low-voltage dropout linear regulator, a waveform generation circuit, a level shifting module, a dead time processing circuit and a non-overlapping module, and a delay calibration circuit. The output end of the low-voltage dropout linear regulator is respectively connected to the input end of the level shifting module and the input end of the dead time processing circuit and the non-overlapping module. The output end of the waveform generation circuit is connected to the input end of the dead time processing circuit and the non-overlapping module. The output end of the dead time processing circuit and the non-overlapping module is connected to the input end of the delay calibration circuit.

[0035] like Figure 5As shown, the RF switch circuit includes a RF terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a RF ANT terminal, and a voltage V CTRL Terminal and voltage V CTRI The radio frequency (RF) terminal is respectively connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4. The other end of the fifth resistor R5 is respectively connected to the source of the third NMOS transistor Q3, the drain of the second NMOS transistor Q2, and one end of the third resistor R3. The other end of the third resistor R3 is respectively connected to the source of the second NMOS transistor Q2 of the first NMOS transistor Q1, the drain of the first NMOS transistor Q1, and one end of the first resistor R1. The other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and is grounded. The base of the first NMOS transistor Q1 is connected to the anode of the first diode, the cathode of the first diode is respectively connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2. The other end of the second resistor R2 is respectively connected to one end of the fourth resistor R4 and the voltage V CTRIThe gate of the fourth NMOS transistor Q4 is connected to the cathode of the fourth diode D4 and one end of the eighth resistor R8, and the other end of the seventh resistor R7 is connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and the drain of the first and second NMOS transistors Q5. One end of the ninth resistor R9 and the gate of the fifth NMOS transistor Q5 are respectively connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the base of the fifth diode D5. The source of the fifth NMOS transistor Q5 is respectively connected to the other end of the ninth resistor R9, one end of the eleventh resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is respectively connected to one end of the twelfth resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the base of the sixth diode D6. The other end of the twelfth resistor R12 is connected to the other end of the eighth resistor R8. The other end of the tenth resistor R10 is connected to the voltage V CTRL The source of the sixth NMOS transistor Q6 is connected to the other end of the eleventh resistor R11 and the radio frequency ANT terminal respectively.

[0036] The radio frequency switch circuit of the present utility model can better meet the requirements of large voltage swing operation under the premise of ensuring insertion loss and isolation. It improves the traditional stacking technology, weakens the uneven voltage distribution, significantly improves the branch voltage processing capability, and improves the branch voltage tolerance capability, so as to be better used for antenna tuning and meet the requirements of normal operation under the condition of antenna mismatch; the radio frequency switch part adopts a series-parallel structure, and the control signals of the two branches are complementary; when the series branch is turned on, it is equivalent to a small resistor, and the parallel branch is turned off, which is equivalent to a capacitor and a resistor in parallel.

[0037] The wireless RF chip uses the nRF905 wireless transceiver chip. This long-range wireless transceiver chip features multiple transmission points, a long transmission distance, and strong anti-interference capabilities. It operates in three ISM frequency bands: 433 / 868 / 915 MHz, and the switching time between transceiver modes is less than 650 μs. Ports such as TRX_CE, PWR_UP, TXEN, CSN, SCK, MISO, and MOSI are connected to the microcontroller, with CSN, SCK, MISO, and MOSI forming the SPI interface. When transmitting data, the nRF905 is set to transmit mode. The microcontroller writes the receiving point address and valid data to the chip buffer via the SPI interface, then generates a CRC and preamble based on the TRX_CE level, and transmits the data. When receiving data, the nRF905 is set to receive mode and waits for incoming data. Upon receiving the preamble, valid address, and CRC, the data is stored in a register, generating an interrupt to allow the microcontroller to read the data.

[0038] like Figure 6 As shown, the high-stable crystal oscillator module includes a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69, and a voltage VCC terminal. The 8-port of the control chip 7N10.000MBP is connected to one end of the resistor R22, and the other end of the resistor R22 is respectively connected to one end of the capacitor C45, the 9-port of the control chip 7N10.000MBP, one end of the resistor R23, and the voltage VCC terminal. The other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is grounded. The 10-port of the control chip 7N10.000MBP is connected to one end of the capacitor C69, and the other end of the capacitor C69 is grounded. The high-stable crystal oscillator module of the utility model has good short-term stability due to the high-stable crystal oscillator.

[0039] like Figure 7 As shown, the dead time processing circuit and the non-overlapping module include a level comparison circuit, a non-overlapping processing module, and a bias circuit processing module. The bias circuit processing module is connected to the level comparison circuit through the non-overlapping processing module.

[0040] like Figure 8 As shown, the level shifting module includes a signal delay calibration unit and a shifting level processing unit, the level comparison circuit is connected to the signal delay calibration unit, and the signal delay calibration unit is connected to the shifting level processing unit.

[0041] The utility model integrates dead time adjustment and non-overlapping modules in one. The non-overlapping function can strictly control the high-side power tube and the low-side power tube drive signals to output high levels at the same time, thereby preventing the two power devices from being turned on at the same time and effectively suppressing the large current shoot-through phenomenon. The dead time adjustment function can reduce the time when the drive waveform is simultaneously at a low level, thereby improving the conversion efficiency of the power supply system within the entire cycle.

[0042] The utility model suppresses the high-current shoot-through phenomenon of the power device by adjusting the dead zone minimization processing module and the non-overlapping module, which helps to improve the efficiency of the power module and utilizes the high-frequency characteristics of the gallium nitride device to significantly increase the operating frequency of the power system.

[0043] The dead time processing circuit and the non-overlapping module include a level comparison circuit, a non-overlapping processing module, and a bias circuit processing module. The bias circuit processing module is connected to the level comparison circuit through the non-overlapping processing module.

[0044] The level shifting module includes a signal delay calibration unit and a shifting level processing unit. The level comparison circuit is connected to the signal delay calibration unit, and the signal delay calibration unit is connected to the shifting level processing unit.

[0045] The GaN high-power device and filter module includes two GaN enhancement-mode NMOS devices and a low-resistance inductor and capacitor filter module. These devices help improve the high-frequency performance of the drive circuit. The output stage of this drive circuit is composed of two GaN enhancement-mode NMOS devices and a low-resistance inductor and capacitor filter module. The unique characteristics of GaN devices increase the operating frequency of the overall drive waveform, while the low-resistance inductor and capacitor filter module ensures minimal loss while completing the filtering.

[0046] The above description is only a preferred embodiment of the present invention. Therefore, any equivalent changes or modifications made according to the structure, features and principles described in the scope of the present invention patent application are included in the scope of the present invention patent application.

[0047] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which this invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and, unless defined as such, will not be interpreted in an idealized or overly formal sense.

[0048] The above embodiments are only for the purpose of illustrating the technical concept of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications made based on the technical solution in accordance with the technical concept of the present invention shall fall within the scope of protection of the present invention. The above embodiments of the present invention are described in detail, but the present invention is not limited to the above embodiments. Various modifications can be made within the scope of knowledge possessed by ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A system-level time characteristic test system for a smart substation, characterized by: The system comprises a data communication module, a signal conditioning module, a filter module, a converter module, a processor module, a time interval detector, a clock module to be tested, an interface module for a substation to be tested and a power supply module. The data communication module receives a standard clock signal through a network. The signal output end of the data communication module is connected to the signal input end of the filter module, the signal output end of the filter module is connected to the signal input end of the signal converter module, the signal output end of the converter module is connected to the signal input end of the processor module, the signal output end of the processor module is connected to the input end of the clock module to be tested, the signal output end of the clock module to be tested is connected to the signal input end of the time interval detector, and the signal transmission end of the time interval detector is connected to the time signal feedback end of the processor module; the interface module for a substation to be tested and the power supply module are respectively connected to the processor module; the processor module comprises a high-stability crystal oscillator module, an FPGA main control module, a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface and an HDMI interface. The high-stability crystal oscillator module is connected to the FPGA main control module, the FPGA main control module is connected to the data processing center via the SB transmission module and the serial port module respectively, and the USB interface, the gigabit network interface and the HDMI interface are respectively connected to the data processing center.

2. The system-level time characteristic test system for a smart substation according to claim 1, characterized in that: The data communication module includes a radio frequency switch circuit and a wireless radio frequency chip, and the radio frequency switch circuit is connected to the wireless radio frequency chip.

3. The intelligent substation system-level time characteristic test system according to claim 1, characterized in that: The signal conditioning module includes three-phase voltage, voltage transformer, three-phase current, current transformer, sampling amplifier circuit, low-pass filter circuit, and sampling and holding module; the three-phase voltage is connected to the sampling amplifier circuit through the voltage transformer, the three-phase current is connected to the sampling amplifier circuit through the current transformer, and the sampling amplifier circuit is connected to the sampling and holding module through the low-pass filter circuit.

4. The intelligent substation system-level time characteristic test system according to claim 1, characterized in that: The power supply module includes a high-frequency drive circuit and a gallium nitride high-power device and a filter module connected thereto. The high-frequency drive circuit includes a low-voltage dropout linear regulator, a waveform generation circuit, a level shifting module, a dead-time processing circuit and a non-overlapping module, and a delay calibration circuit. The output end of the low-voltage dropout linear regulator is respectively connected to the input end of the level shifting module and the input end of the dead-time processing circuit and the non-overlapping module. The output end of the waveform generation circuit is connected to the input end of the dead-time processing circuit and the non-overlapping module. The output end of the dead-time processing circuit and the non-overlapping module is connected to the input end of the delay calibration circuit.

5. The intelligent substation system-level time characteristic test system according to claim 2, characterized in that: The radio frequency switch circuit includes a radio frequency (RF) terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a radio frequency (ANT) terminal, and a voltage V CTRL Terminal and voltage V CTRI The radio frequency (RF) terminal is respectively connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4. The other end of the fifth resistor R5 is respectively connected to the source of the third NMOS transistor Q3, the drain of the second NMOS transistor Q2, and one end of the third resistor R3. The other end of the third resistor R3 is respectively connected to the source of the second NMOS transistor Q2 of the first NMOS transistor Q1, the drain of the first NMOS transistor Q1, and one end of the first resistor R1. The other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and is grounded. The base of the first NMOS transistor Q1 is connected to the anode of the first diode, the cathode of the first diode is respectively connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2. The other end of the second resistor R2 is respectively connected to one end of the fourth resistor R4 and the voltage V CTRI The gate of the fourth NMOS transistor Q4 is connected to the cathode of the fourth diode D4 and one end of the eighth resistor R8, and the other end of the seventh resistor R7 is connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and the drain of the first and second NMOS transistors Q5. One end of the ninth resistor R9 and the gate of the fifth NMOS transistor Q5 are respectively connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the base of the fifth diode D5. The source of the fifth NMOS transistor Q5 is respectively connected to the other end of the ninth resistor R9, one end of the eleventh resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is respectively connected to one end of the twelfth resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the base of the sixth diode D6. The other end of the twelfth resistor R12 is connected to the other end of the eighth resistor R8. The other end of the tenth resistor R10 is connected to the voltage V CTRL The source of the sixth NMOS transistor Q6 is connected to the other end of the eleventh resistor R11 and the radio frequency ANT terminal respectively.

6. The intelligent substation system-level time characteristic test system according to claim 1, characterized in that: The high-stable crystal oscillator module includes a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69 and a voltage VCC end. The 8-interface of the control chip 7N10.000MBP is connected to one end of the resistor R22, and the other end of the resistor R22 is respectively connected to one end of the capacitor C45, the 9-interface of the control chip 7N10.000MBP, one end of the resistor R23 and the voltage VCC end. The other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is grounded. The 10-interface of the control chip 7N10.000MBP is connected to one end of the capacitor C69, and the other end of the capacitor C69 is grounded.

7. The intelligent substation system-level time characteristic test system according to claim 4, characterized in that: The dead time processing circuit and the non-overlapping module include a level comparison circuit, a non-overlapping processing module, and a bias circuit processing module. The bias circuit processing module is connected to the level comparison circuit through the non-overlapping processing module.

8. The intelligent substation system-level time characteristic test system according to claim 7, characterized in that: The level shifting module includes a signal delay calibration unit and a shifting level processing unit. The level comparison circuit is connected to the signal delay calibration unit, and the signal delay calibration unit is connected to the shifting level processing unit.

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