Transient enhancement circuit applied to low dropout regulator

Abstract

The utility model provides a transient enhancement circuit applied to a low dropout regulator, and relates to the technical field of analog integrated circuits. The overvoltage detection circuit drives the charging and discharging circuit to charge the grid electrode of the power output tube to lower the output voltage when the output voltage of the low dropout linear regulator exceeds the first voltage threshold value, and meanwhile, the undervoltage detection circuit drives the charging and discharging circuit to charge the grid electrode of the power output tube to lower the output voltage when the output voltage is smaller than the second voltage threshold value. When the output voltage of the low dropout linear regulator changes instantly and rapidly along with a load or changes in a rapid jitter phenomenon of the input voltage, the charging and discharging circuit is driven to discharge the grid electrode of the power output tube so as to increase the output voltage. The low-dropout linear regulator can quickly and adaptively cooperate with a negative feedback loop included in the low-dropout linear regulator to realize a timely output voltage transient response adjustment effect, so that the corresponding output voltage can be effectively limited to a set threshold range and quickly recovered to a stable state.

Description

Technical Field

[0001] The present application relates to the field of analog integrated circuit technology, and in particular to a transient enhancement circuit applied to a low-dropout linear regulator. Background Art

[0002] Low Dropout Regulator (LDO) is widely used in various system on chip (SOC), digital chips or analog chips because it can provide a stable output voltage within a certain input voltage variation range and load variation range.

[0003] Currently, in the actual use of low-dropout linear regulators, the phenomenon of rapid load changes or rapid input voltage jitter often occurs. When faced with such phenomena, the low-dropout linear regulator will use its own negative feedback loop (including the error amplifier and feedback resistor network) to responsively adjust the gate voltage of the power output tube to provide an adaptive current to the load and ensure the stability of the output voltage. However, it is worth noting that due to the large output impedance and power consumption limitations of the error amplifier, and the large gate capacitance of the power output tube due to the driving requirements of the subsequent circuit, it is impossible to achieve timely output voltage transient response adjustment effect directly using the negative feedback loop. The corresponding output voltage will produce a large spike due to the rapid load change or rapid input voltage jitter, resulting in severe output voltage overshoot or undershoot, and it will take some time for the output voltage to return to a stable state. Utility Model Content

[0004] In view of this, the purpose of this application is to provide a transient enhancement circuit for a low-dropout linear regulator, which can quickly and adaptively cooperate with a negative feedback loop to achieve timely output voltage transient response adjustment when the output voltage of the low-dropout linear regulator changes with the load or the input voltage jitters rapidly, so that the output voltage can be effectively limited to a set threshold range and quickly restored to a stable state.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, the present application provides a transient enhancement circuit for a low-voltage-dropout linear regulator, the transient enhancement circuit comprising an overvoltage detection circuit, an undervoltage detection circuit, and a charge-discharge circuit, wherein the drain of a power output tube included in the low-voltage-dropout linear regulator serves as a voltage output terminal of the low-voltage-dropout linear regulator;

[0007] The signal input terminal of the overvoltage detection circuit is electrically connected to the drain of the power output tube, the signal output terminal of the overvoltage detection circuit is electrically connected to the first control terminal of the charge-discharge circuit, and the charge-discharge terminal of the charge-discharge circuit is electrically connected to the gate of the power output tube, wherein when the output voltage of the low-dropout linear regulator exceeds a first voltage threshold, the overvoltage detection circuit drives the charge-discharge circuit to charge the gate of the power output tube to lower the output voltage;

[0008] The signal input end of the undervoltage detection circuit is electrically connected to the drain of the power output tube, and the signal output end of the undervoltage detection circuit is electrically connected to the second control end of the charge-discharge circuit. When the output voltage is less than a second voltage threshold, the undervoltage detection circuit drives the charge-discharge circuit to discharge the gate of the power output tube to increase the output voltage. The second voltage threshold is less than the first voltage threshold.

[0009] In an optional embodiment, the overvoltage detection circuit includes a first P-channel MOS (Metal-Oxide-Semiconductor) tube;

[0010] The source of the first P-channel MOS transistor serves as a signal input terminal of the overvoltage detection circuit and is electrically connected to the drain of the power output transistor;

[0011] The drain of the first P-channel MOS transistor serves as a signal output terminal of the overvoltage detection circuit and is electrically connected to the first control terminal of the charge and discharge circuit;

[0012] The gate of the first P-channel MOS transistor is connected to a first reference voltage, and the first voltage threshold is obtained by adding the first reference voltage to an absolute value of the threshold voltage of the first P-channel MOS transistor.

[0013] In an optional embodiment, the undervoltage detection circuit includes a first N-channel MOS transistor;

[0014] The source of the first N-channel MOS transistor serves as the signal input terminal of the undervoltage detection circuit and is electrically connected to the drain of the power output transistor;

[0015] The drain of the first N-channel MOS transistor serves as the signal output terminal of the undervoltage detection circuit and is electrically connected to the second control terminal of the charge and discharge circuit;

[0016] The gate of the first N-channel MOS transistor is connected to a second reference voltage, and the second voltage threshold is obtained by subtracting an absolute value of the threshold voltage of the first N-channel MOS transistor from the second reference voltage.

[0017] In an optional embodiment, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other and externally connected to the same reference power supply; wherein the reference power supply is used to provide the first reference voltage and the second reference voltage with the same value.

[0018] In an optional embodiment, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other and electrically connected to the output end of the RC delay circuit; wherein the input end of the RC delay circuit is electrically connected to the drain of the power output tube, and the RC delay circuit provides the first reference voltage and the second reference voltage with the same value based on the output voltage.

[0019] In an optional embodiment, the charge and discharge circuit includes a P-channel current mirror structure and an N-channel current mirror structure;

[0020] The reference current input terminal of the N-channel current mirror structure serves as the first control terminal and is electrically connected to the signal output terminal of the overvoltage detection circuit;

[0021] The mirror current output terminal of the N-channel current mirror structure is electrically connected to the reference current input terminal of the P-channel current mirror structure;

[0022] The mirror current output end of the P-channel current mirror structure serves as the charging and discharging end and is electrically connected to the gate of the power output tube.

[0023] In an optional embodiment, when the undervoltage detection circuit is implemented using an N-channel MOS transistor, the second control terminal and the charge and discharge terminal are directly connected inside the charge and discharge circuit.

[0024] In an optional embodiment, the N-channel current mirror structure includes a second N-channel MOS transistor and a third N-channel MOS transistor;

[0025] The drain of the second N-channel MOS transistor serves as a reference current input terminal of the N-channel current mirror structure, and the drain and gate of the second N-channel MOS transistor are connected to each other;

[0026] The gate of the second N-channel MOS transistor and the gate of the third N-channel MOS transistor are connected to each other, and the source of each of the second N-channel MOS transistor and the third N-channel MOS transistor is grounded;

[0027] The drain of the third N-channel MOS transistor serves as the mirror current output end of the N-channel current mirror structure.

[0028] In an optional embodiment, the P-channel current mirror structure includes a second P-channel MOS transistor and a third P-channel MOS transistor;

[0029] The drain of the second P-channel MOS transistor serves as a reference current input terminal of the P-channel current mirror structure, and the drain and gate of the second P-channel MOS transistor are connected to each other;

[0030] The gate of the second P-channel MOS transistor and the gate of the third P-channel MOS transistor are connected to each other, and the sources of the second P-channel MOS transistor and the third P-channel MOS transistor are connected to each other and externally connected to a positive power supply voltage;

[0031] The drain of the third P-channel MOS transistor serves as the mirror current output end of the P-channel current mirror structure.

[0032] In an optional embodiment, the error amplifier included in the low-voltage difference linear regulator and the charge and discharge circuit reuse the same P-channel current mirror structure, and the positive power supply voltage of the P-channel current mirror structure is the input voltage of the low-voltage difference linear regulator at the voltage input terminal.

[0033] In this case, the beneficial effects of the embodiments of the present application may include the following:

[0034] The present application provides an overvoltage detection circuit to detect whether the output voltage of a low-dropout linear regulator exceeds a first voltage threshold. When the output voltage is detected to exceed the first voltage threshold, the charge-discharge circuit is driven to charge the gate of the power output tube to lower the output voltage. At the same time, an undervoltage detection circuit is provided to detect whether the output voltage is less than a second voltage threshold. When the output voltage is detected to be less than the second voltage threshold, the charge-discharge circuit is driven to discharge the gate of the power output tube to increase the output voltage. Therefore, when the output voltage of the low-dropout linear regulator changes with the load or the input voltage fluctuates rapidly, the negative feedback loop included in the low-dropout linear regulator is quickly and adaptively coordinated to achieve a timely output voltage transient response adjustment effect, so that the corresponding output voltage can be effectively limited to a set threshold range (i.e., between the second voltage threshold and the first voltage threshold) and quickly restored to a stable state.

[0035] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 Connection diagram of the transient enhancement circuit provided by the embodiment of the present application applied to one of the connection diagrams of the low dropout linear regulator;

[0038] Figure 2 Connection diagram of the transient enhancement circuit provided by the embodiment of the present application applied to one of the connection diagrams of the low dropout linear regulator;

[0039] Figure 3 Connection diagram of the transient enhancement circuit provided by the embodiment of the present application applied to one of the connection diagrams of the low dropout linear regulator;

[0040] Figure 4 Circuit composition diagram of the charge-discharge circuit provided by the embodiment of the present application;

[0041] Figure 5 Circuit composition diagram of the charge-discharge circuit provided by the embodiment of the present application;

[0042] Figure 6 Circuit connection diagram of the charge-discharge circuit and the P-channel current mirror structure of the error amplifier in the low dropout linear regulator;

[0043] Figure 7 Output voltage change diagram of the low dropout linear regulator connected before and after the transient enhancement circuit when the input voltage jumps from low to high;

[0044] Figure 8 Output voltage change diagram of the low dropout linear regulator connected before and after the transient enhancement circuit when the input voltage jumps from high to low.

[0045] Icon: 10-transient enhancement circuit; 11-overvoltage detection circuit; 12-under-voltage detection circuit; 13-charge-discharge circuit; 20-low dropout linear regulator; 131-N-channel current mirror structure; 132-P-channel current mirror structure. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0047] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0048] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0049] In the description of this application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the application is usually placed when in use, or are the orientation or position relationship commonly understood by those skilled in the art. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0050] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0051] Through painstaking research, the applicant discovered that the mainstream solutions currently adopted by the industry for the problem of poor transient response performance of low-dropout linear regulators include the following two:

[0052] Solution 1: Increase the dynamic bias current in the error amplifier of the low-dropout linear regulator to increase the gate slew rate of the power output transistor and improve transient response performance. However, this solution requires at least the response time of the error amplifier to provide feedback to the gate of the power output transistor. This makes the transient regulation of the low-dropout linear regulator's output voltage insufficient, and the suppression of output voltage overshoot and undershoot is ineffective. As a result, the corresponding output voltage still takes some time to return to a stable state.

[0053] Solution 2: By comparing the output voltage of a low-dropout linear regulator with a reference voltage in real time, a control signal is generated to directly control the gate of the power output transistor. However, this solution requires the use of a voltage comparator, which increases system power consumption in low-power applications. Furthermore, when an output voltage overshoot occurs, the output power transistor is directly shut off, causing the corresponding output voltage to take a long time to return to a stable state after the load stabilizes.

[0054] To address the aforementioned issues, embodiments of the present application provide a transient enhancement circuit for a low-dropout linear regulator (LDO). This circuit has a simple structure and can quickly and adaptively coordinate with a negative feedback loop to achieve timely output voltage transient response adjustment when the LDO's output voltage changes due to rapid transient load variations or rapid input voltage jitter. This allows the output voltage to be effectively limited to within a set threshold range and quickly restored to a stable state. The transient enhancement circuit operates only when the corresponding output voltage exceeds the set threshold range and does not operate when the corresponding output voltage is within the set threshold range. This circuit does not generate additional power consumption and does not affect the operation of the LDO.

[0055] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0056] Please refer to Figure 1 , Figure 1 This is one of the connection diagrams of the transient enhancement circuit 10 provided in the embodiment of the present application when applied to the low voltage drop linear regulator 20. In the embodiment of the present application, the low voltage drop linear regulator 20 can generally include a power output tube (i.e. Figure 1 The P-channel MOS tube MPout in the error amplifier (i.e. Figure 1 The amplifier EA) and the feedback resistor network (i.e. Figure 1 The feedback network is composed of the feedback resistors R1 and R2 in the circuit). The gate of the power output tube (i.e. Figure 1 The G port of the P-channel MOS tube MPout in the power supply is connected to the output end of the error amplifier, and the drain of the power output tube (i.e. Figure 1 The D port of the P-channel MOS tube MPout in the embodiment of the present invention is used as the voltage output terminal of the low voltage difference linear regulator 20 (ie Figure 1 The output voltage VOUT of the output port), the source of the power output tube (ie Figure 1The S port of the P-channel MOS transistor MPout in the circuit is connected to the input voltage VIN via the voltage input terminal. The voltage sampling terminal of the feedback resistor network (i.e., the end of the feedback resistor R1 not connected to the feedback resistor R2) is connected to the voltage output terminal of the low-dropout linear regulator 20. The ground terminal of the feedback resistor network (i.e., the end of the feedback resistor R2 not connected to the feedback resistor R1) is grounded. The sampling voltage output terminal of the feedback resistor network (i.e., the connection point of the feedback resistor R1 and the feedback resistor R2) is connected to the positive input terminal of the error amplifier, so that the error amplifier receives the feedback voltage VFB sampled by the feedback resistor network based on the output voltage through the positive input terminal. At the same time, the negative input terminal of the error amplifier is connected to the regulator reference voltage VREF. Under the influence of the input voltage, the error amplifier compares the feedback voltage with the regulator reference voltage and feeds back the amplified error signal to the gate of the power output transistor. By adjusting the on-resistance of the power output transistor, the current flowing through the power output transistor is adjusted, so that the corresponding output voltage gradually returns to a stable state. The voltage regulator reference voltage can be generated by various devices such as a bandgap reference voltage source and a Zener diode.

[0057] In the embodiment of the present application, the transient enhancement circuit 10 may include an overvoltage detection circuit 11 , an undervoltage detection circuit 12 and a charge and discharge circuit 13 .

[0058] In this embodiment, the signal input terminal (ie Figure 1 in1 port in) and the signal input terminal of the undervoltage detection circuit 12 (ie Figure 1 The in2 port in the output transistor is electrically connected to the drain of the power output transistor to obtain the output voltage of the low-dropout linear regulator 20.

[0059] The signal output terminal (i.e. Figure 1 out1 port in the charging and discharging circuit 13) and the first control terminal (i.e. Figure 1 The overvoltage detection circuit 11 detects whether the output voltage is greater than (exceeds) the first voltage threshold to determine whether the output voltage has an overshoot phenomenon. When the overvoltage detection circuit 11 detects that the output voltage exceeds the first voltage threshold, it determines that the output voltage has an overshoot phenomenon. At this time, the overvoltage detection circuit 11 sends a charging drive signal to the charge and discharge circuit 13 to drive the charge and discharge circuit 13 to charge and discharge the battery through the charge and discharge terminal (i.e. Figure 1The EO port in the low-voltage dropout linear regulator 20 charges the gate of the power output tube, thereby directly increasing the gate voltage of the power output tube independently of the error amplifier, reducing the output current of the low-voltage dropout linear regulator 20, and further lowering the drain voltage of the power output tube (that is, the output voltage VOUT of the low-voltage dropout linear regulator 20), thereby effectively suppressing the output voltage overshoot phenomenon and quickly lowering the output voltage to a state lower than the first voltage threshold, which is conducive to the output voltage quickly recovering to the steady-state voltage value in the normal working state.

[0060] The signal output terminal (ie Figure 1 out2 port in the charging and discharging circuit 13) and the second control terminal (i.e. Figure 2 The undervoltage detection circuit 12 detects whether the output voltage is less than a second voltage threshold to determine whether the output voltage has undershoot, wherein the second voltage threshold is less than the first voltage threshold, and the steady-state voltage value of the output voltage under normal working conditions is between the second voltage threshold and the first voltage threshold. When the undervoltage detection circuit 12 detects that the output voltage is less than the second voltage threshold, it determines that the output voltage has undershoot. At this time, the undervoltage detection circuit 12 sends a discharge drive signal to the charge-discharge circuit 13 to drive the charge-discharge circuit 13 to discharge the gate of the power output tube through the charge-discharge terminal, thereby directly reducing the gate voltage of the power output tube independently of the error amplifier, thereby increasing the output current of the low-dropout linear regulator 20, and thereby increasing the output voltage VOUT of the low-dropout linear regulator 20, thereby effectively suppressing the output voltage undershoot and quickly raising the output voltage to a state greater than the second voltage threshold, which is conducive to the output voltage quickly recovering to the steady-state voltage value under normal working conditions.

[0061] In the embodiment of the present application, the charge and discharge circuit 13 only works when the corresponding output voltage exceeds the set threshold range (i.e., the voltage value range defined by the second voltage threshold and the first voltage threshold), and does not work when the corresponding output voltage is within the threshold range, so as to avoid generating additional power consumption and at the same time avoid affecting the operation of the low voltage difference linear regulator 20.

[0062] Therefore, the transient enhancement circuit 10 provided in the embodiment of the present application has a simple structure and can quickly and adaptively cooperate with the negative feedback loop to achieve timely output voltage transient response adjustment effect when the output voltage of the low-dropout linear regulator 20 changes with the instantaneous rapid change of the load or the rapid jitter of the input voltage, so that the output voltage can be effectively limited to the set threshold range and then quickly restored to a stable state, while avoiding causing additional power consumption.

[0063] Alternatively, see Figure 2 , Figure 2 This is the second connection diagram of the transient enhancement circuit 10 provided in an embodiment of the present application, when applied to a low-dropout linear regulator 20. In this embodiment of the present application, to ensure that the charging drive signal generated by the overvoltage detection circuit 11 can reflect the magnitude of the output voltage, and to facilitate adaptive adjustment of the gate charging intensity of the power output transistor by the charge-discharge circuit 13 in accordance with the magnitude of the output voltage, thereby improving the smoothness of output voltage recovery, the overvoltage detection circuit 11 can be implemented using a P-channel MOS transistor. This utilizes the on-off characteristics of the P-channel MOS transistor to achieve the aforementioned objectives and effectively avoids generating additional static power consumption.

[0064] In this embodiment, the overvoltage detection circuit 11 may include a first P-channel MOS transistor (ie Figure 2 The source of the first P-channel MOS transistor (i.e. Figure 2 The S port of the P-channel MOS transistor MP1 in the middle is used as the signal input terminal of the overvoltage detection circuit 11 and is electrically connected to the drain of the power output tube; the drain of the first P-channel MOS transistor (i.e. Figure 2 The D port of the P-channel MOS transistor MP1 in the middle) serves as the signal output terminal of the overvoltage detection circuit 11 and is electrically connected to the first control terminal of the charge and discharge circuit 13; the gate of the first P-channel MOS transistor (i.e. Figure 2 The G port of the P-channel MOS transistor MP1 in the middle is connected to the first reference voltage (i.e. Figure 2 The first voltage threshold is obtained by adding the first reference voltage to the absolute value of the threshold voltage of the first P-channel MOS transistor (that is, the absolute value of the threshold voltage of the first P-channel MOS transistor), wherein the first reference voltage can be generated by various devices such as a bandgap reference voltage source and a Zener diode.

[0065] For the first P-channel MOS transistor, when the output voltage exceeds the first voltage threshold, the first P-channel MOS transistor turns on. At this point, the output current of the low-dropout linear regulator 20 is shunted through the first P-channel MOS transistor to the charge-discharge circuit 13. The shunted current signal represents the charge drive signal and simultaneously reflects the magnitude of the output voltage. This allows the charge-discharge circuit 13 to adaptively adjust the gate charging intensity of the power output transistor in accordance with the magnitude of the output voltage, thereby improving the smoothness of output voltage recovery. As the charge-discharge circuit 13 performs gate charging on the power output transistor, the output current of the low-dropout linear regulator 20 gradually decreases, and its output voltage also gradually decreases. At this point, the on-resistance of the first P-channel MOS transistor gradually increases, and when the output voltage is less than the first voltage threshold, the transistor is turned off, thereby preventing the overvoltage detection circuit 11 from generating additional static power consumption.

[0066] In the embodiment of the present application, to ensure that the discharge drive signal generated by the undervoltage detection circuit 12 can reflect the voltage magnitude of the output voltage, and to facilitate the adaptive adjustment of the gate discharge intensity of the power output tube by the charge and discharge circuit 13 according to the voltage magnitude of the output voltage, thereby improving the recovery smoothness of the output voltage, the undervoltage detection circuit 12 can be implemented using an N-channel MOS transistor, so as to utilize the device on-off characteristics of the N-channel MOS transistor to achieve the aforementioned various purposes and effectively avoid generating additional static power consumption.

[0067] In this embodiment, the undervoltage detection circuit 12 may include a first N-channel MOS transistor (ie Figure 2 The source of the first N-channel MOS transistor (i.e. Figure 2 The S port of the N-channel MOS transistor MN1 in the middle) serves as the signal input terminal of the undervoltage detection circuit 12 and is electrically connected to the drain of the power tube; the drain of the first N-channel MOS transistor (i.e. Figure 2 The D port of the N-channel MOS transistor MN1 in the middle) serves as the signal output terminal of the undervoltage detection circuit 12 and is electrically connected to the second control terminal of the charge and discharge circuit 13; the gate of the first N-channel MOS transistor (i.e. Figure 3 The G port of the N-channel MOS transistor MN1 in the middle is connected to the second reference voltage (i.e. Figure 4 The second voltage threshold is obtained by subtracting the absolute value of the threshold voltage of the first N-channel MOS transistor (that is, the absolute value of the threshold voltage of the first N-channel MOS transistor) from the second reference voltage, wherein the second reference voltage can also be generated by various devices such as a bandgap reference voltage source and a Zener diode.

[0068] For the first N-channel MOS transistor, when the output voltage is less than the second voltage threshold, the first N-channel MOS transistor is turned on. At this time, the output current of the low-dropout linear regulator 20 is shunted through the first N-channel MOS transistor to the charge-discharge circuit 13. The shunted current signal represents the discharge drive signal and simultaneously reflects the magnitude of the output voltage. This allows the charge-discharge circuit 13 to adaptively adjust the gate discharge intensity of the power output transistor in accordance with the magnitude of the output voltage, thereby improving the recovery smoothness of the output voltage. As the charge-discharge circuit 13 performs the gate discharge operation on the power output transistor, the output current of the low-dropout linear regulator 20 gradually increases, and the output voltage also gradually increases. At this time, the on-resistance of the first N-channel MOS transistor gradually increases, and when the output voltage is greater than the first voltage threshold, the transistor is in a shut-off state, thereby preventing the undervoltage detection circuit 12 from generating additional static power consumption.

[0069] It is understandable that the first reference voltage and the second reference voltage may be the same or different from each other; the first reference voltage and the second reference voltage may be provided in the same or different manners.

[0070] Optionally, in this embodiment, to simplify the circuit layout of the transient enhancement circuit 10, the first reference voltage and the second reference voltage can be set to the same state and supplied through the same reference voltage supply scheme. In one implementation of this embodiment, the gates of the first P-channel MOS transistor and the first N-channel MOS transistor are interconnected and externally connected to the same reference power supply, which is used to provide the first reference voltage and the second reference voltage with the same value.

[0071] In another implementation of this embodiment, the first reference voltage and the second reference voltage can be obtained by converting the output voltage of the low-dropout linear regulator 20, without the need for additional reference power supply. Figure 4The first reference voltage and the second reference voltage can be obtained by converting the output voltage through an RC delay circuit. The RC delay circuit may include a resistor R3 and a capacitor C, wherein the end of the resistor R3 not connected to the capacitor C serves as the input end of the RC delay circuit and is electrically connected to the drain of the power output transistor to obtain the output voltage of the low-dropout linear regulator 20; the connection point between the resistor R3 and the capacitor C serves as the output end of the RC delay circuit and is electrically connected to the gates of the first P-channel MOS transistor and the first N-channel MOS transistor, respectively. The RC delay circuit delays the output voltage and provides it as the first reference voltage and the second reference voltage to the first P-channel MOS transistor and the first N-channel MOS transistor, respectively.

[0072] In the examples of this application, please refer to Figure 4 , Figure 4 This is one of the circuit composition diagrams of the charge-discharge circuit 13 provided in an embodiment of the present application. In this embodiment of the present application, when the charge-discharge circuit 13 performs a gate charging operation on the power output tube, to ensure that the gate charging intensity of the charge-discharge circuit 13 can be adaptively adjusted according to the output voltage of the low-dropout linear regulator 20, the charge-discharge circuit 13 can, through the coordinated action of an N-channel current mirror structure 131 and a P-channel current mirror structure 132, ensure that the charging current injected by the charge-discharge circuit 13 into the power output tube is positively correlated with the output voltage. The charging current is proportional to the voltage difference between the output voltage and the first voltage threshold; the greater the output voltage is above the first voltage threshold, the greater the charging current; and the closer the output voltage is to the first voltage threshold, the smaller the charging current.

[0073] In the embodiment of the present application, the reference current input terminal (ie Figure 5 The Iin port in the N-channel current mirror structure 131 is used as the first control terminal (i.e., the 1Con port) and is electrically connected to the signal output terminal of the overvoltage detection circuit 11; the mirror current output terminal of the N-channel current mirror structure 131 (i.e., the mirror current output terminal of the N-channel current mirror structure 131 Figure 5 The Iout port in the P-channel current mirror structure 132 is electrically connected to the reference current input terminal of the P-channel current mirror structure 132; the mirror current output terminal of the P-channel current mirror structure 132 serves as the charging and discharging terminal (i.e., the EO port) and is electrically connected to the gate of the power output tube.

[0074] Among them, when the N-channel current mirror structure 131 receives the input current through the reference current input terminal, it will perform current mirror conversion on the input current, and output an output current with the same current value as the input current through the mirror current output terminal; similarly, when the P-channel current mirror structure 132 receives the input current through the reference current input terminal, it will also perform current mirror conversion on the input current, and output an output current with the same current value as the input current through the mirror current output terminal.

[0075] Therefore, when the overvoltage detection circuit 11 is implemented using the first P-channel MOS transistor and the output voltage of the low-dropout linear regulator 20 exceeds the first voltage threshold, the first P-channel MOS transistor is turned on accordingly, and the output current of the low-dropout linear regulator 20 is diverted into a current signal. This current signal is transmitted to the N-channel current mirror structure 131 through the first P-channel MOS transistor. The N-channel current mirror structure 131 and the P-channel current mirror structure 132 cooperate to transpose a charging current having the same current value as the current signal. The P-channel current mirror structure 132 then injects the generated charging current into the gate of the power output tube to charge the gate of the power output tube. At this time, the on-resistance of the power output tube increases under the influence of the increased gate voltage, causing the output current of the low-voltage dropout linear regulator 20 to decrease. The output voltage of the low-voltage dropout linear regulator 20 decreases accordingly, causing the on-resistance of the first P-channel MOS tube to increase accordingly, causing the current flowing to the N-channel current mirror structure 131 to decrease accordingly. When the output voltage is less than the first voltage threshold, the current becomes 0, and the first P-channel MOS tube is also in the off state.

[0076] In an embodiment of the present application, when the charge-discharge circuit 13 performs a gate discharge operation on the power output tube, to ensure that the gate discharge intensity of the charge-discharge circuit 13 can be adaptively adjusted according to the output voltage of the low-dropout linear regulator 20, the charge-discharge circuit 13 can be directly connected to the second control terminal (i.e., the 2Con port) and the charge-discharge terminal when the undervoltage detection circuit 12 is implemented using an N-channel MOS transistor, so that the charge-discharge circuit 13 generates a pull-down current (i.e., a discharge current) corresponding to the gate voltage between the gate and drain of the power output tube. At this time, the magnitude of the discharge current is inversely correlated with the magnitude of the output voltage. The discharge current is proportional to the voltage difference between the second voltage threshold and the output voltage; the smaller the output voltage is below the second voltage threshold, the greater the discharge current; and the closer the output voltage is to the second voltage threshold, the smaller the discharge current.

[0077] When the undervoltage detection circuit 12 is implemented using a first N-channel MOS transistor, and the output voltage of the low-dropout linear regulator 20 is less than the second voltage threshold, the first N-channel MOS transistor is turned on accordingly. At this time, the gate and drain of the power output transistor are directly connected to each other through the first N-channel MOS transistor and the charge-discharge circuit 13, and a discharge current is generated from the gate of the power output transistor to the drain (i.e., the output port of the output voltage VOUT), thereby lowering the gate voltage of the power output transistor. At this time, the on-resistance of the power output transistor decreases under the influence of the reduced gate voltage, causing the output current of the low-dropout linear regulator 20 to increase. The output voltage of the low-dropout linear regulator 20 increases accordingly, causing the on-resistance of the first N-channel MOS transistor to increase accordingly, resulting in a corresponding decrease in the discharge current. The discharge current becomes zero when the output voltage is greater than the second voltage threshold, at which point the first N-channel MOS transistor is also in the off state.

[0078] Alternatively, see Figure 5 , Figure 5 This is the second circuit diagram of the charge and discharge circuit 13 provided in the embodiment of the present application. In the embodiment of the present application, the N-channel current mirror structure 131 may include a second N-channel MOS tube (ie Figure 5 The N-channel MOS tube MN21 in the middle) and the third N-channel MOS tube (ie Figure 5 The drain of the second N-channel MOS transistor (i.e., the D port) serves as the reference current input terminal of the N-channel current mirror structure 131, and the drain and gate (i.e., the G port) of the second N-channel MOS transistor are interconnected; the gate of the second N-channel MOS transistor is interconnected with the gate of the third N-channel MOS transistor, and the sources (i.e., the S ports) of the second N-channel MOS transistor and the third N-channel MOS transistor are both grounded; the drain of the third N-channel MOS transistor serves as the mirror current output terminal of the N-channel current mirror structure 131.

[0079] In the embodiment of the present application, the P-channel current mirror structure 132 may include a second P-channel MOS transistor (ie Figure 5 The P-channel MOS tube MP21 in the middle) and the third P-channel MOS tube (i.e. Figure 5 The drain of the second P-channel MOS transistor serves as the reference current input terminal of the P-channel current mirror structure 132, and the drain and gate of the second P-channel MOS transistor are connected to each other; the gate of the second P-channel MOS transistor is connected to the gate of the third P-channel MOS transistor, and the sources of the second P-channel MOS transistor and the third P-channel MOS transistor are connected to each other and connected to an external positive power supply voltage (i.e. Figure 5the drain of the third P-channel MOS transistor serves as the mirror current output terminal of the P-channel current mirror structure 132.

[0080] It is understandable that the specific implementation of the N-channel current mirror structure 131 is not limited to Figure 5 In the implementation scheme shown in FIG. 1 , the N-channel current mirror structure 131 may further include a Figure 6 This application does not limit the number of N-channel MOS tubes or other additional components.

[0081] Similarly, the specific implementation of the P-channel current mirror structure 132 is not limited to Figure 5 In the implementation scheme shown in FIG. 1 , the P-channel current mirror structure 132 may further include a Figure 6 More N-channel MOS transistors or other additional components are not limited in this application. The positive power supply voltage VCC involved in the P-channel current mirror structure 132 can be provided by an external power supply or by the input voltage of the low-dropout linear regulator 20. The specific method of providing the positive power supply voltage VCC is not limited in this application.

[0082] Alternatively, see Figure 6 In one implementation of this embodiment, in order to effectively reduce the total circuit layout area of ​​the low-dropout linear regulator 20 and the transient enhancement circuit 10, the charge-discharge circuit 13 in the transient enhancement circuit 10 can be implemented by reusing the same P-channel current mirror structure 132 as the error amplifier in the low-dropout linear regulator 20. In this case, the positive power supply voltage used by the charge-discharge circuit 13 at the P-channel current mirror structure 132 is the input voltage VIN at the voltage input terminal of the low-dropout linear regulator 20.

[0083] Schematically, the error amplifier includes Figure 7 The P-channel current mirror structure 132 shown in FIG. 1 may also include a current source and two N-channel MOS transistors (ie Figure 8 The N-channel MOS transistors MNA1 and MNA2 in the circuit are connected, wherein the gate of the N-channel MOS transistor MNA1 serves as the negative input terminal of the error amplifier, the drain of the N-channel MOS transistor MNA1 is connected to the mirror current output terminal of the P-channel current mirror structure 132, the gate of the N-channel MOS transistor MNA2 serves as the positive input terminal of the error amplifier, the drain of the N-channel MOS transistor MNA2 is connected to the reference current input terminal of the P-channel current mirror structure 132, the source of the N-channel MOS transistor MNA1, the source of the N-channel MOS transistor MNA2 and the negative electrode of the current source are connected to each other, the positive electrode of the current source is grounded, and the mirror current output terminal of the P-channel current mirror structure 132 can be used as the output terminal of the error amplifier.

[0084] Therefore, this application can be used ​ The circuit composition diagram shown effectively reduces the total circuit layout area of ​​the low-dropout linear regulator 20 and the transient enhancement circuit 10 .

[0085] Below ​ and ​ The voltage change waveform shown is used as a reference. In view of the rapid jitter phenomenon of the input voltage, the output voltage change of the same low-dropout linear regulator 20 before and after being connected to the transient enhancement circuit 10 is illustrated as follows:

[0086] When the input voltage of the low-dropout linear regulator 20 jumps from 5.2V to 40V in 4μs at a first time point (i.e., the time point of 50μs), if the low-dropout linear regulator 20 is not connected to the transient enhancement circuit 10, then due to the limited transient response capability of the error amplifier in the low-dropout linear regulator 20, the gate response of the power output tube often cannot keep up with the input voltage change, resulting in the output voltage rapidly increasing during the input voltage jump period and then being pulled down by the error amplifier. After increasing again, it is also pulled down by the error amplifier, thereby gradually recovering to the steady-state voltage value of 4.8V. If the low-dropout linear regulator 20 is connected to the transient enhancement circuit 10, then when the output voltage rapidly increases to exceed the first voltage threshold during the input voltage jump period, the charge-discharge circuit 13 generates a current to charge the gate of the power output tube, so that the output voltage is quickly limited to a state below the first voltage threshold and can be quickly recovered to the steady-state voltage value of 4.8V.

[0087] When the input voltage of the low-dropout linear regulator 20 begins to jump from 40V to 5.2V at the second time point (i.e., the time point of 553 μs), if the low-dropout linear regulator 20 is not connected to the transient enhancement circuit 10, then due to the limited transient response capability of the error amplifier in the low-dropout linear regulator 20, the gate response of the power output tube often cannot keep up with the input voltage change, resulting in the output voltage rapidly decreasing during the input voltage jump period before being raised by the error amplifier. Then, after decreasing again, it is raised by the error amplifier again, thereby gradually recovering to the steady-state voltage value of 4.8V. If the low-dropout linear regulator 20 is connected to the transient enhancement circuit 10, then when the output voltage rapidly decreases to less than the second voltage threshold during the input voltage jump period, the charge-discharge circuit 13 generates a current to discharge the gate of the power output tube, so that the output voltage is quickly limited to a state greater than the second voltage threshold and can quickly recover to the steady-state voltage value of 4.8V.

[0088] Therefore, the transient enhancement circuit 10 provided in the embodiment of the present application can cooperate with the negative feedback loop included in the low-voltage difference linear regulator 20 to quickly and adaptively achieve a timely output voltage transient response adjustment effect when the input voltage of the low-voltage difference linear regulator 20 has a serious overshoot or undershoot phenomenon, so that the corresponding output voltage can be effectively limited to the set threshold range (i.e., between the second voltage threshold and the first voltage threshold), achieving a good output voltage overshoot / undershoot suppression function, facilitating the corresponding output voltage to quickly recover to a stable state, and at the same time avoiding additional static power consumption.

[0089] The above are merely various embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A transient enhancement circuit for a low-dropout linear regulator, characterized in that: The transient enhancement circuit includes an overvoltage detection circuit, an undervoltage detection circuit and a charge and discharge circuit, wherein the drain of the power output tube included in the low voltage difference linear regulator serves as the voltage output end of the low voltage difference linear regulator; The signal input terminal of the overvoltage detection circuit is electrically connected to the drain of the power output tube, the signal output terminal of the overvoltage detection circuit is electrically connected to the first control terminal of the charge-discharge circuit, and the charge-discharge terminal of the charge-discharge circuit is electrically connected to the gate of the power output tube, wherein when the output voltage of the low-dropout linear regulator exceeds a first voltage threshold, the overvoltage detection circuit drives the charge-discharge circuit to charge the gate of the power output tube to lower the output voltage; The signal input terminal of the undervoltage detection circuit is electrically connected to the drain of the power output tube, and the signal output terminal of the undervoltage detection circuit is electrically connected to the second control terminal of the charge-discharge circuit. When the output voltage is less than a second voltage threshold, the undervoltage detection circuit drives the charge-discharge circuit to discharge the gate of the power output tube to increase the output voltage. The second voltage threshold is lower than the first voltage threshold.

2. The transient enhancement circuit according to claim 1, wherein: The overvoltage detection circuit includes a first P-channel MOS transistor; The source of the first P-channel MOS transistor serves as a signal input terminal of the overvoltage detection circuit and is electrically connected to the drain of the power output transistor; The drain of the first P-channel MOS transistor serves as a signal output terminal of the overvoltage detection circuit and is electrically connected to the first control terminal of the charge and discharge circuit; The gate of the first P-channel MOS transistor is connected to a first reference voltage, and the first voltage threshold is obtained by adding the first reference voltage to an absolute value of the threshold voltage of the first P-channel MOS transistor.

3. The transient enhancement circuit according to claim 2, characterized in that: The undervoltage detection circuit includes a first N-channel MOS transistor; The source of the first N-channel MOS transistor serves as the signal input terminal of the undervoltage detection circuit and is electrically connected to the drain of the power output transistor; The drain of the first N-channel MOS transistor serves as the signal output terminal of the undervoltage detection circuit and is electrically connected to the second control terminal of the charge and discharge circuit; The gate of the first N-channel MOS transistor is connected to a second reference voltage, and the second voltage threshold is obtained by subtracting an absolute value of the threshold voltage of the first N-channel MOS transistor from the second reference voltage.

4. The transient enhancement circuit according to claim 3, characterized in that: The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other and externally connected to the same reference power supply; wherein the reference power supply is used to provide the first reference voltage and the second reference voltage with the same value.

5. The transient enhancement circuit according to claim 3, characterized in that: The gates of the first P-channel MOS transistor and the first N-channel MOS transistor are connected to each other and electrically connected to the output end of the RC delay circuit; wherein the input end of the RC delay circuit is electrically connected to the drain of the power output transistor, and the RC delay circuit provides the first reference voltage and the second reference voltage of the same value based on the output voltage.

6. The transient enhancement circuit according to any one of claims 1 to 5, characterized in that: The charge and discharge circuit includes a P-channel current mirror structure and an N-channel current mirror structure; The reference current input terminal of the N-channel current mirror structure serves as the first control terminal and is electrically connected to the signal output terminal of the overvoltage detection circuit; The mirror current output terminal of the N-channel current mirror structure is electrically connected to the reference current input terminal of the P-channel current mirror structure; The mirror current output end of the P-channel current mirror structure serves as the charging and discharging end and is electrically connected to the gate of the power output tube.

7. The transient enhancement circuit according to claim 6, characterized in that: When the undervoltage detection circuit is implemented using an N-channel MOS transistor, the second control terminal and the charge and discharge terminal are directly connected inside the charge and discharge circuit.

8. The transient enhancement circuit according to claim 6, characterized in that: The N-channel current mirror structure includes a second N-channel MOS transistor and a third N-channel MOS transistor; The drain of the second N-channel MOS transistor serves as a reference current input terminal of the N-channel current mirror structure, and the drain and gate of the second N-channel MOS transistor are connected to each other; The gate of the second N-channel MOS transistor and the gate of the third N-channel MOS transistor are connected to each other, and the source of each of the second N-channel MOS transistor and the third N-channel MOS transistor is grounded; The drain of the third N-channel MOS transistor serves as the mirror current output end of the N-channel current mirror structure.

9. The transient enhancement circuit according to claim 6, characterized in that: The P-channel current mirror structure includes a second P-channel MOS transistor and a third P-channel MOS transistor; The drain of the second P-channel MOS transistor serves as a reference current input terminal of the P-channel current mirror structure, and the drain and gate of the second P-channel MOS transistor are connected to each other; The gate of the second P-channel MOS transistor and the gate of the third P-channel MOS transistor are connected to each other, and the sources of the second P-channel MOS transistor and the third P-channel MOS transistor are connected to each other and externally connected to a positive power supply voltage; The drain of the third P-channel MOS transistor serves as the mirror current output end of the P-channel current mirror structure.

10. The transient enhancement circuit according to claim 9, characterized in that: The error amplifier included in the low-voltage difference linear regulator and the charge and discharge circuit reuse the same P-channel current mirror structure, and the positive power supply voltage of the P-channel current mirror structure is the input voltage of the low-voltage difference linear regulator at the voltage input terminal.

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