Power supply interference suppression circuit

Abstract

The utility model relates to the field of electronic equipment power supply management, in particular to a power supply interference suppression circuit for consumer electronic equipment. In the prior art, the highly integrated PCB design often causes the problem of power supply interference and affects the equipment performance. The utility model provides a power supply interference suppression circuit which comprises an MOS tube and a reference voltage circuit, the drain electrode of the MOS tube is connected with an input voltage end, and the source electrode of the MOS tube is connected with an output voltage end; the reference voltage circuit is connected with the drain electrode, the grid electrode and the ground of the MOS tube. The circuit is located at the load end of the circuit, interference of input voltage is effectively restrained through cooperation of the working characteristics of the MOS tube and the reference voltage circuit, and stability of output voltage is kept. The structure is simple, is suitable for highly integrated circuits with limited space, reduces the requirements for PCB layout and wiring, improves the flexibility of circuit design, and effectively improves the performance and reliability of consumer electronic equipment at the same time.

Description

Technical Field

[0001] The utility model relates to the field of electronic equipment power management, in particular to a power supply interference suppression circuit for consumer electronic equipment. Background Art

[0002] With the rapid development of the consumer electronics market, the performance of various sensors continues to improve, placing higher demands on circuit design, PCB design, and power supply design. Power supply interference has become a pressing issue on highly integrated PCBs, especially in electronic devices with high power quality requirements, such as camera modules.

[0003] Currently, the commonly used power supply interference solutions in the industry mainly include reserving an RC filter circuit during the circuit design stage to filter out interference at the load end, reserving an external LDO (low-dropout linear regulator) as a backup power supply, and avoiding the power line from being close to the interference source during PCB layout and routing design.

[0004] However, these traditional methods have limitations in practical application. While simple, RC filtering circuits can be less than ideal in complex electromagnetic environments, especially for low-frequency interference. External LDOs, while effective, increase circuit complexity and cost, while also occupying valuable PCB space. In highly integrated modern electronic devices, PCB space is extremely limited, making it impractical to completely avoid routing power lines close to interference sources.

[0005] These issues often create technical challenges when designing high-performance, miniaturized consumer electronic devices: effectively suppressing power supply interference within limited PCB space. This is particularly true in applications such as camera modules, where power supply interference can cause image anomalies such as vertical and dark streaks, severely impacting product performance and user experience. Utility Model Content

[0006] The purpose of the utility model is to provide a power supply interference suppression circuit to solve the problem in the prior art that it is difficult to effectively suppress power supply interference on a highly integrated PCB.

[0007] To achieve the above objectives, the present invention provides a power supply interference suppression circuit, comprising a MOS transistor and a reference voltage circuit. The drain of the MOS transistor is connected to a voltage input terminal, and the source is connected to a voltage output terminal. The reference voltage circuit has a first terminal connected to the drain of the MOS transistor, a second terminal connected to the gate of the MOS transistor, and a third terminal connected to ground.

[0008] Furthermore, the MOS transistor is an N-type MOS transistor. Specifically, the N-type MOS transistor is a Q2601 N-type MOS transistor.

[0009] More specifically, the reference voltage circuit comprises a resistor and a zener diode connected in series; one end of the resistor is connected to the drain of the MOS tube, and the other end is connected to the gate of the MOS tube and the anode of the zener diode; the cathode of the zener diode is grounded.

[0010] Further, the resistor is a resistor of model R2601, and the zener diode is a zener diode of model D2601.

[0011] The power supply interference suppression circuit of the utility model further comprises a first capacitor and a second capacitor, which are both connected between the source of the MOS tube and the ground. Further, the first capacitor is a capacitor of model C2601, and the second capacitor is a capacitor of model C2602.

[0012] Specifically, the power supply interference suppression circuit is located at the circuit load end.

[0013] Compared with the prior art, the utility model has at least the following beneficial effects: the power supply interference suppression circuit provided by the utility model sets the MOS tube and the reference voltage circuit at the load end, utilizes the inherent characteristics of the MOS tube working in the amplification zone, can effectively suppress the interference of the input voltage, and thus maintains the stability of the output voltage. This simple structure design not only can be realized in the limited PCB space, but also can adapt to the requirements of highly integrated circuit design, effectively solves the problem of difficult suppression of power supply interference in small-sized devices in the prior art. At the same time, the design reduces the requirements for PCB layout and wiring, improves the flexibility and reliability of circuit design.

[0014] Further, the utility model further enhances the power supply interference suppression effect by using specific models of N-type MOS tube, resistor and zener diode, and adding parallel capacitors. This combination not only can effectively cope with positive interference, but also can suppress negative interference, and provide comprehensive power protection. At the same time, the circuit is arranged at the circuit load end of the consumer electronic device, and is particularly suitable for application scenarios with high requirements for power quality, such as camera modules, can effectively reduce image abnormal phenomena caused by power supply interference, such as vertical stripes, dark stripes, etc., thereby improving product performance and user experience. In addition, the design of the circuit is simple and easy to realize, which will not significantly increase the circuit complexity and cost, so that it has good application prospect and popularization value. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a structure schematic view of the power supply interference suppression circuit in an embodiment of the utility model;

[0016] Figure 2 It is a circuit diagram of the power supply interference suppression circuit in an embodiment of the utility model. DETAILED DESCRIPTION

[0017] The following detailed description of the specific embodiments of the present invention is provided in conjunction with the accompanying drawings. Preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art may modify the present invention described herein while still achieving the beneficial effects of the present invention. Therefore, the following description should be understood as a general guide for those skilled in the art and not as a limitation of the present invention.

[0018] The following paragraphs describe the present invention in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this specification are for illustrative purposes only. It should be noted that the drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0019] Unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as commonly understood by those skilled in the art to which this invention belongs.

[0020] like Figure 1 As shown, the present invention provides a power supply interference suppression circuit, which primarily includes a transistor VT (a MOS transistor in this embodiment) and a reference voltage circuit. A power supply input Vin is connected to the transistor VT and the reference voltage circuit, and the output of the transistor VT is connected to the power supply output Vout. The reference voltage circuit provides a control signal for the transistor VT. The power supply output Vout is connected to a load.

[0021] Figure 2 The circuit structure is further detailed. The drain (port 3) of the MOS transistor (Q2601) is connected to the input voltage terminal Vin, and the source (port 2) is connected to the output voltage terminal Vout. The reference voltage circuit is connected to the drain, gate (port 1), and ground (GND) of the MOS transistor.

[0022] In this embodiment, the MOS transistor is an N-type MOS transistor, model Q2601. The selection of the N-type MOS transistor is based on its voltage control characteristics in this circuit, and its ability to effectively respond to positive and negative interference.

[0023] The reference voltage circuit includes a resistor R2601 (Rv) and a Zener diode D2601 connected in series. One end of resistor R2601 is connected to the drain of MOS transistor Q2601, and the other end is connected to the gate of MOS transistor Q2601 and the anode of Zener diode D2601. The cathode of Zener diode D2601 is grounded. This connection ensures that the reference voltage circuit can provide a stable reference voltage for the MOS transistor.

[0024] The power supply interference suppression circuit of the present invention further includes two parallel capacitors C2601 and C2602, both connected between the source of the MOS transistor Q2601 and ground. The parallel connection of these two capacitors helps to further filter out high-frequency interference and improve the stability of the circuit.

[0025] The circuit is located at the load end of the circuit, specifically the load end of a consumer electronic device. This arrangement enables the circuit to suppress power supply interference directly at the load end, regardless of the distance from the main power supply and the routing of the power lines.

[0026] In actual applications, when the input voltage Vin is subject to positive interference, the source potential of MOS transistor Q2601 increases, causing the MOS transistor to shut down and block the interference. When the source potential drops to an appropriate level, the MOS transistor turns on again. This process repeats continuously, effectively suppressing positive interference. When the input voltage Vin is subject to negative interference, the gate-source voltage of the MOS transistor increases, increasing the MOS transistor's conduction level and thus stabilizing the output voltage Vout.

[0027] Specifically, the MOS transistor (Q2601) of the present invention has three working regions: a cut-off region, an amplification region, and a saturation region. The present invention mainly utilizes the working characteristics of the MOS transistor in the amplification region.

[0028] The reference voltage circuit is composed of resistor Rv (R2601) and Zener diode (D2601), and its output voltage satisfies the following relationship:

[0029] Vout=Vdz-Vgs

[0030] Wherein, Vdz represents the voltage of the Zener diode (D2601) to ground, and Vgs represents the voltage between the gate and source of the MOS tube, which is usually maintained at about 0.3V.

[0031] The working principle of the present invention can be further described as follows:

[0032] 1. Forward interference suppression mechanism:

[0033] When the input voltage Vin experiences positive interference, the potential at the source S of MOS transistor Q2601 rises, causing Vs to exceed Vg, causing the MOS transistor to shut down, thereby blocking the interference signal from the drain. Subsequently, when the potential at the gate S drops to a point where Vs is less than Vg and Vgs is greater than or equal to 0.3V, the MOS transistor turns back on. This cycle repeats, effectively suppressing power supply interference.

[0034] 2. Negative interference suppression mechanism:

[0035] When the input voltage Vin suffers negative interference, the potential of the gate S decreases because Vdz remains unchanged. According to Kirchhoff's voltage law, Vgs increases accordingly, which makes the MOS tube conduct more, and the current through the MOS tube increases accordingly. According to Ohm's law U = IR, under the condition that the impedance remains unchanged, the increase of the current ensures the stability of the output voltage Vout.

[0036] The design of the utility model not only realizes the effective suppression of power interference, but also reduces the requirements for PCB component arrangement and circuit design. Since the power interference suppression circuit is arranged at the load end, its performance is not affected by the distance of the main power supply and the power line layout, which improves the flexibility of the circuit board design and ensures high-quality power supply at the load end.

[0037] The use of specific models of N-type MOS tubes, resistors and voltage stabilizing diodes, and the addition of parallel capacitors, further enhances the power interference suppression effect. Arranging the circuit at the circuit load end of a consumer electronic device, especially for applications that require high-quality power supply, such as camera modules, can effectively reduce image abnormalities caused by power interference and improve product performance. In addition, the circuit structure is simple and easy to implement, which will not significantly increase the complexity and cost of the circuit.

[0038] It should be understood that the above specific embodiments of the utility model are only used for illustrative or explanatory purposes, and do not constitute a limitation on the utility model. Therefore, any modification, equivalent replacement, improvement, etc. made without deviating from the spirit and scope of the utility model shall be included within the protection scope of the utility model. In addition, the claims of the utility model are intended to cover all changes and modifications falling within the scope and boundaries of the appended claims, or the equivalent forms of such scope and boundaries.

Claims

1. A power supply interference suppression circuit, characterized in that: include: MOS tube, its drain is connected to the voltage input terminal, and its source is connected to the voltage output terminal; a reference voltage circuit, wherein a first end of the reference voltage circuit is connected to the drain of the MOS transistor, a second end of the reference voltage circuit is connected to the gate of the MOS transistor, and a third end of the reference voltage circuit is grounded; The reference voltage circuit includes a resistor and a zener diode connected in series; one end of the resistor is connected to the drain of the MOS tube, and the other end is connected to the gate of the MOS tube and the anode of the zener diode; the cathode of the zener diode is grounded.

2. The power supply interference suppression circuit according to claim 1, wherein: The MOS tube is an N-type MOS tube.

3. The power supply interference suppression circuit according to claim 2, wherein: The N-type MOS tube is a Q2601 N-type MOS tube.

4. The power supply interference suppression circuit according to claim 1, wherein: The resistor is a model R2601 resistor.

5. The power supply interference suppression circuit according to claim 1 or 4, characterized in that: The voltage-stabilizing diode is a voltage-stabilizing diode of model D2601.

6. The power supply interference suppression circuit according to claim 1, wherein: Also includes: The first capacitor and the second capacitor are both connected between the source of the MOS tube and the ground.

7. The power supply interference suppression circuit according to claim 6, wherein: The first capacitor is a capacitor of model C2601, and the second capacitor is a capacitor of model C2602.

8. The power supply interference suppression circuit according to claim 1, wherein: The power supply interference suppression circuit is located at the load end of the circuit.

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