Underwater sound front-end signal acquisition module based on domestic ADC chip

Abstract

The utility model relates to an underwater sound front-end signal acquisition module based on a domestic ADC (Analog to Digital Converter) chip, which obtains a signal frequency required by equipment in the underwater sound field after conditioning, and comprises a single-ended to differential driving unit and an ADC, the input end of the single-ended to differential driving unit is used for receiving an underwater sound weak signal amplified and filtered by a pre-stage circuit, and then filtering and outputting the signal after de-noising operational amplification; in addition, after the ADC receives the driven differential signal and performs analog-to-digital conversion, the differential signal is uploaded to the main control chip through a pin 10 and a pin 11 of the ADC to realize signal acquisition. The underwater sound front-end signal acquisition module is not limited by too high or too low sampling frequency so as not to influence the performance of equipment, the underwater sound front-end signal acquisition module adopts a domestic chip, and meanwhile, the performance requirement is improved.

Description

Technical Field

[0001] The utility model relates to the field of development and design of hardware chips, in particular to an underwater acoustic front-end signal acquisition module based on a domestic ADC chip. Background Art

[0002] Currently, in the domestic underwater acoustics field, ADC chips are widely used in front-end signal acquisition modules. Although there are many domestically produced ADC chips, they are currently mainly used in radar equipment. Due to their high sampling frequency, they are not fully suitable for the signal frequencies of underwater acoustics. Meanwhile, the civilian field, where ADC chips are widely used, generally operates at lower frequencies. As a result, not many domestic chip manufacturers are developing medium-frequency ADC chips, resulting in a relatively low selection of such domestic chips. In the past two years, due to the increasing demand for equipment performance, the requirements for front-end signal acquisition in the underwater acoustic field have also been increasing. Currently, the JAD7961 ADC chip produced by the 58th Institute of China Electronics Technology Group Corporation can meet these design requirements.

[0003] Therefore, there is an urgent need for a design solution and module based on JAD7961 to meet the working requirements of current underwater acoustic equipment. Utility Model Content

[0004] To solve the above technical problems, the utility model provides an underwater acoustic front-end signal acquisition module based on a domestic ADC chip. After conditioning, the signal acquisition module obtains the signal frequency required by underwater acoustic field equipment, including a single-ended to differential drive unit and an ADC;

[0005] The input end of the single-ended to differential driving unit receives the weak underwater sound signal after amplification and filtering by the pre-stage circuit, and then passes through the noise-removing operational amplifier and then filters the signal for output;

[0006] In addition, after the ADC receives the differential signal after driving, it performs analog-to-digital conversion and uploads it to the main control chip through the 10th and 11th pins of the ADC itself to realize signal collection;

[0007] The single-ended to differential drive unit is powered by 5V and 1.8V, and includes a coupling capacitor C34 for coupling the front-stage and post-stage circuits to prevent DC level interference. After receiving the weak underwater sound signal, the coupling capacitor C34 is connected to the negative input terminal of the ASTW8138 op amp chip after passing through the resistor R31. The positive output pin of the ASTW8138 is connected to the IN+ pin of the ADC through the low-pass filter composed of R38 and C38. At the same time, the negative output pin of the ASTW8138 is connected to the IN- pin of the ADC through the low-pass filter composed of R40 and C42.

[0008] In one embodiment of the present invention, the ASTW8138 op amp chip in the single-ended to differential drive unit and the pin ends of the ADC are provided with several filter capacitors, wherein the VDD2 power supply end of the ADC is provided with filter capacitors C22, C24, and C27, and the three groups of filter capacitors are connected in parallel, and the other end thereof is connected to the information ground of SGND, the VIO configuration end of the ADC is connected to the filter capacitor C28, and the VDD1 power supply end of the ADC is provided with C29, C30, and C31, the REF end of the ADC is connected to the filter capacitors C35 and C36, and the VCM end of the ADC is connected to the filter capacitor C40.

[0009] In one embodiment of the present invention, the positive power supply pin of the ASTW8138 operational amplifier chip is connected to a filter capacitor C32 , and the pin for setting the common-mode output voltage is connected to a filter capacitor C41 .

[0010] In one embodiment of the present invention, the positive power pin of the ASTW8138 op amp chip is connected to R27, and the VDD2, VDD1, REF, and VCM terminals of the ADC are also connected to R23, R28, R33, and R39, respectively, for protecting the circuit and filtering out power supply noise.

[0011] In one embodiment of the present invention, a pre-stage matching resistor R36 is provided between the coupling capacitor C34 and the resistor R31 for adjusting the amplitude of the input signal.

[0012] In one embodiment of the present invention, R25 is connected in parallel between the negative input pin and the positive output pin of the ASTW8138 op amp chip, R31 is provided on one side of the negative input pin, R41 is provided between the positive input pin and the SGND information ground, and R44 is connected in parallel between the positive input pin and the negative output pin, which are used to realize matching resistors for converting single-ended signals to differential signals.

[0013] In one embodiment of the present invention, R32 is connected in parallel between the REFIN pin and the EN2 enable terminal of the ADC, wherein the EN0 enable terminal is connected to R35 and the EN2 enable terminal is connected to R37, for realizing the reference voltage mode selection of the JAD7961 chip.

[0014] In one embodiment of the present invention, the DCO+ terminal of the ADC is connected to R42 for selecting a self-clocked interface mode.

[0015] In one embodiment of the present invention, an impedance matching resistor R43 is provided between the clock inputs CLK+ and CLK- of the ADC to prevent signal reflection and other effects caused by impedance mismatch.

[0016] The above technical solution of the present invention has the following advantages over the existing technology: the underwater acoustic front-end signal acquisition module described in the present invention is no longer limited by the problem of too high or too low sampling frequency affecting the performance of the equipment, and the signal acquisition function of the conditioned signal is realized in the underwater acoustic front-end signal acquisition module, so that the underwater acoustic front-end signal acquisition module adopts domestic chips and improves performance requirements at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0018] Figure 1 This is a circuit diagram of the underwater acoustic front-end signal acquisition module of the utility model;

[0019] Figure 2 It is a waveform diagram of the software in which the upper-level main control chip in the utility model collects the results through FPGA. DETAILED DESCRIPTION

[0020] like Figure 1 As shown, this embodiment provides an underwater acoustic front-end signal acquisition module based on a domestic ADC chip. After conditioning, the signal acquisition module obtains a signal frequency suitable for underwater acoustic field equipment, including a single-ended to differential drive unit and an ADC;

[0021] The input end of the single-ended to differential driving unit receives the weak underwater sound signal after amplification and filtering by the pre-stage circuit, and then passes through the noise-removing operational amplifier and then filters the signal for output;

[0022] In addition, after the ADC receives the differential signal after driving, it performs analog-to-digital conversion and uploads it to the main control chip through the 10th and 11th pins of the ADC itself to realize signal collection;

[0023] The single-ended to differential drive unit is powered by 5V and 1.8V, and includes a coupling capacitor C34 for coupling the front-stage and post-stage circuits to prevent DC level interference. After receiving the weak underwater sound signal, the coupling capacitor C34 is connected to the negative input terminal of the ASTW8138 op amp chip after passing through the resistor R31. The positive output pin of the ASTW8138 is connected to the IN+ pin of the ADC through the low-pass filter composed of R38 and C38. At the same time, the negative output pin of the ASTW8138 is connected to the IN- pin of the ADC through the low-pass filter composed of R40 and C42.

[0024] The ADC used is JAD7961, and its main features are as follows:

[0025] Throughput rate: 5MSPS

[0026] 16-bit resolution, no missing codes

[0027] Excellent AC / DC performance

[0028] Dynamic range: 96dB

[0029] Signal-to-noise ratio: 95.5dB

[0030] True differential analog input voltage range: ±4.096V or ±5V

[0031] Low power: 46.5mW (5MSPS, external reference voltage buffer, echo clock mode)

[0032] 64.5mW (5MSPS, internal reference voltage buffer, echo clock mode)

[0033] 39mW (5MSPS, external reference voltage buffer, self clock mode, CNV± is CMOS mode)

[0034] Further, the module circuit of the embodiment mainly realizes the single-ended to differential conversion and differential signal acquisition function of the front-stage conditioned signal. The circuit adopts 5V and 1.8V power supply, the front-stage circuit amplifies and filters the weak underwater acoustic signal, and then sends the analog single-ended signal of 0 to 5V to the left side of the input capacitor C34 of the circuit. The circuit converts the single-ended signal to a differential signal and simultaneously drives the signal, and then sends the driven differential signal to the ADC chip. Finally, the digital signal converted by the ADC chip is uploaded to the main control chip through the 10th and 11th pins of the chip to realize signal acquisition.

[0035] Specifically, the ASTW8138 operational amplifier chip in the single-ended to differential conversion and driving unit and the pin end of the ADC are each provided with a plurality of filter capacitors. The VDD2 power supply end of the ADC is provided with filter capacitors C22, C24 and C27, and the other ends of the three groups of filter capacitors are connected to the information ground of SGND. The VIO configuration end of the ADC is connected to a filter capacitor C28. The VDD1 power supply end of the ADC is provided with C29, C30 and C31. The REF end of the ADC is connected to filter capacitors C35 and C36. The VCM end of the ADC is connected to a filter capacitor C40.

[0036] Specifically, the positive power supply pin of the ASTW8138 operational amplifier chip is connected to a filter capacitor C32, and the pin for setting the common-mode output voltage is connected to a filter capacitor C41.

[0037] Specifically, the positive power supply pin of the ASTW8138 operational amplifier chip is connected to R27, and the VDD2, VDD1, REF end and VCM end of the ADC are further respectively connected to R23, R28, R33 and R39 for protecting the circuit and filtering power supply noise and the like.

[0038] Specifically, a pre-stage matching resistor R36 is provided between the coupling capacitor C34 and the resistor R31 for adjusting the amplitude of the input signal.

[0039] Specifically, R25 is connected in parallel between the negative input pin and the positive output pin of the ASTW8138 op amp chip, R31 is provided on one side of the negative input pin, R41 is provided between the positive input pin and the SGND information ground, and R44 is connected in parallel between the positive input pin and the negative output pin, which are used to realize matching resistors for converting single-ended signals to differential signals.

[0040] Specifically, R32 is connected in parallel between the REFIN pin and the EN2 enable terminal of the ADC, wherein the EN0 enable terminal is connected to R35 and the EN2 enable terminal is connected to R37, for realizing the reference voltage mode selection of the JAD7961 chip.

[0041] Specifically, the DCO+ terminal of the ADC is connected to R42 for selecting the self-clock interface mode.

[0042] Specifically, an impedance matching resistor R43 is provided between the clock inputs CLK+ and CLK- of the ADC to prevent influences such as signal reflection caused by impedance mismatch.

[0043] like Figure 2 As shown, after the underwater acoustic front-end signal acquisition module described in this embodiment is working, the upper main control chip transmits the collected underwater acoustic information to the FPGA for acquisition, processing and analysis, and obtains high-precision signals, indicating good working stability, meeting the high-performance requirements of the underwater acoustic equipment, and improving the response efficiency and accuracy of the equipment.

[0044] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. An underwater acoustic front-end signal acquisition module based on a domestic ADC chip. After conditioning, the signal acquisition module obtains a signal frequency suitable for underwater acoustic field equipment, characterized in that: Including single-ended to differential drive unit and ADC; The input end of the single-ended to differential driving unit receives the weak underwater sound signal after amplification and filtering by the pre-stage circuit, and then passes through the noise-removing operational amplifier and then filters the signal for output; In addition, after the ADC receives the differential signal after driving, it performs analog-to-digital conversion and uploads it to the main control chip through the 10th and 11th pins of the ADC itself to realize signal collection; The single-ended to differential drive unit is powered by 5V and 1.8V, and includes a coupling capacitor C34. After receiving the weak underwater sound signal, the coupling capacitor C34 is connected to the negative input terminal of the ASTW8138 op amp chip after passing through the resistor R31. The positive output pin of the ASTW8138 is connected to the IN+ pin of the ADC through a low-pass filter composed of R38 and C38. At the same time, the negative output pin of the ASTW8138 is connected to the IN- pin of the ADC through a low-pass filter composed of R40 and C42.

2. The underwater acoustic front-end signal acquisition module according to claim 1, characterized in that: The ASTW8138 op amp chip in the single-ended to differential drive unit and the ADC pin ends are equipped with several filter capacitors. The VDD2 power supply end of the ADC is equipped with filter capacitors C22, C24, and C27, the VIO configuration end of the ADC is connected to the filter capacitor C28, and the VDD1 power supply end of the ADC is equipped with C29, C30, and C31. The REF end of the ADC is connected to the filter capacitors C35 and C36, and the VCM end of the ADC is connected to the filter capacitor C40.

3. The underwater acoustic front-end signal acquisition module according to claim 2, characterized in that: At the same time, the positive power supply pin of the ASTW8138 op amp chip is connected to a filter capacitor C32, and the pin for setting the common-mode output voltage is connected to a filter capacitor C41.

4. The underwater acoustic front-end signal acquisition module according to claim 1, characterized in that: The positive power supply pin of the ASTW8138 op amp chip is connected to R27, and the VDD2, VDD1, REF, and VCM terminals of the ADC are also connected to R23, R28, R33, and R39 respectively.

5. The underwater acoustic front-end signal acquisition module according to claim 1, characterized in that: A pre-stage matching resistor R36 is provided between the coupling capacitor C34 and the resistor R31.

6. The underwater acoustic front-end signal acquisition module according to claim 1, characterized in that: R25 is connected in parallel between the negative input pin and the positive output pin of the ASTW8138 op amp chip, R31 is provided on one side of the negative input pin, R41 is provided between the positive input pin and the SGND information ground, and R44 is connected in parallel between the positive input pin and the negative output pin.

7. The underwater acoustic front-end signal acquisition module according to claim 1, characterized in that: R32 is connected in parallel between the REFIN pin and the EN2 enable terminal of the ADC, wherein the EN0 enable terminal is connected to R35, and the EN2 enable terminal is connected to R37.

8. The underwater acoustic front-end signal acquisition module according to claim 1, characterized in that: The DCO+ terminal of the ADC is connected to R42.

9. The underwater acoustic front-end signal acquisition module according to claim 1, characterized in that: An impedance matching resistor R43 is provided between the clock inputs CLK+ and CLK- of the ADC.

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