Semiconductor device

Abstract

A semiconductor device includes a first transistor, a second transistor over the first transistor, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer, and a first source / drain epitaxial structure on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer, and a second source / drain epitaxial structure on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, where the isolation structure is adjacent to the second gate structure in a top view, and where the isolation structure surrounds the first semiconductor channel layer in a first cross-sectional view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced successive generations of integrated circuits. Each generation features smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing ICs. Over the course of IC development, functional density (i.e., the number of interconnected devices per wafer area) has generally increased, while geometry size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This process of scaling down generally provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform. Consequently, forming reliable semiconductor devices at increasingly smaller sizes has become a challenge. Utility Model Content

[0003] In some embodiments disclosed herein, a semiconductor device includes a first transistor, a second transistor vertically positioned above the first transistor, and an isolation structure. The first transistor is above a substrate. The first transistor includes a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer, and first source / drain epitaxial structures on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer, and second source / drain epitaxial structures on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view, the isolation structure is adjacent to the second gate structure, and wherein in a first cross-sectional view, the isolation structure surrounds the first semiconductor channel layer.

[0004] In some embodiments disclosed herein, a semiconductor device includes a first transistor, a second transistor vertically positioned above the first transistor, and a bottom gate contact. The first transistor is positioned above a substrate. The first transistor includes a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer, and first source / drain epitaxial structures on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer, and second source / drain epitaxial structures on opposite ends of the second semiconductor channel layer. The bottom gate contact contacts the first gate structure and is spaced apart from the second gate structure, wherein a top surface of the bottom gate contact is higher than a top surface of the first semiconductor channel layer, and a bottom surface of the bottom gate structure is lower than a bottom surface of the first semiconductor channel layer.

[0005] In some embodiments disclosed herein, a semiconductor device includes a first transistor, a second transistor above the first transistor, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer, and a first source / drain epitaxial structure on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer, and a second source / drain epitaxial structure on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view, the isolation structure is adjacent to the second gate structure, wherein in a first cross-sectional view, the isolation structure surrounds the first semiconductor channel layer, wherein the isolation structure has a portion vertically located between the first semiconductor channel layer and the substrate, and wherein in a second cross-sectional view perpendicular to the first cross-sectional view, the first gate structure surrounds the portion of the isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a perspective view of a semiconductor device according to some embodiments of the present disclosure;

[0008] Figures 1B to 1D is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0009] Figures 2A to 31D Methods are illustrated at various stages in forming a semiconductor device according to some embodiments of the present disclosure.

[0010]

Explanation of symbols

[0011] 10: CFET

[0012] 11:Substrate

[0013] 12: First semiconductor channel layer

[0014] 14: Second semiconductor channel layer

[0015] 22: First metal gate structure

[0016] 24: Second metal gate structure

[0017] 32: First source / drain epitaxial structure

[0018] 34: Second source / drain epitaxial structure

[0019] 41: Gate dielectric layer

[0020] 42: Gate electrode

[0021] 42A, 42B, 42C: Part

[0022] 51: Gate dielectric layer

[0023] 52: Gate electrode

[0024] 60: Isolation Structure

[0025] 60A, 60B, 60C: Part

[0026] 62: Bottom gate contact

[0027] 64: Bottom source / drain contact

[0028] 70: Isolation Structure

[0029] 100:Substrate

[0030] 100P:Semiconductor strip

[0031] 101: First sacrificial layer

[0032] 102: first semiconductor layer

[0033] 103: Second sacrificial layer

[0034] 104: Second semiconductor layer

[0035] 106: Isolation Structure

[0036] 112: dummy gate structure

[0037] 114: Virtual gate hard mask

[0038] 115: Gate spacer

[0039] 116: spacer

[0040] 117: Internal spacer

[0041] 120: first source / drain epitaxial structure

[0042] 125: conductive layer

[0043] 128: Isolation Structure

[0044] 129: Internal spacer

[0045] 130: Second source / drain epitaxial structure

[0046] 132: Isolation Structure

[0047] 140: Gate dielectric layer

[0048] 142: Gate electrode

[0049] 142A, 142B, 142C: Part

[0050] 145: Isolation Structure

[0051] 145A, 145B, 145C: Part

[0052] 150: Gate dielectric layer

[0053] 152: Gate electrode

[0054] 160: conductive layer

[0055] 172: first metal gate structure

[0056] 174: Second metal gate structure

[0057] 182: Bottom source / drain contact

[0058] 190: bottom gate contact

[0059] MA1, MA2, MA3: Patterned masks

[0060] O1: Opening

[0061] R1: sidewall groove

[0062] GT1: Gate Trench

[0063] TR1: first transistor

[0064] TR2: Second transistor

[0065] BB:Line

[0066] CC:Line

[0067] DD:Line

[0068] B'-B': line

[0069] C'-C': line

[0070] D'-D': line DETAILED DESCRIPTION

[0071] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate the relationship between the various embodiments and / or configurations discussed.

[0072] In addition, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly. As used herein, "approximately," "about," "substantially," or "substantially" may generally mean within 20%, within 10%, or within 5% of a given value or range. The values ​​given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "substantially," or "substantially" can be inferred. However, those skilled in the art will recognize that the values ​​or ranges throughout the specification are merely examples and may decrease or change as the scale of integrated circuits decreases.

[0073] A gate all around (GAA) transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, double patterning or multiple patterning processes combine photolithography with a self-aligned process, thereby allowing the production of patterns with a smaller pitch than can be obtained using a single direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0074] Figure 1A is a perspective view of a semiconductor device according to some embodiments of the present disclosure. Figures 1B to 1D is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. In more detail, Figure 1B , Figure 1C , and Figure 1D are cross-sectional views along lines B'-B', C'-C', and D'-D' of Figure 1A .

[0075] In this disclosure, a complementary field effect transistor (CFET) 10 is provided, and a method of fabricating the same will be disclosed in the following discussion. In the CFET 10, a first transistor TR1 is disposed above a substrate 11, and a second transistor TR2 is disposed vertically above the first transistor TR1 (see Figure 1B ). In some embodiments, the first transistor TR1 and the second transistor TR2 can be field effect transistors (FETs), and both can include a gate all around (GAA) configuration, so the first transistor TR1 and the second transistor TR2 can also be referred to as GAA FETs. The first transistor TR1 includes a first semiconductor channel layer 12, a first metal gate structure 22 surrounding the first semiconductor channel layer 12, and first source / drain epitaxial structures 32 on opposite ends of the first semiconductor channel layer 12. Similarly, the second transistor TR2 includes a second semiconductor channel layer 14, a second metal gate structure 24 surrounding the second semiconductor channel layer 14, and second source / drain epitaxial structures 34 on opposite ends of the second semiconductor channel layer 14. The first metal gate structure 22 can include a gate dielectric layer 41 and a gate electrode 42. Similarly, the second metal gate structure 24 can include a gate dielectric layer 51 and a gate electrode 52. In some embodiments, the first transistor TR1 has a first conductivity type (e.g., p-type), and the second transistor TR2 has a second conductivity type (e.g., n-type) different from the first conductivity type. In some embodiments, the first transistor TR1 can be referred to as a P-FET, and the second transistor TR2 can be referred to as an N-FET. In other embodiments, the first transistor TR1 has the second conductivity type (e.g., n-type), and the second transistor TR2 has the first conductivity type (e.g., p-type). In some embodiments, the first transistor TR1 can be referred to as an N-FET, and the second transistor TR2 can be referred to as a P-FET.

[0076] As shown in Figure 1A , Figure 1B , and Figure 1C , the CFET 10 further includes an isolation structure 60 electrically isolating the first metal gate structure 22 from the second metal gate structure 24. As shown in the cross-sectional view of Figure 1C , the isolation structure 60 has a portion 60A vertically between the gate electrode 42 of the first metal gate structure 22 and the gate electrode 52 of the second metal gate structure 24. In some embodiments, the isolation structure 60 can be a dielectric material, such as silicon dioxide, silicon nitride, or other dielectric material. In some embodiments, the isolation structure 60 can be a conductive material, such as a metal or a metal alloy. In some embodiments, the isolation structure 60 can be a semiconductor material, such as a semiconductor alloy. In some embodiments, the isolation structure 60 can be a combination of two or more of the above-mentioned materials. Figure 1C In the cross-sectional view of FIG, the isolation structure 60 also surrounds the first semiconductor channel layer 12. Figure 1B and Figure 1C As shown, the isolation structure 60 also includes a portion 60B vertically located between the first semiconductor channel layer 12 and the substrate 11. Figure 1C As shown, the isolation structure 60 also includes a portion 60C that contacts the sidewalls of the first metal gate structure 22 and the second metal gate structure 24 .

[0077] like Figure 1A 、 Figure 1B ,and Figure 1C As shown, the CFET 10 further includes a bottom gate contact 62 electrically connected to the first metal gate structure 22 at a lower level of the CFET 10. Here, the term "bottom gate contact" may refer to a gate contact that contacts a gate structure at a lower level (e.g., the first metal gate structure 22). In some embodiments, the bottom gate contact 62 may contact a portion of the gate electrode 42 of the first metal gate structure 22. In more detail, as shown in FIG. Figure 1B As shown, the gate electrode 42 of the first metal gate structure 22 may surround a portion 60B of the isolation structure 60. For example, in Figure 1B In the embodiment of the present invention, gate electrode 42 of first metal gate structure 22 may include a portion 42A in contact with the top surface of portion 60B of isolation structure 60, a portion 42B in contact with the bottom surface of portion 60B of isolation structure 60, and two portions 42C connecting portions 42A and 42B. In other words, portions 42A, 42B, and 42C may form a rectangular ring structure surrounding portion 60B of isolation structure 60. Similarly, gate dielectric layer 41 also includes a rectangular ring structure surrounding portion 60B of isolation structure 60. In other words, first metal gate structure 22 also surrounds portion 60B of isolation structure 60.

[0078] On the other hand, Figure 1C As shown, portion 42B of gate electrode 42 may extend to the bottom surface of bottom gate contact 62. More specifically, portion 42B of gate electrode 42 contacts and is electrically connected to the bottom surface of bottom gate contact 62. As a result, portions 42A and 42C of gate electrode 42 may also be electrically connected to bottom gate contact 62. In some embodiments, gate dielectric layer 41 includes a portion perpendicularly located between portion 42B of gate electrode 42 and substrate 11. Furthermore, a portion of gate dielectric layer 41 also extends to a position perpendicularly located between the bottom surface of bottom gate contact 62 and substrate 11.

[0079] like Figure 1A 、 Figure 1B ,and Figure 1DAs shown, CFET 10 further includes bottom source / drain contacts 64 that contact and are electrically connected to the respective first source / drain epitaxial structures 32. Herein, the term "bottom source / drain contacts" may refer to source / drain contacts that contact a source / drain epitaxial structure at a lower level (e.g., the first source / drain epitaxial structure 32). CFET 10 further includes isolation structures 70, wherein each of the isolation structures 70 is vertically positioned between one of the first source / drain epitaxial structures 32 and a respective one of the second source / drain epitaxial structures 34. Thus, the first source / drain epitaxial structure 32 is electrically isolated from the respective second source / drain epitaxial structure 34 via the isolation structures 70.

[0080] like Figure 1D As shown, the bottom source / drain contact 64 contacts the sidewalls of the first source / drain epitaxial structure 32, while the top surface of the first source / drain epitaxial structure 32 is covered by the isolation structure 70. The bottom source / drain contact 64 is spaced apart from the second source / drain epitaxial structure 34. In some embodiments, the bottom source / drain contact 64 may include an L-shaped cross-sectional view.

[0081] Figures 2A to 31D The method of forming a semiconductor device according to some embodiments of the present disclosure at various stages is shown. Figures 2A to 31D The diagram shows a method for forming a Figures 1A to 1D The CFET 10 is a CFET method. Although Figures 2A to 31D Described as a series of actions, it should be understood that these actions are not restrictive, because in other embodiments, the order of actions can be changed, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions shown and / or described can be omitted in whole or in part.

[0082] refer to Figure 2A and Figure 2B ,in Figure 2A is a top view of a semiconductor device, Figure 2B To follow Figure 2A AA cross-sectional view. A substrate 100 is shown. Generally speaking, the substrate 100 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer below a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally include a crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium; a silicon-germanium alloy; a compound semiconductor (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or an alloy thereof (e.g., GaN, AlN, and the like). x Al 1-x As、Ga x Al1-x N、In x Ga 1-x As, and the like); oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, and the like), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0083] A stack ST1 of a first sacrificial layer 101 and a first semiconductor layer 102 is formed over a substrate 100. Next, a stack ST2 of a second sacrificial layer 103 and a second semiconductor layer 104 is formed over the stack ST1. Specifically, the first semiconductor layer 102 is sandwiched between the first sacrificial layers 101, and the second semiconductor layer 104 is sandwiched between the second sacrificial layers 103. In some embodiments, the topmost first sacrificial layer 101 is in contact with the bottommost second sacrificial layer 103. In some embodiments, the first sacrificial layer 101, the first semiconductor layer 102, the second sacrificial layer 103, and the second semiconductor layer 104 can be formed using a suitable deposition process, such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable processes. In some embodiments, the first sacrificial layer 101 and the second sacrificial layer 103 may comprise semiconductor materials and may also be referred to as semiconductor layers. In some embodiments, the first semiconductor layer 102 and the second semiconductor layer 104 may each serve as a channel layer of a transistor and may also be referred to as a semiconductor channel layer.

[0084] In some embodiments, the first semiconductor layer 102 and the second semiconductor layer 104 may include silicon germanium (SiGe). 0.25 Ge 0.75 The first sacrificial layer 101 and the second sacrificial layer 103 may include germanium (Ge). In some embodiments, the first sacrificial layer 101 and the second sacrificial layer 103 may be doped with different impurities to provide sufficient etching resistance. For example, the first sacrificial layer 101 may be germanium doped with phosphorus (Ge:P), and the second sacrificial layer 103 may be germanium doped with boron (Ge:B).

[0085] In other embodiments, the first semiconductor layer 102 and the second semiconductor layer 104 may include silicon (Si). The first sacrificial layer 101 and the second sacrificial layer 103 may include silicon germanium (SiGe). In some embodiments, the first sacrificial layer 101 and the second sacrificial layer 103 may be silicon germanium, but with different germanium concentrations.

[0086] Although one first semiconductor layer 102 and one second semiconductor layer 104 are shown, multiple first semiconductor layers 102 and multiple second semiconductor layers 104 may be applied. For example, the stack ST1 may include alternating first sacrificial layers 101 and first semiconductor layers 102. Similarly, the stack ST2 may include alternating second sacrificial layers 103 and second semiconductor layers 104.

[0087] refer to Figure 3A and Figure 3B ,in Figure 3A is a top view of a semiconductor device, Figure 3B To follow Figure 3A BB. A patterned mask MA1 is formed over the substrate 100 and covering the stack ST2. In some embodiments, the patterned mask MA1 may be a hard mask and may include a dielectric material such as silicon nitride (SiN), silicon dioxide (SiO2), a combination thereof, or the like.

[0088] Then, an etching process is performed using the patterned mask MA1 as an etching mask to remove portions of the stacks ST1 and ST2 and portions of the substrate 100 exposed by the patterned mask MA1, thereby forming a fin structure. The fin structure may include the remaining portions of the stacks ST1 and ST2 and the semiconductor strips 100P protruding above the substrate 100. In some embodiments, the etching process may include wet etching, dry etching, or the like. For example, the etching process may include anisotropic etching using Cl2-based reactive ion etching (RIE).

[0089] refer to Figure 4A and Figure 4B ,in Figure 4A is a top view of a semiconductor device, Figure 4B To follow Figure 4A BB. An isolation structure 106 is formed above the substrate 100 and laterally surrounds the fin structure. In some embodiments, the isolation structure 106 may contact the sidewalls of the semiconductor strip 100P of the substrate 100. The isolation structure 106 may be a shallow trench isolation (STI) structure, a suitable isolation structure, a combination thereof, or the like. In some embodiments, the isolation structure 106 may be made of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof. In some embodiments, the isolation structure 106 may be formed by, for example, depositing a blanket layer of dielectric material above the substrate 100, performing a planarization process on the dielectric material, and then etching back the dielectric material to lower the top surface of the dielectric material to a desired position.

[0090] refer to Figure 5A and Figure 5B wherein Figure 5A is a top view of a semiconductor device, Figure 5B is a cross-sectional view along line A-A of Figure 5A The dummy gate structure 112 is formed over the substrate 100 and intersects the fin structures. In more detail, the dummy gate structure 112 can intersect the stacks ST1 and ST2, as well as the semiconductor strips 100P. In some embodiments, the dummy gate structure 112 can be formed by, for example, depositing a blanket layer of dummy gate material over the substrate 100, forming a dummy gate hardmask 114 over the dummy gate material, followed by performing an etching process to remove portions of the dummy gate material exposed via the dummy gate hardmask 114. In some embodiments, the dummy gate structure 112 can be a conductive or non-conductive material, and can be selected from a group including amorphous silicon, polysilicon (poly-silicon), poly-silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. In some embodiments, the dummy gate hardmask 114 can include a dielectric material, such as silicon oxycarbide (SiOC). In some embodiments, the dummy gate structure 112 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputter deposition, or other techniques for depositing the selected material.

[0091] Referring to Figure 6A and Figure 6B wherein Figure 6A is a top view of a semiconductor device, Figure 6B is a cross-sectional view along line A-A of Figure 6A The gate spacers 115 are formed on opposite sidewalls of the dummy gate structure 112 and opposite sidewalls of the dummy gate hardmask 114. In some embodiments, the gate spacers 115 can be formed of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. In some embodiments, the gate spacers 115 can be formed by, for example, depositing a spacer layer blanket over the substrate 100, followed by performing an anisotropic etching process to remove horizontal portions of the spacer layer, such that vertical portions of the spacer layer remain on the sidewalls of the dummy gate structure 112. The spacer layer can be deposited using techniques such as CVD, ALD, or the like.

[0092] Referring to Figure 7A and Figure 7B wherein Figure 7A is a top view of a semiconductor device, Figure 7B is a cross-sectional view along line A-A of Figure 7AAA cross-sectional view of the line AA of . The etching process is performed using the gate spacer 115 and the dummy gate hard mask 114 (or the dummy gate structure 112) as an etching mask to remove the portion of the stack ST2 exposed through the gate spacer 115 and the dummy gate hard mask 114 (or the dummy gate structure 112). In more detail, portions of the second sacrificial layer 103 and the second semiconductor layer 104 are removed during the etching process. In some embodiments, the etching process may include anisotropic etching, such as RIE. In some embodiments, the first sacrificial layer 101 may have a higher etching resistance to the etching process than the second sacrificial layer 103 and the second semiconductor layer 104, and thus the first sacrificial layer 101 may act as an etching stop layer during the etching process. As a result, the etching process may terminate at the topmost first sacrificial layer 101. After the etching process is completed, a portion of the top surface of the topmost first sacrificial layer 101 may be exposed. In some embodiments, Figure 7B In the cross-sectional view of , the second sacrificial layer 103 and the second semiconductor layer 104 may include a narrower width than the first sacrificial layer 101 and the first semiconductor layer 102 .

[0093] refer to Figure 8A and Figure 8B ,in Figure 8A is a top view of a semiconductor device, Figure 8B To follow Figure 8A AA cross-sectional view. Spacers 116 are formed on opposite sidewalls of the stack ST2. More specifically, the spacers 116 are formed to cover the sidewalls of the second sacrificial layer 103 and the second semiconductor layer 104. On the other hand, the sidewalls of the stack ST1 may be exposed through the spacers 116. More specifically, the sidewalls of the first sacrificial layer 101 and the first semiconductor layer 102 are exposed through the spacers 116. In some embodiments, the spacers 116 may also extend to the sidewalls of the gate spacer 115. In some embodiments, the spacers 116 may also contact the top surface of the topmost first sacrificial layer 101. In some embodiments, the spacers 116 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the spacers 116 and the gate spacers 115 may include the same material. In some embodiments, the spacers 116 may be formed by, for example, depositing a blanket spacer layer over the substrate 100, then performing an anisotropic etching process to remove the horizontal portion of the spacer layer, so that the vertical portion of the spacer layer remains on the sidewalls of the stack ST2. The spacer layer may be deposited using techniques such as CVD, ALD, or the like.

[0094] refer to Figure 9A and Figure 9B ,in Figure 9A is a top view of a semiconductor device, Figure 9B To follow Figure 9AFIG. 1 is a cross-sectional view along line A-A of the semiconductor device of FIG. 0. An etch process is performed to laterally etch the sidewalls of the first sacrificial layer 101, thereby forming sidewall recesses Rl on opposite ends of the etched first sacrificial layer. In some embodiments, the etch process can include a wet etch, a dry etch, or a combination thereof.

[0095] Referring to Figure 10A and Figure 10B wherein Figure 10A is a top-down view of a semiconductor device, Figure 10B is a cross-sectional view along line A-A of the semiconductor device of FIG. 0. An etch process is performed to laterally etch the sidewalls of the first sacrificial layer 101, thereby forming sidewall recesses Rl on opposite ends of the etched first sacrificial layer. In some embodiments, the etch process can include a wet etch, a dry etch, or a combination thereof. Figure 10A Referring to

[0096] and Figure 11A wherein Figure 11B is a top-down view of a semiconductor device, Figure 11A is a cross-sectional view along line A-A of the semiconductor device of FIG. 0. An etch process is performed to laterally etch the sidewalls of the first sacrificial layer 101, thereby forming sidewall recesses Rl on opposite ends of the etched first sacrificial layer. In some embodiments, the etch process can include a wet etch, a dry etch, or a combination thereof. Figure 11B Figure 11A Referring to wherein

[0097] is a top-down view of a semiconductor device, 12A to 12C is a cross-sectional view along line A-A of the semiconductor device of FIG. 0, Figure 12A is a cross-sectional view along line A-A of the semiconductor device of FIG. 0, Figure 12B is a cross-sectional view along line A-A of the semiconductor device of FIG. 0, Figure 12A is a cross-sectional view along line A-A of the semiconductor device of FIG. 0, Figure 12C is a cross-sectional view along line A-A of the semiconductor device of FIG. 0, Figure 12A, a cross-sectional view taken along line CC. A first source / drain epitaxial structure 120 is formed on opposite ends of the first semiconductor layer 102. The first source / drain epitaxial structure 120 can be formed by a suitable deposition process, such as a selective epitaxial growth (SEG) process. In some embodiments, the SEG process can selectively grow semiconductor material on an exposed semiconductor surface, such as an exposed surface of the first semiconductor layer 102. In some embodiments, an implantation process can be performed on the first source / drain epitaxial structure 120. For example, the implantation process can include an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or the like, such that the first source / drain epitaxial structure 120 is an n-type epitaxial structure. Alternatively, the implantation process can include a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like, such that the first source / drain epitaxial structure 120 is a p-type epitaxial structure.

[0098] A conductive layer 125 is formed over the substrate 100 and covers the first source / drain epitaxial structures 120. In some embodiments, the conductive layer 125 may include a metal such as tungsten (W), aluminum (Al), copper (Cu), silver (Ag), or another suitable conductive material. The conductive layer 125 may be formed by, for example, depositing a blanket layer of conductive material over the substrate 100 and covering the first source / drain epitaxial structures 120, followed by a planarization process such as CMP to remove excess conductive material until the top surface of the patterned mask MA2 is exposed.

[0099] refer to 13A to 13C ,in Figure 13A is a top view of a semiconductor device, Figure 13B To follow Figure 13A The cross-sectional view of line AA, Figure 13C To follow Figure 13A . The conductive layer 125 is subjected to an etch-back process, thereby lowering the top surface of the conductive layer 125 until the first source / drain epitaxial structure 120 is exposed. After the etch-back process is completed, the remaining portion of the conductive layer 125 is on the opposite side of the first source / drain epitaxial structure 120 (see FIG. Figure 13C In some embodiments, the conductive layer 125 may be etched using dry etching, wet etching, or the like.

[0100] refer to Figure 14A and Figure 14B ,in Figure 14A is a top view of a semiconductor device, Figure 14B To follow Figure 14AAA cross-sectional view. An isolation structure 128 is formed over the substrate 100 and covers the first source / drain epitaxial structure 120 and the conductive layer 125. In some embodiments, the isolation structure 128 may include silicon dioxide (SiO2), silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials. The isolation structure 128 may be formed by, for example, depositing a blanket layer of dielectric material over the substrate 100 and covering the first source / drain epitaxial structure 120 and the conductive layer 125, followed by a planarization process such as CMP to remove excess dielectric material until the top surface of the patterned mask MA2 is exposed.

[0101] refer to Figures 15A to 15C ,in Figure 15A is a top view of a semiconductor device, Figure 15B To follow Figure 15A The cross-sectional view of line AA, Figure 15C To follow Figure 15A 1. A cross-sectional view of line CC is shown. An etch-back process is performed on isolation structure 128, thereby lowering the top surface of isolation structure 128. In more detail, the top surface of isolation structure 128 may be lowered to a level lower than the second semiconductor layer 104. In some embodiments, isolation structure 128 may be etched using dry etching, wet etching, or the like.

[0102] refer to Figure 16A and Figure 16B ,in Figure 16A is a top view of a semiconductor device, Figure 16B To follow Figure 16A AA cross-sectional view. The patterned mask MA2 is removed. As a result, the top surfaces of the dummy gate hard mask 114, the gate spacer 115, and the spacer 116 are exposed. In some embodiments, the patterned mask MA2 can be removed using a suitable etching process, such as dry etching, wet etching, or the like.

[0103] refer to Figure 17A and Figure 17B ,in Figure 17A is a top view of a semiconductor device, Figure 17B To follow Figure 17A AA cross-sectional view. Spacers 116 are removed. As a result, the sidewalls of second sacrificial layer 103 and second semiconductor layer 104 are exposed. In some embodiments, after removing spacers 116, portions of the top surfaces of inner spacers 117 may also be exposed. In some embodiments, spacers 116 may be removed using a suitable etching process, such as dry etching, wet etching, or the like.

[0104] refer to Figure 18Aand Figure 18B ,in Figure 18A is a top view of a semiconductor device, Figure 18B To follow Figure 18A AA cross-sectional view. The second sacrificial layer 103 is laterally etched to form sidewall recesses. Next, inner spacers 129 are formed in the sidewall recesses on opposite ends of each of the second sacrificial layers 103. In some embodiments, the inner spacers 129 can be formed by, for example, depositing an inner spacer blanket layer over the substrate 100 and filling the sidewall recesses, then performing anisotropic etching to remove portions of the inner spacer layer outside the sidewall recesses, thereby leaving the remaining portions of the inner spacer layer in the sidewall recesses as the inner spacers 129. The inner spacers 129 can be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer may include materials such as SiN, SiOCN, SiCN, or SIOC.

[0105] refer to 19A to 19C ,in Figure 19A is a top view of a semiconductor device, Figure 19B To follow Figure 19A The cross-sectional view of line AA, Figure 19C To follow Figure 19A . A second source / drain epitaxial structure 130 is formed on opposite ends of the second semiconductor layer 104. The second source / drain epitaxial structure 130 can be formed by a suitable deposition process, such as a selective epitaxial growth (SEG) process. In some embodiments, the SEG process can selectively grow semiconductor material on an exposed semiconductor surface, such as an exposed surface of the second semiconductor layer 104. In some embodiments, an implantation process can be performed on the second semiconductor layer 104. For example, the implantation process can include an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or the like, such that the second source / drain epitaxial structure 130 is an n-type epitaxial structure. On the other hand, the implantation process can include a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), or the like, such that the second source / drain epitaxial structure 130 is a p-type epitaxial structure. In some embodiments, the first source / drain epitaxial structure 120 and the second source / drain epitaxial structure 130 have different conductivity types. For example, if the first source / drain epitaxial structure 120 is doped with n-type impurities, the second source / drain epitaxial structure 130 is doped with p-type impurities. Alternatively, if the first source / drain epitaxial structure 120 is doped with p-type impurities, the second source / drain epitaxial structure 130 is doped with n-type impurities.

[0106] refer to 20A to 20C ,in Figure 20Ais a top view of a semiconductor device, Figure 20B To follow Figure 20A The cross-sectional view of line AA, Figure 20C To follow Figure 20A The isolation structure 132 is formed on the substrate 100 and covers the second source / drain epitaxial structure 130. The isolation structure 132 may also contact the top surface of the isolation structure 128 (see FIG. Figure 20C In some embodiments, the isolation structure 132 may include silicon dioxide (SiO2), silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, and / or other suitable dielectric materials. The isolation structure 132 may be formed by, for example, depositing a blanket layer of dielectric material over the substrate 100 and covering the second source / drain epitaxial structure 130 and the isolation structure 1128, followed by a planarization process such as CMP to remove excess dielectric material until the top surfaces of the dummy gate hard mask 114 and the gate spacers 115 are exposed.

[0107] refer to Figures 21A to 21C ,in Figure 21A is a top view of a semiconductor device, Figure 21B To follow Figure 21A The cross-sectional view of line AA, Figure 21C To follow Figure 21A A patterning process is performed to remove portions of the gate spacer 115 and the isolation structure 132 to form an opening O1 (see FIG. 1 ) exposing the sidewall of the dummy gate structure 112. Figure 21C In some embodiments, the opening O1 may be formed by, for example, forming a photoresist layer having an opening over the substrate 100, performing an etching process to remove portions of the gate spacer 115 and the isolation structure 132 exposed by the photoresist layer, and then removing the photoresist layer after the etching process is completed.

[0108] refer to Figures 22A to 22C ,in Figure 22A is a top view of a semiconductor device, Figure 22B To follow Figure 22A The cross-sectional view of line AA, Figure 22C To follow Figure 22A The dummy gate hard mask 114 and the dummy gate structure 112 are removed to expose the first sacrificial layer 101 and the second sacrificial layer 103. Due to the removal of the dummy gate structure 112, a gate trench GT1 is formed between the gate spacers 115 (see FIG. Figure 22B The dummy gate structure 112 may be removed using a suitable etching process, such as dry etching, wet etching, or a combination thereof.

[0109] Next, the first sacrificial layer 101 and the second sacrificial layer 103 are removed through the gate trench GT1, so that the first semiconductor layer 102 and the second semiconductor layer 104 are suspended above the substrate 100. In more detail, the channel regions of the first semiconductor layer 102 and the second semiconductor layer 104 are suspended above the substrate 100 through the gate trench GT1. The first sacrificial layer 101 and the second sacrificial layer 103 can be removed using a suitable etching process, such as dry etching, wet etching, or a combination thereof.

[0110] refer to Figures 23A to 23C ,in Figure 23A is a top view of a semiconductor device, Figure 23B To follow Figure 23A The cross-sectional view of line AA, Figure 23C To follow Figure 23A The gate dielectric layer 140 and the gate electrode 142 are sequentially deposited on the substrate 100 and surround the channel regions of the first semiconductor layer 102 and the second semiconductor layer 104. In some embodiments, a portion of the gate dielectric layer 140 may also extend to the top surface of the semiconductor strip 100P and the isolation structure 106 (see FIG. Figure 23C The gate dielectric layer 140 and the gate electrode 142 may be formed using a conformal deposition process such as ALD, CVD, or the like.

[0111] The gate dielectric layer 140 may include an interfacial layer and / or a high-k dielectric. The interfacial layer may include silicon dioxide (SiO2). Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide (Al2O3), titanium oxide, a hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate electrode 142 may include a titanium-based material or a tantalum-based material, such as Ti, TiN, Ta, TaN, or the like. The gate electrode 142 may also include a metal, such as tungsten (W), aluminum (Al), copper (Cu), silver (Ag), or the like.

[0112] refer to Figures 24A to 24C ,in Figure 24A is a top view of a semiconductor device, Figure 24B To follow Figure 24A The cross-sectional view of line AA, Figure 24C To follow Figure 24AThe isolation structure 145 is formed in the gate trench GT1 and surrounds the first semiconductor layer 102 and the second semiconductor layer 104. In some embodiments, the isolation structure 145 may be silicon dioxide (SiO2). In other embodiments, the isolation structure 145 may include a low-k dielectric material such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y In some embodiments, the isolation structure 145 can be formed by, for example, depositing a dielectric material filling the gate trench GT1 and then performing a planarization process such as CMP to remove excess dielectric material until the isolation structure 132 is exposed.

[0113] refer to Figures 25A to 25C ,in Figure 25A is a top view of a semiconductor device, Figure 25B To follow Figure 25A The cross-sectional view of line AA, Figure 25C To follow Figure 25A BB is a cross-sectional view of FIG. A patterned mask MA3 is formed over substrate 100. More specifically, patterned mask MA3 is formed over isolation structure 132 and has an opening that exposes a portion of isolation structure 145. In some embodiments, patterned mask MA3 may be a photoresist. In some embodiments, patterned mask MA3 may be a hard mask and may include a dielectric material such as silicon dioxide (SiO2) or silicon nitride (SiN).

[0114] refer to Figures 26A to 26C ,in Figure 26A is a top view of a semiconductor device, Figure 26B To follow Figure 26A The cross-sectional view of line AA, Figure 26C To follow Figure 26A , a cross-sectional view taken along line BB. The portion of the isolation structure 145 exposed through the patterned mask MA3 is etched back, lowering the top surface of the portion of the isolation structure 145 to a level lower than the second semiconductor layer 104 and higher than the first semiconductor layer 102. Consequently, a portion of the gate electrode 142 is exposed through the isolation structure 145. More specifically, after the etch-back process, the portion of the gate electrode 142 surrounding the second semiconductor layer 104 is exposed. On the other hand, as a result of the etch-back process, the channel region of the second semiconductor layer 104 is no longer covered by the isolation structure 145, while the channel region of the first semiconductor layer 102 remains covered by the isolation structure 145. The etch-back process may include dry etching, wet etching, or a combination thereof.

[0115] refer to Figures 27A to 27C ,in Figure 27A is a top view of a semiconductor device, Figure 27B To follow Figure 27A The cross-sectional view of line AA, Figure 27C To follow Figure 27A The portion of the gate electrode 142 exposed by the isolation structure 145 is removed, thereby exposing the portion of the gate dielectric layer 140 surrounding the second semiconductor layer 104. The portion of the gate electrode 142 can be removed by a suitable etching process, such as dry etching, wet etching, or a combination thereof.

[0116] refer to Figures 28A to 28C ,in Figure 28A is a top view of a semiconductor device, Figure 28B To follow Figure 28A The cross-sectional view of line AA, Figure 28C To follow Figure 28A BB. A gate dielectric layer 150 and a gate electrode 152 are sequentially deposited over the substrate 100 and surround the channel region of the second semiconductor layer 104. The gate dielectric layer 150 may contact the portion of the gate dielectric layer 140 surrounding the second semiconductor layer 104. In some embodiments, a portion of the gate dielectric layer 150 may also extend to the surface of the isolation structure 145. The gate dielectric layer 150 and the gate electrode 152 may be formed using a conformal deposition process such as ALD, CVD, or the like.

[0117] The gate dielectric layer 150 may include an interfacial layer and / or a high-k dielectric. The interfacial layer may include silicon dioxide (SiO2). Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide (Al2O3), titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate electrode 152 may also include a titanium-based material or a tantalum-based material, such as Ti, TiN, Ta, TaN, or the like. The gate electrode 152 may also include a metal, such as tungsten (W), aluminum (Al), copper (Cu), silver (Ag), or the like.

[0118] After depositing the gate dielectric layer 150 and the gate electrode 152, the first metal gate structure 172 and the second metal gate structure 174 are formed, where the first metal gate structure 172 surrounds the channel region of the first semiconductor layer 102, and the second metal gate structure 174 surrounds the channel region of the second semiconductor layer 104. In some embodiments, the first metal gate structure 172 can include the gate dielectric layer 140 and the gate electrode 142 over the gate dielectric layer 140. On the other hand, the second metal gate structure 174 can include the gate dielectric layer 140, the gate dielectric layer 150 over the gate dielectric layer 140, and the gate electrode 152 over the gate dielectric layer 150. In some embodiments, the thickness of the gate dielectric (e.g., the gate dielectric layer 140) of the first metal gate structure 172 is less than the thickness of the gate dielectric (e.g., the gate dielectric layers 140 and 150) of the second metal gate structure 174.

[0119] The first semiconductor layer 102, the first metal gate structure 172 surrounding the first semiconductor layer 102, and the first source / drain epitaxial structure 120 on the opposite ends of the first semiconductor layer 102 can collectively function as a first transistor (e.g., as described by the first transistor TR1). Figures 1A to 1D The second semiconductor layer 104, the second metal gate structure 174 surrounding the second semiconductor layer 104, and the second source / drain epitaxial structure 130 on the opposite ends of the second semiconductor layer 104 can collectively function as a second transistor (e.g., as described by the second transistor TR2). In some embodiments, the second transistor is vertically stacked on top of the first transistor. Figures 1A to 1D

[0120] Referring to Figure 29A and Figure 29B wherein Figure 29A is a top-down view of a semiconductor device, Figure 29B is a cross-sectional view along line A-A of Figure 29A The patterned mask MA3 is removed. As a result, the top surfaces of the second metal gate structure 174, the gate spacer 115, and the isolation structure 132 are exposed. In some embodiments, the patterned mask MA3 can be removed using a suitable etching process, such as dry etching, wet etching, or the like.

[0121] Referring to Figure 30A and Figure 30B wherein Figure 30A is a top-down view of a semiconductor device, Figure 30B is a cross-sectional view along line A-A of Figure 30A ​, which is a cross-sectional view taken along line CC. Conductive layer 160 is formed in isolation structure 132 and contacts the respective conductive layers 125 below isolation structures 128 and 132. Each conductive layer 160 and its underlying conductive layer 125 may be collectively referred to as bottom source / drain contacts 182. In some embodiments, conductive layer 160 may comprise a metal such as tungsten (W), aluminum (Al), copper (Cu), silver (Ag), or another suitable conductive material. Conductive layers 160 and 125 may comprise the same material. Conductive layer 160 may be formed by, for example, patterning isolation structure 132 to form an opening in isolation structure 132, filling the opening with a conductive material, and then performing a planarization process such as CMP to remove excess conductive material until the top surface of second metal gate structure 174 is exposed.

[0122] like Figure 30B As shown, bottom source / drain contact 182 contacts the sidewalls of first source / drain epitaxial structure 120, while the top surface of first source / drain epitaxial structure 120 is covered by isolation structure 128. Bottom source / drain contact 182 is spaced apart from second source / drain epitaxial structure 130. In some embodiments, bottom source / drain contact 182 may have an L-shaped cross-section. More specifically, bottom source / drain contact 182 includes a first portion (e.g., conductive layer 125) and a second portion (e.g., conductive layer 160) above the first portion, wherein the first portion is laterally wider than the second portion.

[0123] refer to Figures 31A to 31D ,in Figure 31A is a top view of a semiconductor device, Figure 31B To follow Figure 31A The cross-sectional view of line AA, Figure 31C To follow Figure 31A The cross-sectional view of line BB, Figure 31D To follow Figure 31A 145 and is a cross-sectional view taken along line CC. A bottom gate contact 190 is formed in the isolation structure 145 and electrically connected to the first metal gate structure 170. In some embodiments, the bottom gate contact 190 may comprise a metal such as tungsten (W), aluminum (Al), copper (Cu), silver (Ag), or another suitable conductive material. The bottom gate contact 190 may be formed by, for example, patterning the isolation structure 145 to form an opening therein, filling the opening with a conductive material, and then performing a planarization process such as CMP to remove excess conductive material until the top surface of the second metal gate structure 174 is exposed.

[0124] exist Figure 31CIn cross-sectional view, the isolation structure 145 can surround the first semiconductor layer 102. The isolation structure 145 has a portion 145A vertically between the gate electrode 142 of the first metal gate structure 172 and the gate electrode 152 of the second metal gate structure 174. As shown in Figure 31B and Figure 31C shown, the isolation structure 145 further includes a portion 145B vertically between the first semiconductor layer 102 and the semiconductor strip 100P of the substrate 100. As shown in Figure 31C and

[0125] As shown in Figure 31B , the gate electrode 142 of the first metal gate structure 172 can surround the portion 145B of the isolation structure 145. For example, in Figure 31B , the gate electrode 142 of the first metal gate structure 172 can include a portion 142A in contact with a top surface of the portion 145B of the isolation structure 145, a portion 142B in contact with a bottom surface of the portion 145B of the isolation structure 145, and two portions 142C connecting the portions 142A and 142B to each other. That is, the portions 142A, 142B, and 142C can form a rectangular ring structure surrounding the portion 145B of the isolation structure 145, as shown in Figure 31B .

[0126] The bottom gate contact 190 can be in contact with a portion of the gate electrode 142 of the first metal gate structure 22. In more detail, as shown in Figure 31C , the portion 142B of the gate electrode 142 can extend to a bottom surface of the bottom gate contact 190. Specifically, the portion 142B of the gate electrode 142 is in contact with and electrically connected to the bottom surface of the bottom gate contact 190. As a result, the portions 142A and 142C of the gate electrode 142 can also be electrically connected to the bottom gate contact 190. In some embodiments, the portion 142B of the gate electrode 142 is also vertically between the bottom gate contact 190 and the isolation structure 106 (or the substrate 100). In some embodiments, the gate dielectric layer 140 has a portion vertically between the portion 142B of the gate electrode 142 and the substrate 100. Furthermore, the portion of the gate dielectric layer 140 also extends to a location vertically between the bottom surface of the bottom gate contact 190 and the substrate 100.

[0127] As shown in Figure 31CAs shown, the top surface of the bottom gate contact 190 is substantially flush with the top surface of the second metal gate structure 174 and the top surface of the isolation structure 145. The bottom surface of the bottom gate contact 190 is lower than the bottom surface of the second metal gate structure 174 and substantially flush with the bottom surface of the isolation structure 145. In some embodiments, the bottom gate contact 190 is laterally separated from the second metal gate structure 174 by the isolation structure 145.

[0128] like Figure 31C and Figure 31D As shown, the bottom gate contact 190 is vertically separated from the isolation structure 106 by the gate dielectric layer 140 and the gate electrode 142 , while the bottom source / drain contacts 182 are in contact with the isolation structure 106 .

[0129] like Figure 31A As shown, in a top view, the bottom gate contact 190 is separated from the second metal gate structure 174 by the isolation structure 145. That is, the isolation structure 145 is between the bottom gate contact 190 and the second metal gate structure 174 along a first direction. On the other hand, the bottom gate contact 190 and the bottom source / drain contacts 182 are laterally arranged along a second direction perpendicular to the first direction.

[0130] Based on the above embodiments, it can be seen that the present disclosure provides advantages in manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, not all advantages are necessarily disclosed herein, and no particular advantages need to apply to all embodiments. Embodiments of the present disclosure provide a CFET that includes a first transistor and a second transistor above the first transistor. The CFET includes a split-gate structure in which an isolation structure is formed to electrically isolate a first gate structure of the first transistor from a second gate structure of the second transistor. Such a configuration can provide a better area reduction, which is beneficial for device scaling.

[0131] In some embodiments disclosed herein, a semiconductor device includes a first transistor, a second transistor above the first transistor, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer, and first source / drain epitaxial structures on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer, and second source / drain epitaxial structures on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view, the isolation structure is adjacent to the second gate structure, and wherein in a first cross-sectional view, the isolation structure surrounds the first semiconductor channel layer.

[0132] In some embodiments, a top surface of the isolation structure is substantially flush with a top surface of the second gate structure, and a bottom surface of the isolation structure is lower than a bottom surface of the second gate structure.

[0133] In some embodiments, the isolation structure has a portion vertically located between the first semiconductor channel layer and the substrate, and wherein in a second cross-sectional view perpendicular to the first cross-sectional view, the first gate structure surrounds the portion of the isolation structure.

[0134] In some embodiments, in the first cross-sectional view, the isolation structure contacts sidewalls and a bottom surface of the second gate structure.

[0135] In some embodiments, the semiconductor device further includes a bottom gate contact electrically connected to the first gate structure, wherein the isolation structure is laterally located between the bottom gate contact and the second gate structure.

[0136] In some embodiments, in the first cross-sectional view, the first gate structure includes a gate electrode in contact with a bottom surface of the bottom gate contact.

[0137] In some embodiments, a top surface of the bottom gate contact is substantially flush with a top surface of the second gate structure, and a bottom surface of the bottom gate contact is lower than a bottom surface of the second gate structure.

[0138] In some embodiments, the semiconductor device further includes a bottom source / drain contact in contact with one of the first source / drain epitaxial structures, wherein the bottom source / drain contact has an L-shaped cross-sectional profile.

[0139] In some embodiments disclosed herein, a semiconductor device includes a first transistor, a second transistor above the first transistor, and a bottom gate contact. The first transistor includes a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer, and first source / drain epitaxial structures on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer, and second source / drain epitaxial structures on opposite ends of the second semiconductor channel layer. The bottom gate contact contacts the first gate structure and is spaced apart from the second gate structure, wherein a top surface of the bottom gate contact is higher than a top surface of the first semiconductor channel layer, and a bottom surface of the bottom gate structure is lower than a bottom surface of the first semiconductor channel layer.

[0140] In some embodiments, the semiconductor device further includes a shallow trench isolation structure above the substrate, wherein the first gate structure includes a gate electrode, and the gate electrode has a portion vertically located between the bottom gate contact and the shallow trench isolation structure.

[0141] In some embodiments, a portion of the gate electrode contacts a bottom surface of the bottom gate contact.

[0142] In some embodiments, the semiconductor device further includes an isolation structure between the bottom gate contact and the second gate structure, wherein the isolation structure has a first portion vertically located between the first gate structure and the second gate structure.

[0143] In some embodiments, the isolation structure has a second portion vertically located between the first gate structure and the substrate.

[0144] In some embodiments, in a cross-sectional view, the isolation structure surrounds the first semiconductor channel layer.

[0145] In some embodiments, the first gate structure includes a gate electrode, and the gate electrode has a portion extending from a bottom surface of the isolation structure to a bottom surface of the bottom gate contact.

[0146] In some embodiments disclosed herein, a method includes forming a first semiconductor layer and a second semiconductor layer above a substrate; forming a first gate dielectric layer having a first portion surrounding the first semiconductor layer and a second portion surrounding the second semiconductor layer; forming a first gate electrode having a first portion surrounding the first semiconductor layer and a second portion surrounding the second semiconductor layer; forming an isolation structure surrounding the first semiconductor layer and the second semiconductor layer; etching back a portion of the isolation structure to expose the second portion of the first gate electrode; removing the second portion of the first gate electrode; forming a second gate dielectric layer surrounding the second semiconductor layer; and forming a second gate electrode surrounding the second semiconductor layer.

[0147] In some embodiments, the etch-back of the isolation structure is performed such that the first portion of the first gate electrode remains covered by the etched portion of the isolation structure.

[0148] In some embodiments, the second gate dielectric layer contacts the second portion of the first gate dielectric layer.

[0149] In some embodiments, the method further includes forming a bottom gate contact in the isolation structure, wherein the bottom gate contact contacts a third portion of the first gate electrode extending over the shallow trench isolation structure above the substrate.

[0150] In some embodiments, the method further includes forming sacrificial layers alternating with the first semiconductor layer and the second semiconductor layer; and removing the sacrificial layers before forming the first gate dielectric layer.

[0151] In some embodiments disclosed herein, a semiconductor device includes a first transistor, a second transistor above the first transistor, and an isolation structure. The first transistor includes a first semiconductor channel layer, a first gate structure surrounding the first semiconductor channel layer, and a first source / drain epitaxial structure on opposite ends of the first semiconductor channel layer. The second transistor includes a second semiconductor channel layer, a second gate structure surrounding the second semiconductor channel layer, and a second source / drain epitaxial structure on opposite ends of the second semiconductor channel layer. The isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view, the isolation structure is adjacent to the second gate structure, wherein in a first cross-sectional view, the isolation structure surrounds the first semiconductor channel layer, wherein the isolation structure has a portion vertically located between the first semiconductor channel layer and the substrate, and wherein in a second cross-sectional view perpendicular to the first cross-sectional view, the first gate structure surrounds the portion of the isolation structure.

[0152] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and replacements may be made herein for such equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: A first transistor, located above a substrate, comprises: a first semiconductor channel layer; a first gate structure surrounding the first semiconductor channel layer; and A plurality of first source / drain epitaxial structures are provided on opposite ends of the first semiconductor channel layer; and a second transistor is vertically disposed above the first transistor, comprising: a second semiconductor channel layer; a second gate structure surrounding the second semiconductor channel layer; as well as a plurality of second source / drain epitaxial structures on opposite ends of the second semiconductor channel layer; as well as An isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view, the isolation structure is adjacent to the second gate structure, and wherein in a first cross-sectional view, the isolation structure surrounds the first semiconductor channel layer.

2. The semiconductor device according to claim 1, wherein A top surface of the isolation structure is substantially flush with a top surface of the second gate structure, and a bottom surface of the isolation structure is lower than a bottom surface of the second gate structure.

3. The semiconductor device according to claim 1, wherein The isolation structure has a portion vertically located between the first semiconductor channel layer and the substrate, and in a second cross-sectional view perpendicular to the first cross-sectional view, the first gate structure surrounds the portion of the isolation structure.

4. The semiconductor device according to claim 1, wherein In the first cross-sectional view, the isolation structure contacts a sidewall and a bottom surface of the second gate structure.

5. The semiconductor device according to claim 1, wherein It further includes a bottom gate contact electrically connected to the first gate structure, wherein the isolation structure is laterally located between the bottom gate contact and the second gate structure.

6. The semiconductor device according to claim 5, wherein In the first cross-sectional view, the first gate structure includes a gate electrode in contact with a bottom surface of the bottom gate contact.

7. The semiconductor device according to claim 5, wherein A top surface of the bottom gate contact is substantially flush with a top surface of the second gate structure, and a bottom surface of the bottom gate contact is lower than a bottom surface of the second gate structure.

8. The semiconductor device according to claim 1, wherein Further included is a bottom source / drain contact in contact with one of the plurality of first source / drain epitaxial structures, wherein the bottom source / drain contact has an L-shaped cross-sectional profile.

9. A semiconductor device, characterized in that: Include: A first transistor, located above a substrate, comprises: a first semiconductor channel layer; a first gate structure surrounding the first semiconductor channel layer; and A plurality of first source / drain epitaxial structures are provided on opposite ends of the first semiconductor channel layer; and a second transistor is vertically located above the first transistor, comprising: a second semiconductor channel layer; a second gate structure surrounding the second semiconductor channel layer; as well as a plurality of second source / drain epitaxial structures on opposite ends of the second semiconductor channel layer; as well as A bottom gate contact is in contact with the first gate structure and spaced apart from the second gate structure, wherein a top surface of the bottom gate contact is higher than a top surface of the first semiconductor channel layer, and a bottom surface of the bottom gate contact is lower than a bottom surface of the first semiconductor channel layer.

10. A semiconductor device, characterized in that: Include: A first transistor, located above a substrate, comprises: a first semiconductor channel layer; a first gate structure surrounding the first semiconductor channel layer; and A plurality of first source / drain epitaxial structures are provided on opposite ends of the first semiconductor channel layer; and a second transistor is vertically located above the first transistor, comprising: a second semiconductor channel layer; a second gate structure surrounding the second semiconductor channel layer; as well as a plurality of second source / drain epitaxial structures on opposite ends of the second semiconductor channel layer; as well as An isolation structure electrically isolates the first gate structure from the second gate structure, wherein in a top view, the isolation structure is adjacent to the second gate structure, wherein in a first cross-sectional view, the isolation structure surrounds the first semiconductor channel layer, wherein the isolation structure has a portion vertically located between the first semiconductor channel layer and the substrate, and wherein in a second cross-sectional view perpendicular to the first cross-sectional view, the first gate structure surrounds the portion of the isolation structure.

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