Rapid cable detection device

Abstract

The utility model discloses a cable rapid detection device, which belongs to the field of electronic detection, and is characterized in that a cable or a flat cable is rapidly connected through a rapid plugging male head and a rapid plugging female head, so that plugging is convenient; the purpose of detecting the multi-core cable can be achieved through the clock circuit, the pulse generation circuit and the pulse transmission circuit. The device mainly comprises a shell, a detection controller is arranged in the shell, the shell is further provided with a plurality of detection lamps, a power lamp and a test button S1, the detection controller is connected with a connector J1, a connector J2 and a connector J3 through the detection lamps, and the detection controller comprises a clock circuit, a pulse generation circuit and a pulse transmission circuit. The pulse generation circuit comprises a NOR gate U2A and a NOR gate U2B, and an input pin 3 of the NOR gate U2A is connected with the test button S1 through the RC delay circuit. The cable rapid detection device is mainly used for cable rapid detection.

Description

Technical Field

[0001] The utility model relates to the field of electronic detection, and in particular to a cable rapid detection device. Background Art

[0002] Fast-connect cables such as flat cables are widely used in the wiring of electronic products due to their easy plug-in characteristics, which facilitates later maintenance. Many products require the assembly of such cables. After assembly, the cable's conductivity and the presence of damaged conductors must be tested. To ensure the conductivity of the cable after assembly, each pair of wire cores must be tested. There is currently a test device for the conductivity and short circuit of flat cables, such as the publication number CN116224155A, which cannot accurately test the continuity of multi-core cables. With existing products, it is difficult for one person to complete the test because the connector is very small and cannot be fixed. In addition, the connector pins are numerous and densely packed, and it is easy to confuse the corresponding relationship, resulting in misjudgment, and the labor and time costs are very high. Utility Model Content

[0003] The purpose of the present utility model is to provide a cable rapid detection device, which can quickly connect cables or cables through a quick plug-in male connector and a quick plug-in female connector, making the connection convenient; and can achieve the purpose of detecting multi-core cables through a clock circuit, a pulse generating circuit and a pulse transmission circuit.

[0004] The utility model is realized through the following technical solutions:

[0005] A cable rapid detection device includes a shell, in which a detection controller is provided. The shell is also provided with several detection lights, a power light and a test button S1. The detection controller is respectively connected to the connector J1, the connector J2 and the connector J3 through the several detection lights. The detection controller includes a clock circuit, a pulse generating circuit and a pulse transfer circuit. The pulse generating circuit includes a NOR gate U2A and a NOR gate U2B. The input pin 3 of the NOR gate U2A is connected to the test button S1 through an RC delay circuit. The output pin 1 of the NOR gate U2A is connected in series with a resistor R3 and a capacitor C2 and then connected to the input pin 5 of the NOR gate U2B. The input pin 5 of the NOR gate U2B is also connected to a pull-up resistor R4. The input pin 2 of the NOR gate U2A is respectively connected to the output pin 4 of the NOR gate U2B and the input pin 9 of the NOR gate U2C. The output pin 10 of the NOR gate U2C is connected in series with a resistor R7 and a capacitor C3 and then connected to the clock circuit. The clock circuit and the input pin 9 of the NOR gate U2C are respectively connected to the pulse transfer circuit.

[0006] Furthermore, the clock circuit includes a 555 timer U1 and a resistor R5, the RST pin of the 555 timer U1 is connected to a resistor R2 and a capacitor C3 for delayed output, the THRS pin and the TRIG pin of the 555 timer U1 are connected in parallel and then connected to a capacitor C4, the DIS pin of the 555 timer U1 is connected to a resistor R6, the resistor R6 is connected to the capacitor C4, the resistor R5 is connected to an external 5V power supply, and the resistor R5 is connected to the capacitor C4.

[0007] Furthermore, the pulse transfer circuit includes a D flip-flop U3A and a D flip-flop U4A, which are cascaded, and the OUT pin of the 555 timer U1 is connected to the CLK pin of the D flip-flop U3A and the CLK pin of the D flip-flop U4A respectively, and the pin 15 of the D flip-flop U3A is connected to the pin 3 of the D flip-flop U4A, and the pin 3 of the D flip-flop U3A is connected to the output pin 4 of the NOR gate U2B.

[0008] Furthermore, the detection light is an LED light, the D trigger U3A is connected to several LED lights and then connected to the connector J1, the D trigger U4A is connected to several LED lights and then connected to the connector J2, and the connector J3 is connected to several LED lights and then grounded.

[0009] Furthermore, the pulse generating circuit further includes a NOR gate U2D, and the input end of the NOR gate U2D is grounded.

[0010] Furthermore, the RC delay circuit includes a resistor R1 and a capacitor C1 connected in parallel, and both ends of the parallel resistor R1 and the capacitor C1 are connected to the test button S1 and the input pin 3 of the NOR gate U2A respectively.

[0011] Furthermore, the connector J1 and the connector J2 are quick-connect male connectors, and the connector J3 is a quick-connect female connector.

[0012] Compared with the prior art, the beneficial effects of the present invention are:

[0013] 1. Quickly connect cables or flat cables through the quick-connect male and quick-connect female connectors for easy connection.

[0014] 2. The purpose of detecting multi-core cables can be achieved through clock circuits, pulse generating circuits and pulse transmitting circuits.

[0015] 3. Through the combination of buttons and indicator lights, the conductivity of the cable can be tested conveniently and reliably, greatly improving labor productivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a front view of the structural diagram of the utility model;

[0017] Figure 2 It is a side view of the structural diagram of the utility model;

[0018] Figure 3 This is a circuit schematic diagram of the clock circuit, pulse generating circuit and pulse transmitting circuit of the utility model;

[0019] Figure 4 This is a circuit diagram of the connector J3 of the present utility model;

[0020] Figure 5 This is a circuit diagram of the NOR gate U2D of the present utility model;

[0021] Figure 6 This is a wiring diagram of the connector J1, connector J2 and connector J3 of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described below with reference to the accompanying drawings.

[0023] like Figure 1 – Figure 5 As shown, embodiment 1, a cable rapid detection device, includes a shell, a detection controller is provided in the shell, and a plurality of detection lights, a power light and a test button S1 are respectively provided on the shell. The detection controller is connected to the connector J1, the connector J2 and the connector J3 through the plurality of detection lights. The detection controller includes a clock circuit, a pulse generating circuit and a pulse transfer circuit. The pulse generating circuit includes a NOR gate U2A and a NOR gate U2B. The input pin 3 of the NOR gate U2A is connected to the test button S1 through an RC delay circuit. The output pin 1 of the NOR gate U2A is connected in series with a resistor R3 and a capacitor C2 and then connected to the input pin 5 of the NOR gate U2B. The input pin 5 of the NOR gate U2B is also connected to a pull-up resistor R4. The input pin 2 of the NOR gate U2A is respectively connected to the output pin 4 of the NOR gate U2B and the input pin 9 of the NOR gate U2C. The output pin 10 of the NOR gate U2C is connected in series with a resistor R7 and a capacitor C3 and then connected to the clock circuit. The clock circuit and the input pin 9 of the NOR gate U2C are respectively connected to the pulse transfer circuit.

[0024] The clock circuit comprises a 555 timer U1 and a resistor R5, the RST pin of the 555 timer U1 is connected with the resistor R2 and the capacitor C3 to delay the output, the THRS pin and the TRIG pin of the 555 timer U1 are connected in parallel and then connected with the capacitor C4, the DIS pin of the 555 timer U1 is connected with the resistor R6, the resistor R6 is connected with the capacitor C4, the resistor R5 is connected with an external 5V power supply, and the resistor R5 is connected with the capacitor C4; the pulse transmission circuit comprises a D flip-flop U3A and a D flip-flop U4A, the D flip-flop U3A and the D flip-flop U4A are cascaded, the OUT pin of the 555 timer U1 is connected with the CLK pin of the D flip-flop U3A and the CLK pin of the D flip-flop U4A respectively, the pin 15 of the D flip-flop U3A is connected with the pin 3 of the D flip-flop U4A, and the pin 3 of the D flip-flop U3A is connected with the output pin 4 of the NOR gate U2B; the detection lamp is an LED lamp, the D flip-flop U3A is connected with a plurality of LED lamps and then connected with the connector J1, the D flip-flop U4A is connected with a plurality of LED lamps and then connected with the connector J2, and the connector J3 is connected with a plurality of LED lamps and then grounded; the pulse generation circuit further comprises an idle NOR gate U2D, and the input end of the NOR gate U2D is grounded; the RC delay circuit comprises a resistor R1 and a capacitor C1 connected in parallel, and the resistor R1 and the capacitor C1 are connected with the test button S1 and the input pin 3 of the NOR gate U2A respectively; the connector J1 and the connector J2 are male quick connectors, the connector J3 is a female quick connector, the whole machine is powered by a 5V direct current, and the rest is the same as in embodiment 1.

[0025] The clock circuit does not need an external trigger signal, and the power supply charges the capacitor C4 through the resistor R5 and the resistor R6, and the capacitor C4 discharges to the discharge end through the resistor R6, so that the circuit generates oscillation. The low-level reset end (RST) is connected with the NOR gate U2C, the resistor R2 and the capacitor C3 to delay the output, so that the clock waveform of the 555 timer U1 reaches the rising edge during the single pulse duration after the reset. One period of the clock pulse is the single LED lamp lighting maintenance time, and the LED lamp lighting maintenance time can be adjusted by setting different clock pulse periods, that is, the speed of the detection speed is adjusted.

[0026] The NOR gate uses a 74LS02 integrated circuit, comprising four independent two-input NOR gates. Two of these NOR gates function as monostable trigger circuits, one NOR gate, U2C, provides a reset signal to the 555 timer, U1, and the input of the unused NOR gate, U2D, is grounded. When test button S1 is pressed, pin 3 of NOR gate U2A inputs a high level, while pin 1 outputs a low level. This low level then reaches pin 5 of NOR gate U2B. With both pins 5 and 6 low, pin 4 of NOR gate U2B outputs a high level. The duration of this high level is determined by a delay circuit formed by resistor R4 and capacitor C2. When capacitor C2 is fully charged, pin 5 of NOR gate U2B returns to a high state, the circuit outputs a low level, and the LED connected to the corresponding cable turns off.

[0027] The output of the pulse generation circuit is connected to the first-stage D-type flip-flop, U3A. The output of the preceding D-type flip-flop is then connected to the input of the subsequent D-type flip-flop. With each clock pulse, the circuit shifts and outputs a single pulse signal. The D-type flip-flop uses a 74LS174 chip, which integrates six D-type flip-flops. By cascading two 74LS174 chips, up to 12 shifted outputs can be achieved.

[0028] Wiring of cables or flat cables, etc. Figure 6 As shown in the figure, the circuit operates as follows: After power is applied, the 555 timer U1 begins operating in a multivibrator mode, with its out pin continuously outputting a square wave with a duty cycle of approximately 50%. This square wave signal is fed into the CLK pin of a multi-stage parallel D-type flip-flop. At this point, the D-type flip-flops have no high-level inputs, and their outputs are all low, turning off all LEDs. When the test button S1 is pressed, the pulse generator circuit generates a high-level pulse for approximately 720ms. This pulse is fed into the 1D pin of the first-stage D-type flip-flop U3A. The D-type flip-flop then begins transmitting pulses, sequentially outputting high-level signals that illuminate diodes D1-D10. This high-level signal then flows through resistors to the various ports on the quick-connect male connector J1. A multi-core cable is connected between the quick-connect male and female connectors. If all lines of the multi-core cable are conductive, diodes D11-D20 also conduct and illuminate in sequence. If one line of a multi-core cable is disconnected, the corresponding LED light will not light up; if the line number of the multi-core cable is incorrect, the order in which the diodes light up will be incorrect. Through this principle, the purpose of detecting multi-core cables is achieved.

Claims

1. A cable rapid detection device, comprising a housing, a detection controller disposed within the housing, and a plurality of detection lights and a test button S1 disposed on the housing. The detection controller is connected to connectors J1, J2, and J3 via the detection lights, and is characterized in that: The detection controller includes a clock circuit, a pulse generating circuit and a pulse transfer circuit. The pulse generating circuit includes a NOR gate U2A and a NOR gate U2B. Pin 3 of the NOR gate U2A is connected to the test button S1 through an RC delay circuit. Pin 1 of the NOR gate U2A is connected in series with a resistor R3 and a capacitor C2 and then connected to pin 5 of the NOR gate U2B. Pin 2 of the NOR gate U2A is respectively connected to pin 4 of the NOR gate U2B and pin 9 of the NOR gate U2C. Pin 10 of the NOR gate U2C is connected in series with a resistor R7 and a capacitor C3 and then connected to the clock circuit. The clock circuit and pin 9 of the NOR gate U2C are respectively connected to the pulse transfer circuit.

2. The cable rapid detection device according to claim 1, characterized in that: The clock circuit includes a 555 timer U1 and a resistor R5. The RST pin of the 555 timer U1 is connected to a resistor R2 and a capacitor C3. The THRS pin and the TRIG pin of the 555 timer U1 are connected in parallel and then connected to a capacitor C4. The DIS pin of the 555 timer U1 is connected to a resistor R6, which is connected to a capacitor C4. The resistor R5 is connected to an external 5V power supply, and the resistor R5 is connected to a capacitor C4.

3. The cable rapid detection device according to claim 2, characterized in that: The pulse transfer circuit includes a D flip-flop U3A and a D flip-flop U4A. The OUT pin of the 555 timer U1 is connected to the CLK pin of the D flip-flop U3A and the CLK pin of the D flip-flop U4A respectively. Pin 15 of the D flip-flop U3A is connected to pin 3 of the D flip-flop U4A. Pin 3 of the D flip-flop U3A is connected to pin 4 of the NOR gate U2B.

4. The cable rapid detection device according to claim 3, characterized in that: The detection light is an LED light. The D trigger U3A is connected to several LED lights and then connected to the connector J1. The D trigger U4A is connected to several LED lights and then connected to the connector J2. The connector J3 is connected to several LED lights and then grounded.

5. The cable rapid detection device according to claim 1, characterized in that: The pulse generating circuit further includes a NOR gate U2D, and the input end of the NOR gate U2D is grounded.

6. The cable rapid detection device according to claim 1, characterized in that: The RC delay circuit includes a resistor R1 and a capacitor C1 connected in parallel, and the two ends of the parallel resistor R1 and the capacitor C1 are connected to the test button S1 and the pin 3 of the NOR gate U2A respectively.

7. The cable rapid detection device according to claim 1, characterized in that: The connector J1 and the connector J2 are quick-connect male connectors, and the connector J3 is a quick-connect female connector.

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