Video signal device for providing multiple EDID data

Abstract

The utility model relates to a video signal device for providing multiple EDID data. Comprising an EDID storage circuit, an EDID switching circuit, an EDID forbidding circuit and a write protection switching circuit. The multi-EDID display device has a multi-EDID data storage and switching function, so that a user can select different display modes. The EDID forbidding circuit ensures that the display card can normally read EDID data when the HPD is lowered and recovered to a high level. And the write protection function of the EDID memory can be controlled.

Description

Technical Field

[0001] The utility model relates to the field of multi-EDID data storage and switching of DVI / HDMI signals, in particular to a DVI / HDMI video signal device that can provide multi-EDID data functions. Background Art

[0002] In special applications such as medical imaging and industrial applications, a display needs to display multiple display signals simultaneously and frequently switch between multiple display signals. However, existing ordinary displays can only provide a single EDID data per video interface and cannot meet the needs of multiple EDID data. Utility Model Content

[0003] In response to the deficiencies of the prior art, the present invention provides a video signal device that can provide multiple EDID data functions. This system can store different EDID information through multiple memories in the EDID storage circuit. This is because the graphics card uses "A0" as the communication address when reading EDID information. The device addresses of multiple memories are controlled by the EDID switching circuit to ensure that only one memory address is "A0" in the same state, thereby achieving multiple EDID information switching. The EDID disabling circuit ensures that when the HPD is at a low level, all storage addresses are not "A0", so as to avoid the graphics card mistakenly believing that the display connection status has not changed when the HPD is at a low level and not re-reading the EDID. A write protection switching circuit is used to control the write protection status of all memories to prevent data from being accidentally erased or modified.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: a video signal device providing multiple EDID data, comprising: an EDID storage circuit, an EDID switching circuit, an EDID disabling circuit, and a write protection switching circuit;

[0005] The IIC bus interface of the EDID storage circuit is connected to the computer graphics card, the address pin is connected to the control output end of the EDID switching circuit, and the write protection end WP of the EDID storage circuit is connected to the write protection switching circuit;

[0006] The control output end of the EDID switching circuit is connected to the EDID disabling circuit, and the EDID disabling circuit is connected to the display.

[0007] The EDID storage circuit includes a first EEPROM storage chip, a second EEPROM storage chip, and a third EEPROM storage chip;

[0008] The write protection terminals WP of the three EEPROM memory chips are all connected to the EDID_WP terminal of the write protection switching circuit, and the IIC bus interfaces DDCSCL and DDCSDA of the three EEPROM memory chips are connected to the computer graphics card; the address pins A2 of the three EEPROM memory chips are grounded;

[0009] The address pin A0 and the address pin A1 of the first EEPROM storage chip are connected to the control output terminal EDID_SEL0_N and the control output terminal EDID_SEL1_N of the EDID switching circuit respectively;

[0010] The address pin A0 and the address pin A1 of the second EEPROM storage chip are respectively connected to the control output terminal EDID_SEL0 and the control output terminal EDID_SEL1_N of the EDID switching circuit;

[0011] The address pin A0 and the address pin A1 of the third EEPROM storage chip are connected to the control output terminal EDID_SEL0_N and the control output terminal EDID_SEL1 of the EDID switching circuit respectively.

[0012] The EDID switching circuit includes a two-position dial switch SW1, and a first EDID switching unit and a second EDID switching unit connected thereto; the first EDID switching unit and the second EDID switching unit have the same structure, specifically as follows:

[0013] The source of the NMOS transistor Q2 is connected to the power supply through the resistor R1, and the gate is connected to the power supply through the resistor R7 and the resistor R4 in sequence. The gate is connected to the two-position DIP switch SW1 after passing through the resistor R7;

[0014] The source of the NMOS transistor Q2 of the first EDID switching unit serves as the control output terminal EDID_SEL1_N of the EDID switching circuit;

[0015] The source of the NMOS transistor Q2 of the second EDID switching unit serves as the control output terminal EDID_SEL0_N of the EDID switching circuit;

[0016] The first EDID switching unit and the second EDID switching unit are respectively connected to the first input terminal and the second input terminal of the two-position dial switch SW1;

[0017] The first input terminal and the second input terminal of the two-position dial switch SW1 serve as the control output terminal EDID_SEL1 and the control output terminal EDID_SEL0 of the EDID switching circuit respectively; the first output terminal and the second output terminal of the two-position dial switch SW1 are grounded.

[0018] The EDID disabling circuit includes a triode, a transistor and multiple resistors, and has the following structure:

[0019] The collector of the transistor Q1 and the collector of the transistor Q4 are connected to the control output terminal EDID_SEL0 and the control output terminal EDID_SEL1 of the EDID switching circuit respectively; the emitter of the transistor Q1 and the emitter of the transistor Q4 are grounded;

[0020] The base of transistor Q1 is connected to the power supply through resistor R6 and resistor R3 in sequence; the base of transistor Q4 is connected to the power supply through resistor R12 and resistor R3 in sequence;

[0021] The source of transistor Q5 is connected to the power supply through resistor R3 and the drain is grounded; the gate is connected to the power supply through resistor R13 and resistor R11 in sequence; the node of resistor R11 and resistor R13 is connected to the HotPlug control port of the display and is also grounded through button SW2.

[0022] The EDID write protection switching circuit includes a switch SW3 and a resistor R14;

[0023] One end of the switch SW3 serves as the EDID_WP end of the EDID write protection switching circuit and is connected to the power supply via the resistor R14; the other end of the switch SW3 is grounded.

[0024] The utility model has the following beneficial effects and advantages:

[0025] 1. This utility model uses an EEPROM chip to store multiple EDID information, which can provide the EDID information required for different display modes.

[0026] 2. This utility model uses an EDID switching circuit that takes advantage of the graphics card's ability to read EDID information using the "A0" device address. By switching the EEPROM chip's device address, it can switch between multiple EDID information. This can simplify circuit design and switching circuit costs.

[0027] 3. The present invention adopts an EDID disable circuit, which can prevent the graphics card from obtaining the display connection status through the "A0" address when the HPD signal is at a low level.

[0028] 4. The utility model adopts a write protection switching circuit, which can realize the write protection switching of the EEPROM chip, avoiding the risk of data being accidentally deleted or modified during normal use by the user. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the hardware connection structure of the utility model;

[0030] Figure 2This is a circuit diagram of a utility model EDID storage circuit;

[0031] Figure 3 This is a circuit diagram of a utility model EDID switching circuit;

[0032] Figure 4 This is a utility model EDID disable circuit diagram;

[0033] Figure 5 The utility model is a circuit diagram of an EDID write protection switching circuit. DETAILED DESCRIPTION

[0034] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0035] The utility model includes an EDID storage circuit 1, an EDID switching circuit 2, an EDID disable circuit 3, and a write-protect switching circuit 4. It has the function of storing and switching multiple EDID data, allowing users to select different display modes. The EDID disable circuit ensures that the graphics card can read EDID data normally when the HPD is pulled low and restored to a high level. It can also control the write protection function of the EDID memory.

[0036] The IIC bus DDCSCL / DDCSDA of the EDID storage circuit 1 is connected to an external computer to provide EDID information to the graphics card. The address control terminal is respectively connected to the control output terminals EDID_SEL0 / EDID_SEL1 / EDID_SEL0_N / EDID_SEL1_N of the EDID switching circuit 2. The switch SW1 of the EDID switching circuit 2 controls the status of its four output terminals. The HPD port of the EDID disable circuit 3 is connected to the HotPlug control port of the display. The output terminals EDID_SEL0 / EDID_SEL1 of the EDID disable circuit 3 are respectively connected to the corresponding ports of the EDID switching circuit. The EDID_WP terminal of the write protection switching circuit 4 is connected to the corresponding port of the EDID storage circuit 1.

[0037] By increasing the number of address bits and the number of EDID switching circuit components, it can be expanded to a maximum of 7 EDID information. A 5V power supply is used to power each circuit.

[0038] EDID storage circuit 1 uses multiple EEPROM memory chips and several resistors. EDID switching circuit 2 uses N-MOSFET transistors and several resistors. EDID disable circuit 3 uses an N-MOSFET, two NPN transistors, a control switch SW2, and several resistors. Write-protect switching circuit 4 includes a control switch SW3 and several resistors.

[0039] like Figure 1Shown is a hardware connection structure diagram of the present utility model.

[0040] The device includes an EDID storage circuit 1, an EDID switching circuit 2, an EDID disabling circuit 3, a write protection switching circuit 4 and other parts.

[0041] 1. EDID storage circuit part 1: such as Figure 2 As shown, three 24C02 EEPROM memory chips are used. The SCL and SDA pins of all memory chips are connected together and then connected to the corresponding pins of the DVI or HDMI connector via the DDCSCL / DDCSDA ports, establishing a communication channel between the memory chips and the graphics card. The A0 / A1 / A2 pins of the memory are device address configuration pins. When all three pins are low, the device address is "A0." The A2 address pin of all memory chips is grounded. The A0 / A1 address pins of EEPROM1 are connected to the EDID_SEL0_N and EDID_SEL1_N pins of the EDID switch circuit, respectively. The A0 / A1 address pins of EEPROM2 are connected to the EDID_SEL0 and EDID_SEL1_N pins of the EDID switch circuit, respectively. The A0 / A1 address pins of EEPROM3 are connected to the EDID_SEL0_N and EDID_SEL1 pins of the EDID switch circuit, respectively. The WP pins of all memory chips are connected together and connected to the EDID_WP port of the write-protect switch circuit. The corresponding relationship between various addresses and valid EEPROM is shown in Table 1. Note: L-level, H-high level, address A0 is valid.

[0042] Table 1

[0043] Signal port EEPROM1 A0 EEPROM2 A0 EEPROM3 A0 All memory addresses are not A0 EDID_SEL0 H L H L EDID_SEL1 H H L L EDID_SEL0_N L H L H EDID_SEL1_N L L H H

[0044] 2. EDID switching circuit 2 parts: such as Figure 3 As shown, by adjusting the SW1 dual-position DIP switch, the user controls the on / off states of NMOS transistors Q2 and Q3, thereby controlling the states of EDID_SEL0 / EDID_SEL1 / EDID_SEL0_N / EDID_SEL1_N. R2 / R5 / R1 / R4 act as pull-up resistors to provide high-level power to these four signals. R7 / R9 limit the gate current of Q2 / Q3, respectively, thus achieving EDID switching.

[0045] 3. EDID disable circuit section 3: After adjusting SW1, the user can pull the HPD signal low by pressing SW2. Releasing SW2 triggers the graphics card to interpret the monitor's connection status as changed and re-read the EDID. Some graphics cards send commands to address "A0" while the HPD signal is low, and determine the monitor's connection status based on whether or not a response signal is received. If a response signal is received, the graphics card assumes the monitor is connected and does not read the EDID information, preventing the display mode switch (graphics card EDID switching) function.

[0046] To solve this problem, an EDID disable circuit is designed. Figure 4 As shown in the figure, when the button SW2 is on, the gate of Q5 is low, the NMOS transistor Q5 is off, and the D pole is high. Then, the transistors Q1 and Q4 are turned on at the same time, pulling EDID_SEL0 / EDID_SEL1 low, EDID_SEL0_N / EDID_SEL1_N high, and all memory addresses are not "A0". At this time, the graphics card cannot obtain the response signal, so the graphics card does not mistakenly believe that the monitor is not disconnected, thus avoiding problems. When SW2 is in the port state, Q5 is on, the D pole is high, and Q1 / Q4 are in the on state, which does not affect the state of EDID_SEL0 / EDID_SEL1. This circuit does not affect the normal operation of the EDID switching circuit.

[0047] 4. EDID write protection switching circuit part, such as Figure 5 As shown, switch SW3 is used to switch the memory chip's write-protect status. R14 is a pull-up resistor, providing a high-level pull-up for the write-protect pin. When SW3 is disconnected, the EDID_WP signal is high, and the memory is write-protected, preventing accidental data deletion or modification. When SW3 is connected, the EDID_WP signal is low, and the memory is not write-protected. At this time, all memory data can be modified.

[0048] By increasing the number of address bits and the number of EDID switching circuit components, it can be expanded to a maximum of 7 EDID information.

[0049] The utility model can realize the following functions and features: can provide up to 7 sets of EDID information; multiple sets of EDID storage function; can realize switching between multiple sets of EDID data; avoid misjudgment of display status by graphics card; have write protection switching function to avoid data loss during normal use.

Claims

1. A video signal device providing multiple EDID data, characterized in that: include: EDID storage circuit (1), EDID switching circuit (2), EDID disabling circuit (3), write protection switching circuit (4); The IIC bus interface of the EDID storage circuit (1) is connected to a computer graphics card, the address pin is connected to a control output end of the EDID switching circuit (2), and the write protection end WP of the EDID storage circuit (1) is connected to a write protection switching circuit (4); The control output end of the EDID switching circuit (2) is connected to the EDID disabling circuit (3), and the EDID disabling circuit (3) is connected to the display.

2. The video signal device for providing multiple EDID data according to claim 1, wherein: The EDID storage circuit includes a first EEPROM storage chip, a second EEPROM storage chip, and a third EEPROM storage chip; The write protection terminals WP of the three EEPROM memory chips are all connected to the EDID_WP terminal of the write protection switching circuit, and the IIC bus interfaces DDCSCL and DDCSDA of the three EEPROM memory chips are connected to the computer graphics card; the address pins A2 of the three EEPROM memory chips are grounded; The address pin A0 and the address pin A1 of the first EEPROM storage chip are connected to the control output terminal EDID_SEL0_N and the control output terminal EDID_SEL1_N of the EDID switching circuit respectively; The address pin A0 and the address pin A1 of the second EEPROM storage chip are respectively connected to the control output terminal EDID_SEL0 and the control output terminal EDID_SEL1_N of the EDID switching circuit; The address pin A0 and the address pin A1 of the third EEPROM storage chip are connected to the control output terminal EDID_SEL0_N and the control output terminal EDID_SEL1 of the EDID switching circuit respectively.

3. The video signal device for providing multiple EDID data according to claim 1, wherein: The EDID switching circuit includes a two-position dial switch SW1, and a first EDID switching unit and a second EDID switching unit connected thereto; the first EDID switching unit and the second EDID switching unit have the same structure, specifically as follows: The source of the NMOS transistor Q2 is connected to the power supply through the resistor R1, and the gate is connected to the power supply through the resistor R7 and the resistor R4 in sequence. The gate is connected to the two-position DIP switch SW1 after passing through the resistor R7; The source of the NMOS transistor Q2 of the first EDID switching unit serves as the control output terminal EDID_SEL1_N of the EDID switching circuit; The source of the NMOS transistor Q2 of the second EDID switching unit serves as the control output terminal EDID_SEL0_N of the EDID switching circuit; The first EDID switching unit and the second EDID switching unit are respectively connected to the first input terminal and the second input terminal of the two-position dial switch SW1; The first input terminal and the second input terminal of the two-position dial switch SW1 serve as the control output terminal EDID_SEL1 and the control output terminal EDID_SEL0 of the EDID switching circuit respectively; the first output terminal and the second output terminal of the two-position dial switch SW1 are grounded.

4. The video signal device for providing multiple EDID data according to claim 1, wherein: The EDID disabling circuit includes a triode, a transistor and multiple resistors, and has the following structure: The collector of the transistor Q1 and the collector of the transistor Q4 are connected to the control output terminal EDID_SEL0 and the control output terminal EDID_SEL1 of the EDID switching circuit respectively; the emitter of the transistor Q1 and the emitter of the transistor Q4 are grounded; The base of transistor Q1 is connected to the power supply through resistor R6 and resistor R3 in sequence; the base of transistor Q4 is connected to the power supply through resistor R12 and resistor R3 in sequence; The source of transistor Q5 is connected to the power supply via resistor R3, and the drain is grounded; the gate is connected to the power supply via resistors R13 and R11 in sequence; the node between resistors R11 and R13 is connected to the Hot Plug control port of the display and is also grounded via button SW2.

5. The video signal device for providing multiple EDID data according to claim 1, wherein: The write protection switching circuit includes a switch SW3 and a resistor R14; One end of the switch SW3 serves as the EDID_WP end of the write protection switching circuit and is connected to the power supply via the resistor R14; the other end of the switch SW3 is grounded.

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