Semiconductor device

Abstract

The utility model discloses a semiconductor device which comprises a substrate, a bit line structure, a gate electrode structure, an etching stop layer and an interlayer dielectric layer. The substrate includes a first region and a second region. The bit line structure is disposed on the substrate and located in the first region. The gate structure is disposed on the substrate and located in the second region. An etch stop layer is disposed on the substrate covering a top surface and sidewalls of the bit line structure and sidewalls of the gate structure. An interlayer dielectric layer overlies the bit line structure and the gate structure, where the interlayer dielectric layer physically contacts the etch stop layer overlying the top surface of the bit line structure and the top surface of the gate structure. Therefore, both the bit line structure and the gate structure can have better structural reliability, so that the semiconductor device can achieve more optimized component efficiency.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor device, especially a semiconductor memory device. BACKGROUND

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor memory devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, so it has gradually replaced the dynamic random access memory with only a planar gate structure. Generally, the dynamic random access memory with a recessed gate structure is formed by a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from the word line (WL) and the bit line (BL). In response to product demand, the density of memory cells in the array area must continue to increase, causing the difficulty and complexity of related manufacturing processes and design to increase. Therefore, the prior art still needs to be further improved to effectively improve the performance and reliability of related storage devices. SUMMARY

[0003] One purpose of the utility model is to provide a semiconductor device, which is provided with etching stop layers with different coverage degrees in different regions, and / or the thickness of the cap layer in a specific region is thinned synchronously in the implementation of a specific process (such as a planarization process or an etch-back process), the component height difference of the semiconductor device in different regions is reduced, the structural reliability of the semiconductor device is improved, so that the semiconductor device can achieve more optimized component performance and operation performance.

[0004] To achieve the above purpose, one embodiment of the utility model provides a semiconductor device, which comprises a substrate, a bit line structure, a gate structure, an etching stop layer and an interlayer dielectric layer. The substrate comprises a first region and a second region. The bit line structure is arranged on the substrate and located in the first region. The gate structure is arranged on the substrate and located in the second region. The etching stop layer is arranged on the substrate and covers the top surface and the sidewall of the bit line structure and the sidewall of the gate structure. The interlayer dielectric layer covers the bit line structure and the gate structure, wherein the interlayer dielectric layer physically contacts the etching stop layer covering the top surface of the bit line structure and the top surface of the gate structure. BRIEF DESCRIPTION OF DRAWINGS

[0005] The accompanying drawings are included to provide a further understanding of principles of embodiments and are incorporated in and constitute a part of this specification. The drawings

[0006] Figures 1-2 Fig. 1 illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present application, wherein:

[0007] Figure 1 Fig. 2 illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present application, wherein:

[0008] Figure 2 Fig. 3 illustrates another cross-sectional view of a semiconductor device according to an embodiment of the present application, wherein:

[0009] Figures 3-10 Fig. 4 illustrates a flow chart of a method of fabricating a semiconductor device according to an embodiment of the present application, wherein:

[0010] Figure 3 Fig. 5 illustrates a cross-sectional view of a semiconductor device after forming a first semiconductor layer according to an embodiment of the present application, wherein:

[0011] Figure 4 Fig. 6 illustrates a cross-sectional view of a semiconductor device after forming a bit line opening according to an embodiment of the present application, wherein:

[0012] Figure 5 Fig. 7 illustrates a cross-sectional view of a semiconductor device after forming a second semiconductor layer according to an embodiment of the present application, wherein:

[0013] Figure 6 Fig. 8 illustrates a cross-sectional view of a semiconductor device after forming a cap material layer according to an embodiment of the present application, wherein:

[0014] Figure 7 Fig. 9 illustrates a cross-sectional view of a semiconductor device after forming an etch stop material layer according to an embodiment of the present application, wherein:

[0015] Figure 8 Fig. 10 illustrates a cross-sectional view of a semiconductor device after performing a planarization process according to an embodiment of the present application, wherein:

[0016] Figure 9 Fig. 11 illustrates a cross-sectional view of a semiconductor device after forming an etch stop layer according to an embodiment of the present application, wherein:

[0017] Figure 10 Fig. 12 illustrates a cross-sectional view of a semiconductor device after forming an interlayer dielectric layer according to an embodiment of the present application, wherein:

[0018] Figures 11-12 Fig. 13 illustrates a flow chart of a method of fabricating a semiconductor device according to another embodiment of the present application, wherein:

[0019] Figure 11A cross-sectional view of a semiconductor device after performing a back-etching process.

[0020] Figure 12 A cross-sectional view of a semiconductor device after forming an etch stop layer.

[0021] BRIEF DESCRIPTION OF DRAWINGS

[0022] 10 semiconductor device

[0023] 100 substrate

[0024] 100A first region

[0025] 100B second region

[0026] 102 shallow trench isolation

[0027] 104 doped region

[0028] 110 dielectric layer

[0029] 110t top surface

[0030] 112 oxide layer

[0031] 114 nitride layer

[0032] 116 oxide layer

[0033] 118 gate dielectric layer

[0034] 118t top surface

[0035] 120 bit line structure

[0036] 120s sidewall

[0037] 120t top surface

[0038] 122 first conductor layer

[0039] 122t top surface

[0040] 124 first cap layer

[0041] 126 semiconductor layer

[0042] 126t top surface

[0043] 128, 148 barrier layer

[0044] 130, 150 metal layer

[0045] 132 bit line plug

[0046] 140 gate structure

[0047] 140t top surface

[0048] 140s sidewall

[0049] 142 second conductor layer

[0050] 142t top surface

[0051] 144 Second Cover Layer

[0052] 146 top semiconductor layer

[0053] 146t top surface

[0054] 152 bottom semiconductor layer

[0055] 152t top surface

[0056] 160 bit line spacers

[0057] 160t top surface

[0058] 162, 172 spacer

[0059] 164, 174 gap wall

[0060] 180, 182, 184 Etch stop layer

[0061] 190, 192, 194 insulation layer

[0062] 196 interlayer dielectric layer

[0063] 200 buried gate structure

[0064] 202 dielectric layer

[0065] 204 gate dielectric layer

[0066] 206 gate

[0067] 208 cap layer

[0068] 210 Insulation Structure

[0069] 212, 214 plug

[0070] 216 Metal Wire

[0071] 218 gate dielectric material layer

[0072] 224 Covering material layer

[0073] 224t top surface

[0074] 226 second semiconductor material layer

[0075] 228 barrier material layer

[0076] 230 metal material layer

[0077] 252 first semiconductor material layer

[0078] 280 etch stop material layer

[0079] 290 insulating material layer

[0080] HM1, HM2, HM3 mask layer

[0081] OP opening

[0082] P1 first plane

[0083] P2 second plane

[0084] T1, T2, T3, T4 thickness DETAILED DESCRIPTION

[0085] In order to enable those skilled in the art to further understand the present application, the following preferred embodiments of the present application are listed, and the constitution and effects of the present application are described in detail with reference to the accompanying drawings. It should be understood that the following embodiments can be replaced, reorganized, mixed to complete other embodiments without departing from the spirit of the present application.

[0086] Please refer to Figures 1-2 , which is a cross-sectional schematic view of a semiconductor device 10 in a preferred embodiment of the present application. First, as shown in Figure 1 , the semiconductor device 10 includes a substrate 100, a bit line structure 120, a gate structure 140, an etch stop layer 180, and an interlayer dielectric layer 186. The substrate 100 is, for example, a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate, etc., and at least two regions are defined on the substrate 100, for example, a first region 100A (for example, as a storage region of the semiconductor device 10) with a relatively high component concentration and a second region 100B (for example, as a peripheral region of the semiconductor device 10) with a relatively low component concentration, wherein the second region 100B is, for example, disposed on one side of the first region 100A, as shown in Figure 1 , but is not limited thereto. In addition, at least one shallow trench isolation (STI) 102 is formed in the substrate 100 to define a plurality of active areas (AA) on the substrate 100.

[0087] The bit line structure 120 and the gate structure 140 are both disposed on the substrate 100, wherein the bit line structure 120 is located in the first region 100A and the gate structure 140 is located in the second region 100B. The etch stop layer 180 is also disposed on the substrate 100, wherein the etch stop layer 182 disposed in the first region 100A integrally covers the bit line structure 120 and the substrate 100, including covering the top surface 120t and the sidewall 120s of the bit line structure 120 at the same time, and the etch stop layer 184 disposed in the second region 100B covers the sidewall 140s of the gate structure 140 and the substrate 100. The interlayer dielectric layer 196 is further disposed on the etch stop layer 180 and integrally covers above the bit line structure 120 and the gate structure 140. It is noted that since the etch stop layer 184 disposed in the second region 100B does not cover the top surface 140t of the gate structure 140, the interlayer dielectric layer 196 physically contacts the top surface 140t of the gate structure 140 and physically contacts the etch stop layer 182 covering the top surface 120t of the bit line structure 120. In this way, the bit line structure 120 disposed in the first region 100A and the gate structure 140 disposed in the second region 100B can both have more improved structural reliability, so that the semiconductor device 10 can achieve more optimized component performance.

[0088] In one embodiment, the bit line structure 120 in detail comprises a first conductor layer 122 and a first cap layer 124 (e.g., comprising an insulating material such as silicon oxide, silicon nitride or silicon oxynitride) disposed in a stacked manner on the dielectric layer 110, while the first conductor layer 122 preferably comprises a composite layer structure, e.g., further comprising a semiconductor layer 126 (e.g., comprising a semiconductor material such as polysilicon), a barrier layer 128 (e.g., comprising a conductive barrier material such as titanium and / or titanium nitride) and a metal layer 130 (e.g., comprising a low-resistance metal material such as tungsten, aluminum or copper) disposed in a stacked manner on the top surface 110t of the dielectric layer 110 from bottom to top, but not limited thereto. Further, at least one bit line contact 132 (BLC) is disposed below the bit line structure 120. The bit line contact 132, for example, is formed through the dielectric layer 110, partially extends into the substrate 100 in the first region 100A and is disposed between two adjacent buried gate structures 200, so that the bit line structure 120 is electrically connected to an active region in the first region 100A through the bit line contact 132 disposed therebelow. Preferably, the semiconductor layer 126 in the first conductor layer 122 is, for example, integrally formed with the bit line contact 132 and comprises the same semiconductor material (e.g., comprising polysilicon), but not limited thereto. Further, the dielectric layer 110 preferably also has a composite layer structure, e.g., comprising an oxide-nitride-oxide (ONO) structure, but not limited thereto. In addition, the buried gate structure 200 is disposed in the substrate 100 below the dielectric layer 110 and in detail comprises a dielectric layer 202, a gate dielectric layer 204, a gate 206 and a cap layer 208 disposed in a stacked manner, but not limited thereto.

[0089] On the other hand, the gate structure 140 in detail includes a second conductor layer 142 and a second cap layer 144 (e.g., including an insulating material such as silicon oxide, silicon nitride or silicon oxynitride) disposed in sequence on the gate dielectric layer 118, while the second conductor layer 142 preferably includes a composite layer structure, e.g., further including a bottom semiconductor layer 152 (e.g., including a doped polysilicon, a doped amorphous silicon or the like semiconductor material) disposed in sequence on the top surface 118t of the gate dielectric layer 118, a top semiconductor layer 146 (e.g., including a doped polysilicon, a doped amorphous silicon or the like semiconductor material), a barrier layer 148 (e.g., including a conductive barrier material such as titanium and / or titanium nitride) and a metal layer 150 (e.g., including a low-resistance metal material such as tungsten, aluminum or copper) disposed in sequence on the top semiconductor layer 146. In one embodiment, the second cap layer 144 and the first cap layer 124 preferably include the same insulating material, the metal layer 150 in the second conductor layer 142 and the metal layer 130 in the first conductor layer 122 preferably include the same metal material, the barrier layer 148 in the second conductor layer 142 and the barrier layer 128 in the first conductor layer 122 preferably include the same conductive barrier material, the top semiconductor layer 146 in the second conductor layer 142 and the semiconductor layer 126 in the first conductor layer 122 preferably include the same semiconductor material, but the application is not limited thereto. In another embodiment, the gate dielectric layer 118 and the oxide layer 112 in the dielectric layer 110 preferably include the same material and thickness, but the application is not limited thereto.

[0090] It is noted that in the case that the disposition plane of the second conductor layer 142 (i.e., the top surface 118t of the gate dielectric layer 118) in the second region 100B is lower than the disposition plane of the first conductor layer 122 (i.e., the top surface 110t of the dielectric layer 110) in the first region 100A, the top surface 142t of the second conductor layer 142 is higher than the top surface 122t of the first conductor layer 122 due to the additional bottom semiconductor layer 152 included in the second conductor layer 142. Also, the top surface 126t of the semiconductor layer 126 in the first conductor layer 122 is preferably higher than the top surface 152t of the bottom semiconductor layer 152 in the second conductor layer 142, and lower than the top surface 146t of the top semiconductor layer 146 in the second conductor layer 142, while the thickness T2 of the top semiconductor layer 146 is preferably equal to the thickness T1 of the semiconductor layer 126 on the dielectric layer 110, but the application is not limited thereto. Furthermore, the top surface of the second cap layer 144 (i.e., the top surface 140t of the gate structure 140) is lower than the top surface of the first cap layer 124 (i.e., the top surface 120t of the bit line structure 120) due to the thickness T3 of the first cap layer 124 disposed above the first conductor layer 122 being greater than the thickness T4 of the second cap layer 144 disposed above the second conductor layer 142.

[0091] For example Figure 1As shown, the semiconductor device 10 further includes an insulating layer 190 disposed on the substrate 100, a bit line spacer 160 disposed on the sidewall 120s of the bit line structure 120, and a gate spacer 170 disposed on the sidewall 140s of the gate structure 140. The insulating layer 190 is, for example, positioned between the bit line structure 120 and the gate structure 140. Among them, the insulating layer 192 disposed in the first region 100A only covers the etching stop layer 182 on the bit line spacer 160, and has a first plane P1 flush with the etching stop layer 182 covering the top surface 120t of the bit line structure 120, while the insulating layer 194 disposed in the second region 100B completely covers the etching stop layer 184 disposed in the second region 100B, and has a second plane P2 flush with the etching stop layer 184 and the top surface 140t of the gate structure 140. That is, the insulating layer 192 disposed in the first region 100A and the insulating layer 194 disposed in the second region 100B have different heights of top surfaces, respectively, and the first plane P1 in the first region 100A is preferably higher than the second plane P2 in the second region 100B.

[0092] The bit line spacer 160 is, for example, disposed between the bit line structure 120 and the etching stop layer 182 disposed in the first region 100A, and in detail includes a spacer 162 (for example, including silicon nitride, silicon carbon nitride) and a spacer 164 (for example, including silicon oxide, silicon oxynitride) stacked in sequence on the sidewall 120s of the bit line structure 120, but not limited thereto. Among them, the etching stop layer 182 disposed in the first region 100A further integrally covers the bit line spacer 160 and can physically contact the top surface 160t of the bit line spacer 160. The gate spacer 170 is, for example, disposed between the gate structure 140 and the etching stop layer 184 disposed in the second region 100B, and in detail includes a spacer 172 (for example, including silicon nitride, silicon carbon nitride) and a spacer 174 (for example, including silicon oxide, silicon oxynitride) stacked in sequence on the sidewall 140s of the gate structure 140, but not limited thereto. In an embodiment, the spacer 162 of the bit line spacer 160 and the spacer 172 of the gate spacer 170 preferably include the same material and thickness, and the spacer 164 of the bit line spacer 160 and the spacer 174 of the gate spacer 170 also include the same material and thickness, but not limited thereto.

[0093] Under this configuration, the semiconductor device 10 of this embodiment can function as a dynamic random access memory (DRAM) device, with the buried gate structure 200 and the bitline structure 120 in the first region 100A serving as the buried wordline (WL) and bitline (BL) of the semiconductor device 10, respectively, to receive or transmit voltage signals from the substrate 100. According to the semiconductor device 10 of this embodiment, although the gate structure 140 in the second region 100B additionally includes a bottom semiconductor layer 152 and has a relatively high second conductive layer 142, a second capping layer 144 with a reduced thickness is provided on the second conductive layer 142, thereby ensuring that the top surface of the second capping layer 144 (i.e., the top surface 140t of the gate structure 140) is lower than the top surface of the first capping layer 124 (i.e., the top surface 120t of the bitline structure 120). Furthermore, the etch stop layer 184 disposed in the second region 100B does not cover the top surface of the second capping layer 144. In this way, the top surface 140t of the gate structure 140 disposed in the second region 100B can be correspondingly lower than the top surface 120t of the bit line structure 120 disposed in the first region 100A. The further disposed interlayer dielectric layer 196 physically contacts the top surface 140t of the gate structure 140, and the etching stop layer 182 covering the top surface 120t of the bit line structure 120. As a result, the bit line structure 120 and the gate structure 140 disposed in the first region 100A and the second region 100B, respectively, can both have more improved structural reliability, allowing the semiconductor device 10 to achieve more optimized operating performance.

[0094] In addition, the semiconductor device 10 of this embodiment may further be provided with plugs 212 and 214 electrically connected to the bit line structure 120 and the gate structure 140, and a metal wire 216 connecting the plugs 212 and 214. Figure 2 As shown, after forming the semiconductor device 10 shown in FIG. 1 , plugs 212 and 214 are further provided in the first region 100A and the second region 100B, respectively, and metal wires 216 are simultaneously provided in the first region 100A and the second region 100B. The plug 212 provided in the first region 100A penetrates the interlayer dielectric layer 196, the etch stop layer 182, and the first cap layer 124, and physically contacts the first conductive layer 122 of the bitline structure 120, thereby electrically connecting to the bitline structure 120. The plug 214 provided in the second region 100B penetrates the interlayer dielectric layer 196, the insulating layer 194, and the etch stop layer 184, and physically contacts the doped regions 104 provided on both sides of the gate structure 140, thereby electrically connecting to the gate structure 140.

[0095] It should be noted that the semiconductor device 10 is also provided with a plurality of insulating structures 210 that penetrate the metal wires 216 and the interlayer dielectric layer 196 and partially extend into the insulating layer 194, the second capping layer 144, or the etch stop layer 184 to segment the metal wires 216 disposed in the second region 100B into a plurality of segments. In this manner, the segments can be arranged alternately with the insulating structures 210 in the horizontal direction, thereby serving as metal lines electrically connected to different components. In one embodiment, the insulating structures 210 include an insulating material such as silicon nitride or silicon carbonitride, while the plugs 212, 214, and the metal wires 216 include a low-resistance metal material such as aluminum, titanium, copper, or tungsten, preferably including tungsten, but not limited thereto. Thus, the plugs 212, 214 and the metal wire 216 form a first-layer metal interconnection (M0 interconnection) electrically connected to the bit line structure 120 and the gate structure 140, respectively. In addition, the insulating structure 210 effectively isolates the metal wire 216 disposed above the gate structure 140, thereby avoiding problems such as short circuits, thereby further optimizing the operating performance of the semiconductor device 10 of this embodiment.

[0096] In order to enable a person skilled in the art to implement the semiconductor device 10 according to the aforementioned embodiment of the present invention, a method for manufacturing the semiconductor device 10 is further described below.

[0097] See also Figures 3-10 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device in a preferred embodiment of the present invention. Figure 3 As shown, a substrate 100 is provided, and shallow trench isolations 102 are formed in a first region 100A and a second region 100B of the substrate 100 to define active regions. In one embodiment, the shallow trench isolations 102 are formed by, for example, first etching a plurality of trenches (not shown) in the substrate 100, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride), but the present invention is not limited thereto. Next, a plurality of buried gate structures 200 are sequentially formed within the substrate 100 and a dielectric layer 110 covering the substrate 100 is sequentially formed within the first region 100A, and a gate dielectric material layer 218 is formed within the second region 100B. In one embodiment, the manufacturing method of the buried gate structure 200 includes but is not limited to the following steps, such as first forming a plurality of trenches (not shown) in the substrate 100 that can simultaneously pass through the active area and the shallow trench isolation 102, and then sequentially forming a dielectric layer 202 covering the entire surface of the trench, a gate dielectric layer 204 covering the surface of the lower half of the trench, a gate 206 filling the lower half of the trench, and a cap layer 208 filling the upper half of the trench in the trench, but the present invention is not limited thereto.

[0098] The dielectric layer 110 is formed, for example, to cover the surface of the substrate 100 in the first region 100A as a whole, and the gate dielectric material layer 218 is formed to cover the surface of the substrate 100 in the second region 100B as a whole. The gate dielectric material layer 218, for example, includes an insulating material such as silicon oxide or silicon oxynitride, and preferably includes the same insulating material and film thickness as the oxide layer 116 in the dielectric layer 110, but is not limited thereto. In an embodiment, the dielectric layer 110 and the gate dielectric material layer 218 are formed by, for example, the following steps: sequentially forming a first oxide material layer (not shown), a nitride material layer (not shown), and a second oxide material layer (not shown) to cover the first region 100A and the second region 100B as a whole on the substrate 100, and then removing the second oxide material layer and the nitride material layer covering the second region 100B, so that the first oxide material layer remaining in the second region 100B forms the gate dielectric material layer 218, and the first oxide material layer, the nitride material layer, and the second oxide material layer in the first region 100A simultaneously form the dielectric layer 110 as shown in Figure 3 for example, including the oxide layer 112, the nitride layer 114, and the oxide layer 116 stacked in sequence on the substrate 100, but is not limited thereto. Alternatively, the first oxide material layer, the nitride material layer, and the second oxide material layer covering the second region 100B can be removed completely, and then the gate dielectric material layer 218 is re-formed.

[0099] As shown in Figure 3 , a first semiconductor material layer 252 is formed on the top surface of the dielectric layer 110 in the first region 100A and on the top surface of the gate dielectric material layer 218 in the second region 100B. The first semiconductor material layer 252, for example, includes a semiconductor material such as polysilicon, doped amorphous silicon, or the like, but is not limited thereto. It should be noted that, since the gate dielectric material layer 218 is formed only on the substrate 100 in the second region 100B, the first semiconductor material layer 252 formed in the first region 100A and the second region 100B has top surfaces that are not flush with each other. Then, a mask layer HM1 is formed in the second region 100B to cover the first semiconductor material layer 252 formed in the second region 100B as a whole.

[0100] As shown in Figure 4 , the first semiconductor material layer 252 in the first region 100A is removed by, for example, etching, so that the first semiconductor material layer 252 in the first region 100A is removed completely, and the first semiconductor material layer 252 in the second region 100B is left as a whole. The first semiconductor material layer 252 in the second region 100B, for example, includes a semiconductor material such as polysilicon, doped amorphous silicon, or the like, but is not limited thereto. Then, as shown in Figure 3The mask layer HM1 shown is covered by an etching process to completely remove the first semiconductor material layer 252 formed in the first region 100A, and then the mask layer HM1 is completely removed. That is, after the etching process, only the first semiconductor material layer 252 formed on the gate dielectric material layer 218 remains. Then, another etching process is performed with the aid of another mask layer (not shown) to partially remove the dielectric layer 110 in the first region 100A and the substrate 100 thereunder, and to form an opening OP between two adjacent buried gate structures 200 that partially exposes the substrate 100, defining a region as shown in FIG. Figure 1 After the bit line plug 132 is formed, the other mask layer is completely removed.

[0101] like Figure 5 As shown, a second semiconductor material layer 226 is simultaneously formed on the first region 100A and the second region 100B, such that the second semiconductor material layer 226 formed in the first region 100A fills the opening OP and further covers the dielectric layer 110, and the second semiconductor material layer 226 formed in the second region 100B directly covers the first semiconductor material layer 252. The second semiconductor material layer 226 includes, for example, a semiconductor material such as doped polysilicon or doped amorphous silicon, and preferably includes the same semiconductor material as the first semiconductor material layer 252, but is not limited thereto. It should be noted that since the second semiconductor material layer 226 formed in the first region 100A and the second region 100B are located on the dielectric layer 110 and the first semiconductor material layer 252, respectively, the second semiconductor material layer 226 formed in the first region 100A and the second region 100B have top surfaces that are not flush with each other. In one embodiment, the second semiconductor material layer 226 formed on the dielectric layer 110 has a thickness T1, for example, and the second semiconductor material layer 226 formed on the first semiconductor material layer 252 has a thickness T2 and a relatively high top surface, and the thickness T1 is preferably equal to the thickness T2, but is not limited thereto.

[0102] like Figure 6As shown, a barrier material layer 228 (e.g., comprising a conductive barrier material such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal material layer 230 (e.g., comprising a low-resistance metal material such as tungsten, aluminum, or copper), and a capping material layer 224 (e.g., comprising an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride) are simultaneously formed in a stacked order from bottom to top on the first region 100A and the second region 100B, completely covering the second semiconductor material layer 226 within the first region 100A and the second region 100B. In one embodiment, the capping material layer 224 formed in the first region 100A and the second region 100B preferably has the same thickness T3, but this is not limiting. It should be noted that due to the additional formation of the first semiconductor material layer 252 within the second region 100B, the barrier material layer 228, the metal material layer 230, and the capping material layer 224 within the first region 100A and the second region 100B have uneven top surfaces.

[0103] like Figure 7 As shown, a patterning process is simultaneously performed on the capping material layer 224, the metal material layer 230, the barrier material layer 228, the second semiconductor material layer 226, the first semiconductor material layer 252 and the dielectric layer 110 thereunder in the first region 100A and the second region 100B. The semiconductor layer 126, the barrier layer 128, the metal layer 130 and the first capping layer 124 are stacked in sequence from bottom to top on the top surface 110t of the dielectric layer 110 in the first region 100A. At the same time, the gate dielectric layer 118, the bottom semiconductor layer 152, the top semiconductor layer 146, the barrier layer 148, the metal layer 150 and the capping material layer 224 are stacked in sequence from bottom to top in the second region 100B. Thus, the semiconductor layer 126, barrier layer 128, and metal layer 130 in the first region 100A collectively form the first conductive layer 122. The sequentially stacked first conductive layer 122 and first capping layer 124 collectively form the bitline structure 120. Furthermore, the semiconductor layer 126 filling the opening OP also simultaneously forms the bitline plug 132, which is integrally formed with the semiconductor layer 126 in the bitline structure 120. Meanwhile, the bottom semiconductor layer 152, top semiconductor layer 146, barrier layer 148, and metal layer 150 in the second region 100B collectively form the second conductive layer 142, and the capping material layer 224 covers the second conductive layer 142. Among them, the top surface 142t of the second conductive layer 142 in the second area 100B is higher than the top surface 122t of the first conductive layer 122 in the first area 100A, and the top surface 224t of the capping material layer 224 in the second area 100B is also higher than the top surface 124t of the first capping layer 124 in the first area 100A (i.e., the top surface 120t of the bit line structure 120).

[0104] Next, bitline spacers 160 are formed on the sidewalls 120s of the bitline structure 120 in the first region 100A, and gate spacers 170 are formed on the sidewalls of the second conductive layer 142 and the capping material layer 224 in the second region 100B. In one embodiment, a method for fabricating the bitline spacers 160 and the gate spacers 170 includes, but is not limited to, the following steps: for example, forming a first spacer material layer (e.g., comprising silicon nitride or silicon carbonitride) and a second spacer material layer (e.g., comprising silicon oxide or silicon oxynitride) entirely covering the bitline structure 120 in the first region 100A and the second conductive layer 142 and the capping material layer 224 in the second region 100B by the same process; performing an etch-back process on the first spacer material layer and the second spacer material layer, respectively; and forming sequentially stacked spacers 162 and 164 on the sidewalls 120s of the bitline structure 120 to form the bitline spacer 160. Simultaneously, forming spacers 172 and 174 on the sidewalls of the second conductive layer 142 and the capping material layer 224 to form the gate spacers 170. In this operation, the spacers 162 of the bit line spacers 160 and the spacers 172 of the gate spacers 170 preferably include the same material and thickness, and the spacers 164 of the bit line spacers 160 and the spacers 174 of the gate spacers 170 also include the same material and thickness, but not limited thereto.

[0105] For example Figure 7 As shown, an etch-stop material layer 280 and an insulating material layer 290 are simultaneously formed in the first region 100A and the second region 100B. The etch-stop material layer 280 and the insulating material layer 290 both completely cover the bitline structure 120 in the first region 100A, and the second conductive layer 142 and the capping material layer 224 in the second region 100B. It should be noted that due to the additional formation of the bottom semiconductor layer 152 in the second region 100B, the etch-stop material layer 280 formed in the first region 100A and the second region 100B has uneven top surfaces. The etch-stop material layer 280 formed in the second region 100B has a relatively higher top surface.

[0106] like Figure 8As shown, a planarization process is performed to partially remove the insulating material layer 290 formed in the first and second regions 100A, 100B, and partially remove the etch-stop material layer 280 formed in the second region 100B, exposing the top surface 224t of the capping material layer 244. It should be noted that due to the relatively high device density in the first region 100A, the planarization process uses the etch-stop material layer 280 formed in the first region 100A as a stop layer, thereby removing the relatively high but scattered etch-stop material layer 280 in the second region 100B. As a result, after the planarization process, the insulating material layer 290 in the first and second regions 100A, 100B, and the etch-stop material layer 280 formed in the first and second regions 100A, 100B have flush top surfaces.

[0107] like Figure 9 As shown, a mask layer HM2 is formed in the first region 100A, and an etch-back process is performed on the mask layer HM2 to partially remove the insulating material layer 290, the etch-stop material layer 280, the gate spacers 170, and the capping material layer 244 in the second region 100B. In the second region 100B, an insulating layer 194, an etch-stop layer 184, the gate spacers 170, and the second capping layer 144 are formed. The second capping layer 144 has a relatively small thickness T4. Thus, the second conductive layer 142 and the second capping layer 144, which are sequentially stacked on the gate dielectric layer 118, together form the gate structure 140. It should be noted that the insulating layer 194 formed in the second region 100B covers the etch-stop layer 184 and has a second plane P2 flush with the etch-stop layer 184 and the top surface 140t of the gate structure 140. On the other hand, after the etch-back process is performed, the etch-stop material layer 280 and the insulating material layer 290 in the first region 100A simultaneously form the insulating layer 192 and the etch-stop layer 182 .

[0108] Thus, the Figure 1The insulating layer 190 and the etch-stop layer 180 are shown in FIG. The insulating layer 190 includes an insulating layer 192 formed in the first region 100A and an insulating layer 194 formed in the second region 100B, while the etch-stop layer 180 includes an etch-stop layer 182 formed in the first region 100A and an etch-stop layer 184 formed in the second region 100B. The insulating layer 192 has a first plane P1 flush with the etch-stop layer 182 overlying the top surface 120 t of the bitline structure 120, and the insulating layer 194 has a second plane P2 flush with the etch-stop layer 184 and the top surface 140 t of the gate structure 140, with the first plane P1 being lower than the second plane P2. The etch stop layer 182 covers the substrate 100 in the first region 100A and the top surface 120 t and sidewalls 120 s of the bit line structure 120 . The etch stop layer 184 covers the substrate 100 in the second region 100B and the sidewalls 140 s of the gate structure 140 .

[0109] like Figure 10 As shown, the mask layer HM2 is removed, and then an interlayer dielectric material layer 296 is formed simultaneously in the first area 100A and the second area 100B, covering the top surfaces of the insulating layer 192 and the etch stop layer 182 in the first area 100A as a whole, and covering the top surfaces of the insulating layer 194, the etch stop layer 184, the gate spacers 170, and the gate structure 140 in the second area 100B. The interlayer dielectric material layer 296 formed in the first area 100A and the second area 100B has top surfaces flush with each other. Subsequently, by Figure 10 The interlayer dielectric material layer 296 shown in FIG. 1 is then subjected to an etch-back process to form a Figure 1 The interlayer dielectric layer 196 is shown. Thus, the manufacturing of the semiconductor device 10 in this embodiment is completed.

[0110] According to the manufacturing method of the semiconductor device 10 of the present embodiment, the bottom semiconductor layer 152 is additionally formed in the second region 100B, so that the second conductor layer 142 has a relatively high top surface 142t, and the cap material layer 244 above the second conductor layer 142 has a relatively high top surface 224t. Then, when the insulating layer 194 and the etching stop layer 184 are formed in the second region 100B, the thickness T3 of the cap material layer 244 is simultaneously thinned, and the second cap layer 144 having a relatively small thickness T4 is formed. Thus, the top surface 140t of the gate structure 140 formed in the second region 100B can be correspondingly lower than the top surface 120t of the bit line structure 120 formed in the first region 100A. The interlayer dielectric layer 196 formed subsequently physically contacts the top surface 140t of the gate structure 140 and the etching stop layer 182 covering the top surface 120t of the bit line structure 120, so that the bit line structure 120 and the gate structure 140 formed in the first region 100A and the second region 100B, respectively, can have improved structural reliability, and the semiconductor device 10 can have optimized operation performance.

[0111] Those skilled in the art to which the present application pertains should easily understand that, under the premise of meeting the actual product requirements, the manufacturing method of the semiconductor device of the present application can have other forms and is not limited to the foregoing. The following will further describe other embodiments or variations of the manufacturing method of the semiconductor device of the present application. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and the same parts will not be repeatedly described. In addition, the same components in the embodiments of the present application are denoted by the same reference numerals, so as to facilitate mutual comparison between the embodiments.

[0112] Please refer to Figures 11-12 , which is a schematic diagram of the manufacturing method of the semiconductor device 10 in another preferred embodiment of the present application. The manufacturing method of the semiconductor device 10 of the present embodiment is basically the same as that of the semiconductor device 10 in the foregoing embodiment, and the main difference is that, when the planarization process is performed, the etching stop material layer 280 formed in the second region 100B and arranged at a relatively high position is used as the stop layer. Figure 8

[0113] In detail, as shown in Figure 11 ​As shown, during the planarization process of this embodiment, the insulating material layer 290 in the second region 100B is first partially removed until it is flush with the etch-stop material layer 280 in the second region 100B. The insulating material layer 290 in the second region 100B is then further removed through over-etching with the polishing slurry to form a recessed top surface. Furthermore, the insulating material layer 290 in the first region 100A is removed until the etch-stop material layer 280 in the first region 100BA is exposed. In other words, the planarization process in this embodiment does not remove the etch-stop material layer 280 covering the top surface 244t of the capping material layer 244. As a result, after the planarization process, the insulating material layer 290 in the second region 100B has a recessed top surface, and the etch-stop material layers 280 formed in the first region 100A and the second region 100B have uneven top surfaces.

[0114] like Figure 12 As shown, a mask layer HM3 is formed in the first region 100A, and an etch-back process is performed on the mask layer HM2 to partially remove the insulating material layer 290, etch-stop material layer 280, gate spacers 170, and capping material layer 244 in the second region 100B. An insulating layer 194, etch-stop layer 184, gate spacers 170, and a second capping layer 144 are formed in the second region 100B. The second capping layer 144 has a relatively small thickness T4. Thus, the second conductive layer 142 and the second capping layer 144, stacked sequentially on the gate dielectric layer 118, together form the gate structure 140. The insulating layer 194 formed in the second region 100B also has a second plane P2 flush with the etch-stop layer 184 and the top surface 140t of the gate structure 140. On the other hand, after the etch-back process, the etch-stop material layer 280 and the insulating material layer 290 in the first region 100A simultaneously form the insulating layer 192 and the etch-stop layer 182 . The insulating layer 192 also has a first plane P1 lower than the second plane P2 .

[0115] Subsequently, as in the above embodiment Figure 10 As shown, after the interlayer dielectric material layer 296 is formed in the first area 100A and the second area 100B simultaneously, an etch-back process is performed to form the same Figure 1 The interlayer dielectric layer 196 is formed, and the fabrication of the semiconductor device 10 in this embodiment is completed.

[0116] Overall, the semiconductor device and the manufacturing method thereof of the utility model lend the etching stop layer of different covering degrees in different areas, and / or reduce the thickness of the cover layer in the specific area in the implementation of specific process (such as planarization process or etching back process etc.), reduce the component height difference of semiconductor device in different areas, improve the structural reliability of component. Thus, the component (such as memory cell etc.) formed subsequently can be formed on the relatively flat setting plane, effectively optimize the component performance and operation performance of semiconductor device.

[0117] The above is only preferred embodiment of the utility model, and is not used to limit the utility model, for the person skilled in the art, the utility model can have various changes and changes. Any modification, equivalent replacement, improvement etc. that is made within the spirit and principle of the utility model should be included in the protection scope of the utility model.

Claims

1. A semiconductor device, characterized in that: include: a substrate comprising a first region and a second region; a bit line structure disposed on the substrate and located in the first region; a gate structure, disposed on the substrate and located in the second region; an etch stop layer, disposed on the substrate, covering the top surface and sidewalls of the bit line structure and the sidewalls of the gate structure; as well as An interlayer dielectric layer covers the bit line structure and the gate structure, wherein the interlayer dielectric layer physically contacts the etching stop layer covering the top surface of the bit line structure and the top surface of the gate structure.

2. The semiconductor device according to claim 1, wherein Also includes: An insulating layer is disposed on the substrate and located between the bit line structure and the gate structure, wherein the insulating layer includes a first plane located in the first region and a second plane located in the second region, and the first plane is higher than the second plane.

3. The semiconductor device according to claim 1, wherein The bit line structure further includes a first conductor layer and a first cap layer which are sequentially arranged, and the gate structure further includes a second conductor layer and a second cap layer which are sequentially arranged.

4. The semiconductor device according to claim 3, wherein A top surface of the second conductor layer is higher than a top surface of the first conductor layer.

5. The semiconductor device according to claim 3, wherein A top surface of the second cover layer is lower than a top surface of the first cover layer.

6. The semiconductor device according to claim 3, wherein The first conductor layer includes a semiconductor layer, a barrier layer and a metal layer stacked in sequence, and the second conductor layer includes a bottom semiconductor layer, a top semiconductor layer, a barrier layer and a metal layer stacked in sequence, wherein the top surface of the semiconductor layer in the first conductor layer is higher than the top surface of the bottom semiconductor layer in the second conductor layer.

7. The semiconductor device according to claim 6, wherein: The thickness of the first cover layer is greater than the thickness of the second cover layer.

8. The semiconductor device according to claim 6, wherein Also includes: At least one bit line plug is disposed below the bit line structure and partially extends into the substrate, wherein the semiconductor layer in the first conductor layer and the at least one bit line plug are integrally formed.

9. The semiconductor device according to claim 1, wherein Also includes: A bit line spacer is provided on a bit line sidewall of the bit line structure and between the bit line structure and the etching stop layer covering the bit line structure; as well as The gate spacer is arranged on the sidewall of the bit line of the gate structure and is between the gate structure and the etching stop layer arranged on the sidewall of the gate structure.

10. The semiconductor device according to claim 9, wherein The etching stop layer covering the bit line structure physically contacts a top surface of the bit line spacer.

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