Current reference circuit

Abstract

The utility model discloses a current reference circuit which comprises a first current generating unit, a second current generating unit, a mirror image unit, a compensation unit and an output unit. The first current generation unit is used for generating first current in direct proportion to temperature; the second current generation unit is used for generating a second current inversely proportional to the temperature; the mirroring unit is used for mirroring the first current to generate mirroring current and mirroring the second current to generate mirroring current; the compensation unit is used for generating compensation current based on the mirror current of the first current and the mirror current of the second mirror current; the output unit is used for compensating the image current of the first current and the second current based on the compensation current to generate the reference current. According to the current reference circuit disclosed by the utility model, points are taken on a reference current curve for compensation, and curvature injection is carried out on the reference current at different temperature sections according to a multi-point interpolation thought, so that the temperature coefficient of the reference current is adjusted.

Description

TECHNICAL FIELD

[0001] The utility model belongs to integrated circuit technical field, concretely relates to a current reference circuit. BACKGROUND

[0002] The output current in the traditional circuit is often compensated by the zero temperature voltage generated by the band gap reference and the zero temperature drift current generated by the voltage to current circuit when the temperature coefficient needs to be compensated. However, the high order term of the temperature coefficient in this process will affect the temperature coefficient of the output current, and the temperature coefficient of the resistor determines the temperature coefficient of the output current because of the existence of the resistor in the voltage to current. In some application scenarios, the temperature coefficient of the output current generated by the traditional method cannot meet the required temperature coefficient.

[0003] The information disclosed in this BACKGROUND section is only for the purpose of increasing the understanding of the background of the present utility model and should not be regarded as an acknowledgment or any form of suggestion that it forms prior art of those skilled in the art. CONTENT OF THE UTILITY MODEL

[0004] The utility model aims at providing a current reference circuit which can compensate the output current at multiple points to meet the temperature coefficient requirement of the output current.

[0005] In order to achieve the above purpose, one embodiment of the utility model provides a current reference circuit, which comprises a first current generating unit, a second current generating unit, a mirror unit, a compensation unit and an output unit.

[0006] The first current generating unit is used to generate a first current proportional to temperature; the second current generating unit is used to generate a second current inversely proportional to temperature; the mirror unit is connected with the first current generating unit and the second current generating unit, and is used to mirror the first current to generate one or more corresponding mirror currents and mirror the second current to generate one or more corresponding mirror currents; the compensation unit is connected with the mirror unit, and is used to generate one or more compensation currents based on the mirror current of the first current and the mirror current of the second mirror current; the output unit is connected with the mirror unit and the compensation unit, and is used to compensate the mirror current of the first current and the second current based on the compensation current to generate a reference current.

[0007] In one or more embodiments of the utility model, the mirror unit is used to mirror the first current to generate a first mirror current and mirror the second current to generate a third proportional current; the compensation unit is used to generate a first compensation current based on the third proportional current and the first mirror current; the output unit is used to compensate the mirror current of the first current and the second current based on the first compensation current; and / or

[0008] The mirror unit is configured to mirror the first current to generate a third mirror current and mirror the second current to generate a first proportional current; the compensation unit is configured to generate a second compensation current based on the first proportional current and the third mirror current; the output unit is configured to compensate the mirror currents of the first current and the second current based on the second compensation current; and / or

[0009] The mirror unit is configured to mirror the first current to generate a second mirror current and mirror the second current to generate a fourth proportional current; the compensation unit is configured to generate a third compensation current based on the second mirror current and the fourth proportional current; the output unit is configured to compensate the mirror currents of the first current and the second current based on the third compensation current; and / or

[0010] The mirror unit is configured to mirror the first current to generate a fourth mirror current and mirror the second current to generate a second proportional current; the compensation unit is configured to generate a fourth compensation current based on the fourth mirror current and the second proportional current; the output unit is configured to compensate the mirror currents of the first current and the second current based on the fourth compensation current.

[0011] In one or more embodiments of the present application, the first current generating unit comprises an amplifier, a first transistor, a first resistor, a second resistor, a third resistor, a first triode, a second triode and a third triode; a first end of the first transistor is connected with a power supply voltage, a control end of the first transistor is connected with an output end of the amplifier, a second end of the first transistor is connected with a first end of the first resistor and a first end of the second resistor, a second end of the first resistor is connected with a first input end of the amplifier, a second end of the first triode and a control end of the first triode, a second end of the second resistor is connected with a second input end of the amplifier and a first end of the third resistor, a second end of the third resistor is connected with a second end of the second triode and a control end of the second triode, a control end of the third triode is connected with the control end of the second triode, a second end of the third triode generates the first current, and a first end of the first triode, a first end of the second triode and a first end of the third triode are connected with a reference voltage.

[0012] In one or more embodiments of the present application, the second current generating unit comprises a fourth resistor, a fourth triode, a second transistor and a current mirror unit; a control end of the fourth triode is connected with a first end of the fourth resistor, a first end of the fourth triode is connected with a second end of the fourth resistor, a first end of the second transistor is connected with the first end of the fourth resistor, a control end of the second transistor is connected with a second end of the fourth triode, and the current mirror unit is connected with a second end of the second transistor and a second end of the fourth triode to generate the second current.

[0013] In one or more embodiments of the utility model, the mirror unit includes first current mirror unit and second current mirror unit, the first current mirror unit is used to mirror first current to produce first mirror current, second mirror current, third mirror current and fourth mirror current, the second current mirror unit is used to mirror second current to produce first proportional current, second proportional current, third proportional current and fourth proportional current.

[0014] In one or more embodiments of the utility model, the first current mirror unit includes first mirror module and second mirror module, the first mirror module is used to mirror first current to produce first intermediate current, first mirror current and second mirror current, the second mirror module is connected with first mirror module to mirror first intermediate current to produce third mirror current and fourth mirror current, or

[0015] The first current mirror unit includes first mirror module and second mirror module, the first mirror module is used to mirror first current to produce first intermediate current, first mirror current and second mirror current, the second mirror module is connected with first mirror module to mirror first intermediate current to produce third mirror current, fourth mirror current and fifth mirror current for providing to output unit.

[0016] In one or more embodiments of the utility model, the second current mirror unit includes first current mirror module and second current mirror module, the first current mirror module is used to mirror second current to produce second intermediate current, first proportional current and second proportional current, the second current mirror module is connected with first current mirror module to mirror second intermediate current to produce third proportional current and fourth proportional current, or

[0017] The second current mirror unit includes first current mirror module and second current mirror module, the first current mirror module is used to mirror second current to produce second intermediate current, first proportional current and second proportional current, the second current mirror module is connected with first current mirror module to mirror second intermediate current to produce third proportional current, fourth proportional current and fifth proportional current for providing to output unit.

[0018] In one or more embodiments of the utility model, the compensation unit includes first compensation module, second compensation module, third compensation module and fourth compensation module,

[0019] The first compensation module is used to subtract third proportional current generated by second current mirror and first mirror current generated by first current mirror to produce first compensation current,

[0020] The second compensation module is configured to generate a second compensation current by subtracting a third mirror current generated by the first current mirror from a first proportional current generated by the second current mirror.

[0021] The third compensation module is configured to generate a third compensation current by subtracting a fourth proportional current generated by the second current mirror from a second mirror current generated by the first current mirror.

[0022] The fourth compensation module is configured to generate a fourth compensation current by subtracting a fourth mirror current generated by the first current mirror from a second proportional current generated by the second current mirror.

[0023] In one or more embodiments of the utility model, the first compensation module, the second compensation module, the third compensation module and / or the fourth compensation module are current mirror units.

[0024] In one or more embodiments of the utility model, the output unit comprises one or more third current mirror modules for receiving compensation currents, the third current mirror modules being connected to the mirror units to compensate and integrate the mirror currents of the first current and the second mirror current and the compensation currents to generate a reference current.

[0025] Compared with the prior art, the current reference circuit of the utility model compensates by taking points on the reference current curve, adjusts the temperature coefficient of the reference current by injecting the curvature of the reference current at different temperature ranges according to the idea of multi-point interpolation, reduces the influence of high-order terms of transistors and the influence of temperature coefficients of resistors in the process, and guarantees that the compensation current with different temperature coefficients can be generated within a temperature range, realizes compensation current injection / withdrawal at different temperature ranges, and the compensation currents, the first current and the second current are generated from the same source, so that the adjustment process can be avoided and the test efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or the prior art, the drawings needed to be used in the embodiment or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the utility model, and those skilled in the art can obtain other drawings according to these drawings without creating creative labor.

[0027] Figure 1 It is a system block diagram of the current reference circuit in an embodiment.

[0028] Figure 2 It is a circuit principle diagram of the first current generating unit in an embodiment.

[0029] Figure 3Circuit schematic diagram of a second current generation unit in an embodiment.

[0030] Figure 4 Partial circuit schematic diagram of a mirror unit in an embodiment.

[0031] Figure 5 Partial circuit schematic diagram of a first compensation current generation in an embodiment.

[0032] Figure 6 Partial circuit schematic diagram of a second compensation current generation in an embodiment.

[0033] Figure 7 Partial circuit schematic diagram of a third compensation current generation in an embodiment.

[0034] Figure 8 Partial circuit schematic diagram of a fourth compensation current generation in an embodiment.

[0035] Figure 9 Partial circuit schematic diagram of a reference current generation in an embodiment.

[0036] Figure 10 Waveform diagram of a first compensation current, a second compensation current, a third compensation current and a fourth compensation current generation in an embodiment.

[0037] Figure 11 Waveform diagram of a reference current generation in an embodiment. DETAILED DESCRIPTION

[0038] In order to make the technical solutions in the present application better understood, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work should belong to the scope of protection of the present application.

[0039] In the specification, "coupling" or "connection" or "linked" includes both direct connection and indirect connection. Indirect connection is the connection through an intermediate medium, such as the connection through an electrically conductive medium, which can have a parasitic inductance or a parasitic capacitance; indirect connection can also include the connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as the connection through circuits or components such as switches, follower circuits, etc. In addition, in the present application, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply a certain actual relationship, quantity or order between the technical features.

[0040] In the detailed description of the specification, reference is made to the accompanying drawings, which form a part of the specification, in which like reference numerals refer to like parts throughout, and in which by way of illustration, example embodiments that can be implemented can be shown. It is to be understood that other embodiments can be utilized, and structural or logical changes can be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0041] Various operations can be described as multiple discrete actions or operations in turn, in a manner that can be helpful in understanding embodiments of the claimed subject matter. However, the order of description should not be construed as to imply that these operations are order dependent. In particular, these operations can not be performed in the order of presentation. Operations described can be performed in a different order than the described embodiments. Various additional operations can be performed and / or described operations can be omitted in additional embodiments.

[0042] For purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0043] Various components, devices, etc. can be referred to herein in singular form, or in plural form, e.g., "a transistor", "the transistor", "a switch", etc., but this is merely to facilitate discussion, and any element referred to in singular form can include a plurality of such elements according to the teachings herein.

[0044] The specification describes using the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising", "including", "having" and the like, as used with respect to embodiments of the present disclosure, are synonymous.

[0045] As Figure 1 shown in the utility model embodiment, a current reference circuit, including: first current generating unit, second current generating unit, mirror unit, compensation unit and output unit.

[0046] The first current generating unit is configured to generate a first current IPTC that is proportional to temperature. The second current generating unit is configured to generate a second current INTC that is inversely proportional to temperature.

[0047] The mirror unit is connected to the first current generating unit and the second current generating unit, and is configured to mirror the first current IPTC to generate one or more corresponding mirror currents and to mirror the second current INTC to generate one or more corresponding mirror currents. The compensation unit is connected to the mirror unit, and is configured to generate one or more compensation currents based on the mirror current of the first current IPTC and the mirror current of the second mirror current IPTAT1.

[0048] The output unit is connected to the mirror unit and the supplement unit, and is configured to compensate the mirror current of the first current IPTAT and the second current INTC based on the compensation current to generate a reference current.

[0049] like Figure 2 As shown, the first current generating unit includes an amplifier EA, a first transistor M1, a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2 and a third transistor Q3.

[0050] A first end of the first transistor M1 is connected to a power supply voltage, a control end of the first transistor M1 is connected to an output end of the amplifier EA, a second end of the first transistor M1 is connected to a first end of a first resistor R1 and a first end of a second resistor R2, a second end of the first resistor R1 is connected to a first input end of the amplifier EA and a second end of a first transistor Q1, a second end of the first transistor Q1 is connected to a control end of the first transistor Q1, a second end of the second resistor R2 is connected to a second input end of the amplifier EA and a first end of a third resistor R3, a second end of the third resistor R3 is connected to a second end of the second transistor Q2 and a control end of the second transistor Q2, a control end of the third transistor Q3 is connected to the control end of the second transistor Q2, a second end of the third transistor Q3 generates a first current IPTAT, and a first end of the first transistor Q1, a first end of the second transistor Q2, and a first end of the third transistor Q3 are connected to a reference voltage.

[0051] In one embodiment, the reference voltage is ground voltage, and the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all NPN transistors, with the first terminal of each transistor being an emitter, the second terminal of each transistor being a collector, and the control terminal of each transistor being a base. In other embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 may be PNP transistors, and the first current generating unit may have other circuit structures.

[0052] like Figure 3As shown, the second current generating unit comprises a fourth resistor R4, a fourth transistor Q4, a second transistor M2 and a current mirror unit, the control end of the fourth transistor Q4 is connected with the first end of the fourth resistor R4, the first end of the fourth transistor Q4 is connected with the second end of the fourth resistor R4 and the reference voltage, the first end of the second transistor M2 is connected with the first end of the fourth resistor R4, the control end of the second transistor M2 is connected with the second end of the fourth transistor Q4, and the current mirror unit is connected with the second end of the second transistor M2 and the second end of the fourth transistor Q4 to generate the second current INTC. In other embodiments, the current generating unit 20 can be other circuit structures.

[0053] In an embodiment, the current mirror unit comprises a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7.

[0054] The first end of the third transistor M3, the first end of the fourth transistor M4 and the first end of the fifth transistor M5 are connected with the power voltage, the control end of the third transistor M3, the control end of the fourth transistor M4 and the control end of the fifth transistor M5 are connected, the second end of the third transistor M3 is connected with the control end of the third transistor M3 and the second end of the second transistor M2, the second end of the fourth transistor M4 is connected with the control end of the second transistor M2 and the second end of the fourth transistor Q4, the second end of the fifth transistor M5 is connected with the second end of the sixth transistor M6, the control end of the sixth transistor M6 and the control end of the seventh transistor M7, the first end of the sixth transistor M6 and the first end of the seventh transistor M7 are connected with the reference voltage, and the second end of the seventh transistor M7 generates the second current INTC.

[0055] The width-length ratio between the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 can be set as required.

[0056] In an embodiment, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are N-channel MOS transistors, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are P-channel MOS transistors, and the first end of each transistor is the source, the second end of each transistor is the drain, and the control end of each transistor is the gate. In other embodiments, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are P-channel MOS transistors or other types of transistors such as transistors, and the third transistor M3, the fourth transistor M4 and the fifth transistor M5 are N-channel MOS transistors or other types of transistors such as transistors.

[0057] The mirroring of the first current IPTC by the mirroring unit can generate one or more corresponding mirror currents and the mirroring of the second current INTC by the mirroring unit can generate one or more corresponding mirror currents, and the number of the mirror currents of the first current IPTC and the mirror currents of the second current INTC are selected as needed to achieve the best compensation effect.

[0058] In one embodiment, four mirror currents (a first mirror current IPTC1, a second mirror current IPTC2, a third mirror current IPTC3 and a fourth mirror current IPTC4) are generated by mirroring the first current IPTC and four mirror currents (a first proportional current INTC1, a second proportional current INTC2, a third proportional current INTC3 and a fourth proportional current INTC4) are generated by mirroring the second current INTC.

[0059] The mirroring unit generates the first mirror current IPTC1 by mirroring the first current IPTC and generates the third proportional current INTC3 by mirroring the second current INTC, and the compensation unit generates the first compensation current I1 based on the third proportional current INTC3 and the first mirror current IPTC1.

[0060] At the same time, the mirroring unit generates the third mirror current IPTC3 by mirroring the first current IPTC and generates the first proportional current INTC1 by mirroring the second current INTC, and the compensation unit generates the second compensation current I2 based on the first proportional current INTC1 and the third mirror current IPTC3.

[0061] In addition, the mirroring unit generates the second mirror current IPTC2 by mirroring the first current IPTC and generates the fourth proportional current INTC4 by mirroring the second current INTC, and the compensation unit generates the third compensation current I3 based on the second mirror current IPTC2 and the fourth proportional current INTC4.

[0062] And the mirroring unit generates the fourth mirror current IPTC4 by mirroring the first current IPTC and generates the second proportional current INTC2 by mirroring the second current INTC, and the compensation unit generates the fourth compensation current I4 based on the fourth mirror current IPTC4 and the second proportional current INTC2.

[0063] Finally, the mirroring currents of the first current IPTAT and the second current INTC are compensated by the output unit based on the first compensation current I1, the second compensation current I2, the third compensation current I3 and the fourth compensation current I4.

[0064] Specifically, the mirror unit includes a first current mirror unit and a second current mirror unit. The first current mirror unit is used to mirror the first current IPTC to generate a first mirror current IPTC1, a second mirror current IPTC2, a third mirror current IPTC3, a fourth mirror current IPTC4 and a fifth mirror current IPTC5. The second current mirror unit is used to mirror the second current INTC to generate a first proportional current INTC1, a second proportional current INTC2, a third proportional current INTC3, a fourth proportional current INTC4 and a fifth proportional current INTC5.

[0065] Among them, the first current mirror unit includes a first mirror module and a second mirror module. The first mirror module is used to mirror the first current IPTC to generate a first intermediate current IP, a first mirror current IPTC1, and a second mirror current IPTC2. The second mirror module is connected to the first mirror module to mirror the first intermediate current IP to generate a third mirror current IPTC3, a fourth mirror current IPTC4, and a fifth mirror current IPTC5 for providing to the output unit.

[0066] like Figure 4 、 Figure 5 and Figure 7 As shown, in one embodiment, the first mirror module includes: a sixth resistor R6, a tenth transistor M10, an eleventh transistor M11, an eighteenth transistor M18, a nineteenth transistor M19, a twenty-second transistor M22, a twenty-third transistor M23, a thirty-eighth transistor M38, and a thirty-ninth transistor M39. The width-to-length ratios of the tenth transistor M10, the eleventh transistor M11, the eighteenth transistor M18, the nineteenth transistor M19, the twenty-second transistor M22, the twenty-third transistor M23, the thirty-eighth transistor M38, and the thirty-ninth transistor M39 can be set as needed.

[0067] The first end of the sixth resistor R6 is used for receiving the first current IPTC, and a current mirror is needed to mirror the first current IPTC on the third transistor Q3 in an embodiment. The second end of the sixth resistor R6 is connected to the second end of the tenth transistor M10. The first end of the tenth transistor M10 is connected to the second end of the eleventh transistor M11. The first end of the eleventh transistor M11 is connected to a reference voltage. The control end of the tenth transistor M10 is connected to the first end of the sixth resistor R6. The control end of the eleventh transistor M11 is connected to the second end of the sixth resistor R6. The control end of the tenth transistor M10 is connected to the control end of the eighteenth transistor M18, the control end of the twenty-second transistor M22, and the control end of the thirty-eighth transistor M38. The control end of the eleventh transistor M11 is connected to the control end of the nineteenth transistor M19, the control end of the twenty-third transistor M23, and the control end of the thirty-ninth transistor M39. The first end of the eighteenth transistor M18 is connected to the second end of the nineteenth transistor M19. The first end of the nineteenth transistor M19 is connected to a reference voltage. The first end of the twenty-second transistor M22 is connected to the second end of the twenty-third transistor M23. The first end of the twenty-third transistor M23 is connected to a reference voltage. The first end of the thirty-eighth transistor M38 is connected to the second end of the thirty-ninth transistor M39. The first end of the thirty-ninth transistor M39 is connected to a reference voltage.

[0068] The first current IPTC is mirrored to generate a first intermediate current IP through the sixth resistor R6, the tenth transistor M10, the eleventh transistor M11, the eighteenth transistor M18, and the nineteenth transistor M19. The first current IPTC is mirrored to generate a first mirror current IPTC1 through the sixth resistor R6, the tenth transistor M10, the eleventh transistor M11, the twenty-second transistor M22, and the twenty-third transistor M23. The first current IPTC is mirrored to generate a second mirror current IPTC2 through the sixth resistor R6, the tenth transistor M10, the eleventh transistor M11, the thirty-eighth transistor M38, and the thirty-ninth transistor M39.

[0069] In an embodiment, the tenth transistor M10, the eleventh transistor M11, the eighteenth transistor M18, the nineteenth transistor M19, the twenty-second transistor M22, the twenty-third transistor M23, the thirty-eighth transistor M38, and the thirty-ninth transistor M39 are N-channel MOS transistors, and the first end of each transistor is a source, the second end of each transistor is a drain, and the control end of each transistor is a gate. In other embodiments, the tenth transistor M10, the eleventh transistor M11, the eighteenth transistor M18, the nineteenth transistor M19, the twenty-second transistor M22, the twenty-third transistor M23, the thirty-eighth transistor M38, and the thirty-ninth transistor M39 can be other types of transistors such as triodes.

[0070] As Figure 4 , Figure 6 , Figure 8 and Figure 9 shown, in an embodiment, the second mirror module includes: an eighth resistor R8, a sixteenth transistor M16, a seventeenth transistor M17, a twenty-eighth transistor M28, a twenty-ninth transistor M29, a forty-fourth transistor M44, a forty-fifth transistor M45, a fifty-fourth transistor M54 and a fifty-fifth transistor M55. The width-length ratio between the sixteenth transistor M16, the seventeenth transistor M17, the twenty-eighth transistor M28, the twenty-ninth transistor M29, the forty-fourth transistor M44, the forty-fifth transistor M45, the fifty-fourth transistor M54 and the fifty-fifth transistor M55 can be set as required.

[0071] The first end of the eighth resistor R8 is connected with the second end of the eighteenth transistor M18, the second end of the eighth resistor R8 is connected with the second end of the seventeenth transistor M17, the second end of the sixteenth transistor M16 is connected with the first end of the seventeenth transistor M17, and the first end of the sixteenth transistor M16 is connected with the power supply voltage. The control end of the sixteenth transistor M16 is connected with the second end of the eighth resistor R8, and the control end of the seventeenth transistor M17 is connected with the first end of the eighth resistor R8. The control end of the sixteenth transistor M16 is connected with the control end of the twenty-eighth transistor M28, the control end of the forty-fourth transistor M44 and the control end of the fifty-fourth transistor M54, and the control end of the seventeenth transistor M17 is connected with the control end of the twenty-ninth transistor M29, the control end of the forty-fifth transistor M45 and the control end of the fifty-fifth transistor M55. The second end of the twenty-eighth transistor M28 is connected with the first end of the twenty-ninth transistor M29, the first end of the twenty-eighth transistor M28 is connected with the power supply voltage, the second end of the forty-fourth transistor M44 is connected with the first end of the forty-fifth transistor M45, the first end of the forty-fourth transistor M44 is connected with the power supply voltage, the second end of the fifty-fourth transistor M54 is connected with the first end of the fifty-fifth transistor M55, and the first end of the fifty-fourth transistor M54 is connected with the power supply voltage.

[0072] The eighth resistor R8, the sixteenth transistor M16, the seventeenth transistor M17, the twenty-eighth transistor M28 and the twenty-ninth transistor M29 generate a third mirror current IPTC3 from the first intermediate current IP, the eighth resistor R8, the sixteenth transistor M16, the seventeenth transistor M17, the forty-fourth transistor M44 and the forty-fifth transistor M45 generate a fourth mirror current IPTC4 from the first intermediate current IP, and the eighth resistor R8, the sixteenth transistor M16, the seventeenth transistor M17, the fifty-fourth transistor M54 and the fifty-fifth transistor M55 generate a fifth mirror current IPTC5 from the first intermediate current IP, which is provided to the output unit.

[0073] In an embodiment, the sixteenth transistor M16, the seventeenth transistor M17, the twenty-eighth transistor M28, the twenty-ninth transistor M29, the forty-fourth transistor M44, the forty-fifth transistor M45, the fifty-fourth transistor M54 and the fifty-fifth transistor M55 are all P-channel MOS transistors, and the first end of each transistor is a source, the second end of each transistor is a drain, and the control end of each transistor is a gate. In other embodiments, the sixteenth transistor M16, the seventeenth transistor M17, the twenty-eighth transistor M28, the twenty-ninth transistor M29, the forty-fourth transistor M44, the forty-fifth transistor M45, the fifty-fourth transistor M54 and the fifty-fifth transistor M55 can be other types of transistors such as triodes.

[0074] In other embodiments, the first mirror module and the second mirror module can be Cascode current mirrors without resistors or other current mirror structures.

[0075] The second current mirror unit includes a first current mirror module and a second current mirror module. The first current mirror module is configured to mirror the second current INTC to generate a second intermediate current IN, a first proportional current INTC1 and a second proportional current INTC2. The second current mirror module is connected to the first current mirror module to mirror the second intermediate current IN to generate a third proportional current INTC3, a fourth proportional current INTC4 and a fifth proportional current INTC5 provided to the output unit.

[0076] As Figure 4 , Figure 6 and Figure 8As shown, in an embodiment, the first current mirror module comprises: a fifth resistor R5, an eighth transistor M8, a ninth transistor M9, a fourteenth transistor M14, a fifteenth transistor M15, a thirtieth transistor M30, a thirty-first transistor M31, a forty-sixth transistor M46 and a forty-seventh transistor M47. The width-length ratio between the eighth transistor M8, the ninth transistor M9, the fourteenth transistor M14, the fifteenth transistor M15, the thirtieth transistor M30, the thirty-first transistor M31, the forty-sixth transistor M46 and the forty-seventh transistor M47 can be set as required.

[0077] The first end of the fifth resistor R5 is configured to receive the second current INTC, and in an embodiment, the second current INTC on the seventh transistor M7 is also mirrored by a current mirror. The second end of the fifth resistor R5 is connected to the second end of the eighth transistor M8. The first end of the eighth transistor M8 is connected to the second end of the ninth transistor M9. The first end of the ninth transistor M9 is connected to a reference voltage. The control end of the eighth transistor M8 is connected to the first end of the fifth resistor R5. The control end of the ninth transistor M9 is connected to the second end of the fifth resistor R5. The control end of the eighth transistor M8 is connected to the control end of the fourteenth transistor M14, the control end of the thirtieth transistor M30 and the control end of the forty-sixth transistor M46. The control end of the ninth transistor M9 is connected to the control end of the fifteenth transistor M15, the control end of the thirty-first transistor M31 and the control end of the forty-seventh transistor M47. The first end of the fourteenth transistor M14 is connected to the second end of the fifteenth transistor M15. The first end of the fifteenth transistor M15 is connected to a reference voltage. The first end of the thirtieth transistor M30 is connected to the second end of the thirty-first transistor M31. The first end of the thirty-first transistor M31 is connected to a reference voltage. The first end of the forty-sixth transistor M46 is connected to the second end of the forty-seventh transistor M47. The first end of the forty-seventh transistor M47 is connected to a reference voltage.

[0078] The second current INTC is mirrored by the fifth resistor R5, the eighth transistor M8, the ninth transistor M9, the fourteenth transistor M14 and the fifteenth transistor M15 to generate a second intermediate current IN. The second current INTC is mirrored by the fifth resistor R5, the eighth transistor M8, the ninth transistor M9, the thirtieth transistor M30 and the thirty-first transistor M31 to generate a first proportional current INTC1. The second current INTC is mirrored by the fifth resistor R5, the eighth transistor M8, the ninth transistor M9, the forty-sixth transistor M46 and the forty-seventh transistor M47 to generate a second proportional current INTC2.

[0079] In an embodiment, the eighth transistor M8, the ninth transistor M9, the fourteenth transistor M14, the fifteenth transistor M15, the thirtieth transistor M30, the thirty-first transistor M31, the forty-sixth transistor M46 and the forty-seventh transistor M47 are N-channel MOS transistors, and the first end of each transistor is a source, the second end of each transistor is a drain, and the control end of each transistor is a gate. In other embodiments, the eighth transistor M8, the ninth transistor M9, the fourteenth transistor M14, the fifteenth transistor M15, the thirtieth transistor M30, the thirty-first transistor M31, the forty-sixth transistor M46 and the forty-seventh transistor M47 can be other types of transistors such as triodes.

[0080] As shown in Figure 4 , Figure 5 , Figure 7 and Figure 9 , the second current mirror module includes the seventh resistor R7, the twelfth transistor M12, the thirteenth transistor M13, the twentieth transistor M20, the twenty-first transistor M21, the thirty-sixth transistor M36, the thirty-seventh transistor M37, the fifty-second transistor M52 and the fifty-third transistor M53. The width-to-length ratio between the twelfth transistor M12, the thirteenth transistor M13, the twentieth transistor M20, the twenty-first transistor M21, the thirty-sixth transistor M36, the thirty-seventh transistor M37, the fifty-second transistor M52 and the fifty-third transistor M53 can be set as needed.

[0081] The first end of the seventh resistor R7 is connected to the second end of the fourteenth transistor M14, and the second end of the seventh resistor R7 is connected to the second end of the thirteenth transistor M13. The second end of the twelfth transistor M12 is connected to the first end of the thirteenth transistor M13, and the first end of the twelfth transistor M12 is connected to a power supply voltage. The control end of the twelfth transistor M12 is connected to the second end of the seventh resistor R7, and the control end of the thirteenth transistor M13 is connected to the first end of the seventh resistor R7. The control end of the twelfth transistor M12 is connected to the control end of the twentieth transistor M20, the control end of the thirty-sixth transistor M36 and the control end of the fifty-second transistor M52, and the control end of the thirteenth transistor M13 is connected to the control end of the twenty-first transistor M21, the control end of the thirty-seventh transistor M37 and the control end of the fifty-third transistor M53. The second end of the twentieth transistor M20 is connected to the first end of the twenty-first transistor M21, and the first end of the twentieth transistor M20 is connected to a power supply voltage. The second end of the thirty-sixth transistor M36 is connected to the first end of the thirty-seventh transistor M37, and the first end of the thirty-sixth transistor M36 is connected to a power supply voltage. The second end of the fifty-second transistor M52 is connected to the first end of the fifty-third transistor M53, and the first end of the fifty-second transistor M52 is connected to a power supply voltage.

[0082] The seventh resistor R7, the twelfth transistor M12, the thirteenth transistor M13, the twentieth transistor M20 and the twenty-first transistor M21 mirror the second intermediate current IN to generate a third proportional current INTC3, the seventh resistor R7, the twelfth transistor M12, the thirteenth transistor M13, the thirty-sixth transistor M36 and the thirty-seventh transistor M37 mirror the second intermediate current IN to generate a fourth proportional current INTC4, and the seventh resistor R7, the twelfth transistor M12, the thirteenth transistor M13, the fifty-second transistor M52 and the fifty-third transistor M53 mirror the second intermediate current IN to generate a fifth proportional current INTC5 provided to the output unit.

[0083] In an embodiment, the twelfth transistor M12, the thirteenth transistor M13, the twentieth transistor M20, the twenty-first transistor M21, the thirty-sixth transistor M36, the thirty-seventh transistor M37, the fifty-second transistor M52 and the fifty-third transistor M53 are P-channel MOS transistors, and the first end of each transistor is a source, the second end of each transistor is a drain, and the control end of each transistor is a gate. In other embodiments, the twelfth transistor M12, the thirteenth transistor M13, the twentieth transistor M20, the twenty-first transistor M21, the thirty-sixth transistor M36, the thirty-seventh transistor M37, the fifty-second transistor M52 and the fifty-third transistor M53 can be other types of transistors such as triodes.

[0084] In other embodiments, the first current mirror module and the second current mirror module can be Cascode current mirrors without resistors or other current mirror structures.

[0085] In an embodiment, the compensation unit includes a first compensation module, a second compensation module, a third compensation module and a fourth compensation module. In other embodiments, if the compensation current to be compensated increases, the compensation module can be increased.

[0086] The first compensation module is configured to subtract the third proportional current INTC3 mirrored from the second current INTC and the first mirrored current IPTC1 mirrored from the first current IPTC to generate a first compensation current I1.

[0087] The second compensation module is configured to subtract the third mirrored current IPTC3 mirrored from the first current IPTC and the first proportional current INTC1 mirrored from the second current INTC to generate a second compensation current I2.

[0088] The third compensation module is configured to subtract the fourth proportional current INTC4 mirrored from the second current INTC and the second mirrored current IPTC2 mirrored from the first current IPTC to generate a third compensation current I3.

[0089] The fourth compensation module is configured to generate a fourth compensation current I4 by calculating the difference between a fourth mirror current IPTC4 generated by the mirror of the first current IPTC and a second proportional current INTC2 generated by the mirror of the second current INTC.

[0090] The first compensation module, the second compensation module, the third compensation module and the fourth compensation module are current mirror units. In other embodiments, the first compensation module, the second compensation module, the third compensation module and the fourth compensation module can have other structures.

[0091] like Figure 5 As shown, in one embodiment, the first compensation module includes: a ninth resistor R9, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, and a twenty-sixth transistor M27. The width-to-length ratios of the twenty-fourth transistor M24, the twenty-fifth transistor M25, the twenty-sixth transistor M26, and the twenty-sixth transistor M27 can be set as needed.

[0092] A first end of the ninth resistor R9 is connected to the second end of the twenty-first transistor M21, the second end of the twenty-second transistor M22, and the control end of the twenty-sixth transistor M26. The second end of the ninth resistor R9 is connected to the second end of the twenty-fourth transistor M24 and the control end of the twenty-seventh transistor M27. The control end of the twenty-fourth transistor M24 is connected to the first end of the ninth resistor R9. The first end of the twenty-fourth transistor M24 is connected to the second end of the twenty-fifth transistor M25. The control end of the twenty-fifth transistor M25 is connected to the second end of the ninth resistor R9. The first end of the twenty-fifth transistor M25 and the first end of the twenty-sixth transistor M27 are connected to the reference voltage. The first end of the twenty-sixth transistor M26 is connected to the second end of the twenty-seventh transistor M27. The second end of the twenty-seventh transistor M27 generates the first compensation current I1.

[0093] In one embodiment, the twenty-fourth transistor M24, the twenty-fifth transistor M25, the twenty-sixth transistor M26, and the twenty-sixth transistor M27 are N-channel MOS transistors, and the first end of each transistor is a source, the second end of each transistor is a drain, and the control end of each transistor is a gate. In other embodiments, the twenty-fourth transistor M24, the twenty-fifth transistor M25, the twenty-sixth transistor M26, and the twenty-sixth transistor M27 may be other types of transistors such as triodes.

[0094] like Figure 6As shown in the figure, the second compensation module comprises a tenth resistor R10, a thirty-second transistor M32, a thirty-third transistor M33, a thirty-fourth transistor M34 and a thirty-fifth transistor M35. The width-length ratio between the thirty-second transistor M32, the thirty-third transistor M33, the thirty-fourth transistor M34 and the thirty-fifth transistor M35 can be set as required.

[0095] The first end of the tenth resistor R10 is connected with the second end of the twenty-ninth transistor M29, the second end of the thirtieth transistor M30 and the control end of the thirty-fifth transistor M35, the second end of the tenth resistor R10 is connected with the second end of the thirty-third transistor M33, the second end of the thirty-second transistor M32 is connected with the first end of the thirty-third transistor M33, the first end of the thirty-second transistor M32 is connected with the power supply voltage, the control end of the thirty-third transistor M33 is connected with the first end of the tenth resistor R10, the control end of the thirty-second transistor M32 is connected with the second end of the tenth resistor R10 and the control end of the thirty-fourth transistor M34, the first end of the thirty-fourth transistor M34 is connected with the power supply voltage, the second end of the thirty-fourth transistor M34 is connected with the first end of the thirty-fifth transistor M35, and the second end of the thirty-fifth transistor M35 generates the second compensation current I2.

[0096] In an embodiment, the thirty-second transistor M32, the thirty-third transistor M33, the thirty-fourth transistor M34 and the thirty-fifth transistor M35 are P-channel MOS transistors, and the first end of each transistor is the source, the second end of each transistor is the drain, and the control end of each transistor is the gate. In other embodiments, the thirty-second transistor M32, the thirty-third transistor M33, the thirty-fourth transistor M34 and the thirty-fifth transistor M35 can be other types of transistors such as triodes.

[0097] As shown in the figure, Figure 7 The third compensation module comprises an eleventh resistor R11, a fortieth transistor M40, a forty-first transistor M41, a forty-second transistor M42 and a forty-third transistor M43. The width-length ratio between the fortieth transistor M40, the forty-first transistor M41, the forty-second transistor M42 and the forty-third transistor M43 can be set as required.

[0098] A first end of the eleventh resistor R11 is connected to the second end of the thirty-seventh transistor M37, the second end of the thirty-eighth transistor M38, and the control end of the forty-third transistor M43. The second end of the eleventh resistor R11 is connected to the second end of the forty-first transistor M41. The second end of the fortieth transistor M40 is connected to the first end of the fortieth transistor M41. The first end of the fortieth transistor M40 is connected to the power supply voltage. The control end of the fortieth transistor M41 is connected to the first end of the eleventh resistor R11. The control end of the fortieth transistor M40 is connected to the second end of the eleventh resistor R11 and the control end of the forty-second transistor M42. The first end of the forty-second transistor M42 is connected to the power supply voltage. The second end of the forty-second transistor M42 is connected to the first end of the forty-third transistor M43. The second end of the forty-third transistor M43 generates the third compensation current I3.

[0099] In one embodiment, the 40th transistor M40, the 41st transistor M41, the 42nd transistor M42, and the 43rd transistor M43 are P-channel MOS transistors, and the first end of each transistor is a source, the second end of each transistor is a drain, and the control end of each transistor is a gate. In other embodiments, the 40th transistor M40, the 41st transistor M41, the 42nd transistor M42, and the 43rd transistor M43 may be other types of transistors such as triodes.

[0100] like Figure 8 As shown, the fourth compensation module includes: a twelfth resistor R12, a 48th transistor M48, a 49th transistor M49, a 50th transistor M50, and a 51st transistor M51. The width-to-length ratios of the 48th transistor M48, the 49th transistor M49, the 50th transistor M50, and the 51st transistor M51 can be set as needed.

[0101] The first end of the twelfth resistor R12 is connected to the second end of the forty-fifth transistor M45, the second end of the forty-sixth transistor M46 and the control end of the fiftieth transistor M50. The second end of the twelfth resistor R12 is connected to the second end of the forty-eighth transistor M48 and the control end of the fifty-first transistor M51. The control end of the forty-eighth transistor M48 is connected to the first end of the twelfth resistor R12. The first end of the forty-eighth transistor M48 is connected to the second end of the forty-ninth transistor M49. The control end of the forty-ninth transistor M49 is connected to the second end of the twelfth resistor R12. The first end of the forty-ninth transistor M49 and the first end of the fifty-first transistor M51 are connected to the reference voltage. The first end of the fiftieth transistor M50 is connected to the second end of the fifty-first transistor M51. The second end of the fifty-first transistor M51 generates the fourth compensation current I4.

[0102] In an embodiment, the forty-eighth transistor M48, the forty-ninth transistor M49, the fiftieth transistor M50 and the fifty-first transistor M51 are N-channel MOS transistors, and the first end of each transistor is a source, the second end of each transistor is a drain, and the control end of each transistor is a gate. In other embodiments, the forty-eighth transistor M48, the forty-ninth transistor M49, the fiftieth transistor M50 and the fifty-first transistor M51 can be other types of transistors such as triodes.

[0103] As shown in FIG. 4, the output unit includes a third current mirror module for receiving the compensation currents. The third current mirror module is connected to the mirror unit to compensate and integrate the first current IPTC, the mirrored current of the second mirror current IPTAT1 and the compensation currents to generate the reference current. The current mirror ratio of the third current mirror module can be set as needed. Figure 9 In an embodiment, the third current mirror module is connected to the second end of the twenty-sixth transistor M26, the second end of the thirty-fifth transistor M35, the second end of the forty-third transistor M43, the second end of the fifty-first transistor M50, the second end of the fifty-third transistor M53 and the second end of the fifty-fifth transistor M55 to receive the first compensation current I1, the second compensation current I2, the third compensation current I3, the fourth compensation current I4, the fifth proportional current INTC5 and the fifth mirror current IPTC5 and output the reference current IREF.

[0104]

[0105] The waveform diagram of the first compensation current I1 obtained by the third proportional current INTC3 and the first mirror current IPTC1 is shown, the waveform diagram of the second compensation current I2 obtained by the third mirror current IPTC3 and the first proportional current INTC1 is shown, the waveform diagram of the third compensation current I3 obtained by the second mirror current IPTC2 and the fourth proportional current INTC4 is shown, and the waveform diagram of the fourth compensation current I4 obtained by the second proportional current INTC2 and the fourth mirror current IPTC4 is shown. Figure 10

[0106] The waveform diagram of the reference current IREF generated by the compensation of the first compensation current I1, the second compensation current I2, the third compensation current I3 and the fourth compensation current I4 is shown. The proportional summation of the fifth proportional current INTC5 and the fifth mirror current IPTC5 can eliminate the first-order term to obtain an open-down curve, and at this time, the temperature coefficient of the current is only the high-order term. In order to further reduce the temperature coefficient, compensation is introduced, the first compensation current I1 and the second compensation current I2 are used for two-point compensation in the low-temperature section, and the third compensation current I3 and the fourth compensation current I4 are used for two-point compensation in the high-temperature section. Through the compensation currents in the high-temperature section and the low-temperature section, the temperature coefficient of the reference current IREF can be effectively reduced. Figure 11 ​

[0107] Combination Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown in FIG. 3, by adjusting the width-length ratio between the transistor generating the third proportional current INTC3 and the transistor generating the first mirror current IPTC1, the intervention temperature point of the first compensation current I1 can be adjusted; similarly, by adjusting the width-length ratio between the transistor generating the third mirror current IPTC3 and the transistor generating the first proportional current INTC1, the intervention temperature point of the second compensation current I2 can be adjusted; by adjusting the width-length ratio between the transistor generating the fourth proportional current INTC4 and the transistor generating the second mirror current IPTC2, the intervention temperature point of the third compensation current I3 can be adjusted; by adjusting the width-length ratio between the transistor generating the fourth mirror current IPTC4 and the transistor generating the second proportional current INTC2, the intervention temperature point of the fourth compensation current I4 can be adjusted.

[0108] Combination Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown in FIG. 3, by adjusting the width-length ratio between the transistor generating the third proportional current INTC3 and the transistor generating the first mirror current IPTC1, the intervention temperature point of the first compensation current I1 can be adjusted; similarly, by adjusting the width-length ratio between the transistor generating the third mirror current IPTC3 and the transistor generating the first proportional current INTC1, the intervention temperature point of the second compensation current I2 can be adjusted; by adjusting the width-length ratio between the transistor generating the fourth proportional current INTC4 and the transistor generating the second mirror current IPTC2, the intervention temperature point of the third compensation current I3 can be adjusted; by adjusting the width-length ratio between the transistor generating the fourth mirror current IPTC4 and the transistor generating the second proportional current INTC2, the intervention temperature point of the fourth compensation current I4 can be adjusted.

[0109] As can be seen from the above, since the current sources with positive and negative temperature coefficients are the same, the high-order terms can be offset to each other, the amplitude of the high-order terms can be set by the proportion of the current mirror, and the adjustment of the current can be realized by adjusting the mirror proportion between the transistors, without the need for adjustment to compensate for the temperature coefficient without adjustment.

[0110] The application further discloses a chip comprising the current reference circuit.

[0111] It is apparent for a person skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, but that it can be implemented in other concrete forms without departing from the spirit or the essential characteristics of the present application. Therefore, the embodiments should be considered as exemplary and non-limiting, the scope of the present application being defined by the claims appended hereto rather than by the above description, and all the changes which fall within the meaning and the scope of the equivalent elements of the claims are intended to be embraced therein. Any reference signs in the claims should not be construed as limiting the claims to the figures in which the reference signs are used.

[0112] Furthermore, it should be understood that although the present specification describes exemplary embodiments, not every embodiment contains only one independent technical solution, and the present specification is described in this way only for the sake of clarity, and a person skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that a person skilled in the art can understand.

Claims

1. A current reference circuit, characterized in that: include: a first current generating unit, configured to generate a first current proportional to temperature; a second current generating unit, configured to generate a second current inversely proportional to the temperature; a mirror unit connected to the first current generating unit and the second current generating unit, and configured to mirror the first current to generate one or more corresponding mirror currents and to mirror the second current to generate one or more corresponding mirror currents; a compensation unit connected to the mirror unit, configured to generate one or more compensation currents based on a mirror current of the first current and a mirror current of the second mirror current; as well as The output unit is connected to the mirror unit and the supplement unit, and is used to compensate the mirror current of the first current and the second current based on the compensation current to generate a reference current.

2. The current reference circuit according to claim 1, wherein: The mirror unit is used to mirror the first current to generate a first mirror current and to mirror the second current to generate a third proportional current; The compensation unit is used to generate a first compensation current based on the third proportional current and the first mirror current; the output unit is used to compensate the mirror currents of the first current and the second current based on the first compensation current; and / or The mirror unit is used to mirror the first current to generate a third mirror current and to mirror the second current to generate a first proportional current; The compensation unit is used to generate a second compensation current based on the first proportional current and the third mirror current; the output unit is used to compensate the mirror currents of the first current and the second current based on the second compensation current; and / or The mirror unit is used to mirror the first current to generate a second mirror current and to mirror the second current to generate a fourth proportional current; The compensation unit is used to generate a third compensation current based on the second mirror current and the fourth proportional current; the output unit is used to compensate the mirror currents of the first current and the second current based on the third compensation current; and / or The mirror unit is used to mirror the first current to generate a fourth mirror current and to mirror the second current to generate a second proportional current; The compensation unit is configured to generate a fourth compensation current based on the fourth mirror current and the second proportional current; The output unit is configured to compensate for the mirror current of the first current and the second current based on the fourth compensation current.

3. The current reference circuit according to claim 1, wherein: The first current generating unit includes an amplifier, a first transistor, a first resistor, a second resistor, a third resistor, a first triode, a second triode, and a third triode; the first end of the first transistor is connected to a power supply voltage, the control end of the first transistor is connected to the output end of the amplifier, the second end of the first transistor is connected to the first end of the first resistor and the first end of the second resistor, the second end of the first resistor is connected to the first input end of the amplifier, the second end of the first triode, and the control end of the first triode, the second end of the second resistor is connected to the second input end of the amplifier and the first end of the third resistor, the second end of the third resistor is connected to the second end of the second triode and the control end of the second triode, the control end of the third triode is connected to the control end of the second triode, the second end of the third triode generates a first current, and the first end of the first triode, the first end of the second triode, and the first end of the third triode are connected to a reference voltage.

4. The current reference circuit according to claim 1, wherein: The second current generating unit includes a fourth resistor, a fourth triode, a second transistor and a current mirror unit, the control end of the fourth triode is connected to the first end of the fourth resistor, the first end of the fourth triode is connected to the second end of the fourth resistor, the first end of the second transistor is connected to the first end of the fourth resistor, the control end of the second transistor is connected to the second end of the fourth triode, and the current mirror unit is connected to the second end of the second transistor and the second end of the fourth triode to generate the second current.

5. The current reference circuit according to claim 1, wherein: The mirror unit includes a first current mirror unit and a second current mirror unit, the first current mirror unit is used to mirror the first current to generate a first mirror current, a second mirror current, a third mirror current and a fourth mirror current, and the second current mirror unit is used to mirror the second current to generate a first proportional current, a second proportional current, a third proportional current and a fourth proportional current.

6. The current reference circuit according to claim 5, characterized in that: The first current mirror unit includes a first mirror module and a second mirror module, the first mirror module is used to mirror the first current to generate a first intermediate current, a first mirror current and a second mirror current, and the second mirror module is connected to the first mirror module to mirror the first intermediate current to generate a third mirror current and a fourth mirror current; or The first current mirror unit includes a first mirror module and a second mirror module. The first mirror module is used to mirror the first current to generate a first intermediate current, a first mirror current, and a second mirror current. The second mirror module is connected to the first mirror module to mirror the first intermediate current to generate a third mirror current, a fourth mirror current, and a fifth mirror current for providing to the output unit.

7. The current reference circuit according to claim 5, characterized in that: The second current mirror unit includes a first current mirror module and a second current mirror module, the first current mirror module is used to mirror the second current to generate a second intermediate current, a first proportional current, and a second proportional current, and the second current mirror module is connected to the first current mirror module to mirror the second intermediate current to generate a third proportional current and a fourth proportional current; or The second current mirror unit includes a first current mirror module and a second current mirror module. The first current mirror module is used to mirror the second current to generate a second intermediate current, a first proportional current, and a second proportional current. The second current mirror module is connected to the first current mirror module to mirror the second intermediate current to generate a third proportional current, a fourth proportional current, and a fifth proportional current for providing to the output unit.

8. The current reference circuit according to claim 1, wherein: The compensation unit includes a first compensation module, a second compensation module, a third compensation module and a fourth compensation module; The first compensation module is used to generate a first compensation current by calculating the difference between a third proportional current generated by the second current mirror and a first mirror current generated by the first current mirror; The second compensation module is used to generate a second compensation current by calculating the difference between the third mirror current generated by the first current mirror and the first proportional current generated by the second current mirror; The third compensation module is used to generate a third compensation current by calculating the difference between the fourth proportional current generated by the second current mirror and the second mirror current generated by the first current mirror; The fourth compensation module is used to generate a fourth compensation current by calculating the difference between a fourth mirror current generated by the first current mirror and a second proportional current generated by the second current mirror.

9. The current reference circuit according to claim 2, wherein: The first compensation module, the second compensation module, the third compensation module and / or the fourth compensation module are current mirror units.

10. The current reference circuit according to claim 1, wherein: The output unit includes one or more third current mirror modules for receiving the compensation current. The third current mirror module is connected to the mirror unit to compensate and integrate the mirror current of the first current and the second mirror current and the compensation current to generate a reference current.

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