Charging upgrading multiplexing circuit

Abstract

The utility model belongs to the related field of charging upgrading circuits, and particularly relates to a charging upgrading multiplexing circuit. A main control chip is provided with a charging circuit, the charging circuit is provided with a charging positive input end and a charging negative input end and is connected with an external charging power supply, the main control chip is further provided with an upgrading end, the upgrading end is provided with a first upgrading circuit, and the input end of the first upgrading circuit is connected with the charging positive input end. And the first control circuit determines on-off of the first upgrading circuit according to whether the charging positive input end has voltage or not. Through multiplexing of the charging positive input end and the first upgrading circuit and switching of the first control circuit, the upgrading function of the circuit is achieved, and meanwhile upgrading and charging functions are prevented from being carried out at the same time.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the related field of charging upgrade circuit, and especially relates to a charging upgrade multiplexing circuit. BACKGROUND

[0002] The software upgrade of the product can repair the BUG left by the early software of the product, and when the product is produced, the software upgrade is usually directly burned into the main control chip in the form of burning.

[0003] The special software upgrade connection port makes the product appearance not beautiful and the design not convenient on some compact products.

[0004] However, the charging voltage greatly affects some signals with high sensitivity to fluctuations, and this multiplexing method cannot be used for some non-USB charging jacks, such as products with only positive and negative charging interfaces. UTILITY MODEL CONTENTS

[0005] To solve the technical problems of no corresponding technical solutions disclosed in the background art, packet loss during charging and upgrading, and non-USB charging jacks that cannot be upgraded, the utility model provides a dimming circuit and a lamp.

[0006] The utility model discloses a purpose through the following technical schemes:

[0007] In a first aspect, the embodiment provides a charging upgrade multiplexing circuit, which comprises:

[0008] A main control chip is provided with an upgrade end.

[0009] A charging circuit is provided with a charging positive input end and a charging negative input end.

[0010] A first upgrade circuit is provided with a first upgrade input end and a first upgrade output end.

[0011] The first upgrade circuit is provided with a first control circuit, and the first control circuit determines the on-off of the first upgrade circuit according to whether the charging positive input end has voltage.

[0012] The main control chip is provided with a charging circuit, the charging circuit is provided with a charging positive input end and a charging negative input end and is connected with an external charging power supply, and the main control chip is further provided with an upgrade end, the first upgrade circuit is arranged on the upgrade end, an input end of the first upgrade circuit is connected with the charging positive input end, and the first upgrade circuit is determined to be on-off by the first control circuit according to whether the charging positive input end has voltage. The charging positive input end and the first upgrade circuit are multiplexed, and the first control circuit is switched, so that the upgrade function of the circuit is realized, and the upgrade and charging functions are prevented from being performed simultaneously.

[0013] In some embodiments, the first control circuit includes a first control member, the first control member includes a first control end, a first control output end and a first control input end, the first control output end is a first upgrade output end, the first control input end is a first upgrade input end, and the first control end controls the first control member to make the first upgrade circuit on-off.

[0014] The first control member controls the on-off of the first upgrade circuit, so that data loss caused by simultaneous upgrade and charging is avoided.

[0015] In some embodiments, the first control member includes a first MOS tube, the first MOS tube is an N-channel MOS tube, a gate of the first MOS tube is the first control end, a source of the first MOS tube is the first control input end, and a drain of the first MOS tube is the first control output end.

[0016] The MOS tube is arranged to be on-off, the connection between the communication circuit and the charging positive input end can be disconnected through the first control end in communication, so that simultaneous communication and charging are avoided, and the MOS tube is used to prevent the main control chip from being damaged due to reverse surge of the charging voltage.

[0017] In some embodiments, the first control end can be connected with a control power supply.

[0018] Alternatively, the first control end can be connected with the main control chip for control.

[0019] When the first control end is connected with the control power supply to provide pull-up voltage, the MOS tube can be controlled to be cut off by controlling the voltage of the source of the MOS tube. When the first control end is controlled to be on-off by the main control chip, the MOS tube can be directly controlled to be turned on by controlling the voltage of the gate of the MOS tube.

[0020] In some embodiments, the first upgrade circuit further comprises a first resistor, a second resistor, a third resistor, and a first capacitor; one end of the first resistor is connected to the first control end, and the other end of the first resistor is connected to the control power supply; one end of the second resistor is connected to the control power supply, and the other end of the second resistor is connected to the upgrade end; one end of the third resistor is connected to the charging positive input end; the other end of the third resistor is connected to the first control output end; one end of the first capacitor is connected to the charging positive input end, and the other end of the first capacitor is connected to the low potential.

[0021] The first resistor and the second resistor function as voltage division, the third resistor functions as current limiting protection, and the first capacitor functions as filter protection.

[0022] In some embodiments, the second upgrade circuit and the third upgrade circuit are further included; the master control chip is provided with an upgrade reading end and an upgrade sending end; the second upgrade circuit is provided with a second upgrade output end and a second upgrade input end; the third upgrade circuit is provided with a third upgrade input end and a third upgrade output end; the second upgrade input end and the third upgrade input end are both connected to the charging positive input end; the second upgrade output end is connected to the upgrade reading end; and the third upgrade output end is connected to the upgrade sending end.

[0023] The second upgrade circuit further comprises a second control circuit, which determines the on-off of the second upgrade circuit according to whether the charging positive input end has voltage.

[0024] The third upgrade circuit further comprises a third control circuit, which determines the on-off of the third upgrade circuit according to whether the charging positive input end has voltage.

[0025] The second upgrade circuit and the third upgrade circuit are used to realize that when the upgrade receiving and sending ports are separated, the input and output can be realized through the charging positive input end.

[0026] In some embodiments, the second control circuit comprises a second control member, which comprises a second control end, a second control output end, and a second control input end; the second control output end is the second upgrade input end, the upgrade reading end is the second upgrade output end, and the second control end controls the second control member to make the second upgrade circuit on-off.

[0027] The third control circuit comprises a third control member, which comprises a third control end, a third control output end, and a third control input end; the third control output end is the third upgrade input end, the upgrade sending end is the third upgrade output end, and the third control end controls the third control member to make the third upgrade circuit on-off.

[0028] The first upgrade circuit and the second upgrade circuit realize the on-off of the upgrade circuit through the second control member and the third control member respectively, so as to avoid the simultaneous charging and upgrading functions.

[0029] In some embodiments, the second control member comprises a second MOS tube, the second MOS tube being an N-channel MOS tube, a gate of the second MOS tube being a second control end; a source of the second MOS tube being a second control input end; and a drain of the second MOS tube being a second control output end.

[0030] The third control member comprises a third MOS tube, the third MOS tube being an N-channel MOS tube, a gate of the third MOS tube being a third control end; a source of the third MOS tube being a third control input end; and a drain of the third MOS tube being a third control output end.

[0031] The second MOS tube and the third MOS tube are used to turn on the second upgrade circuit and the third upgrade circuit.

[0032] In some embodiments, the second control end is connected to a control power supply.

[0033] Alternatively, the second control end is connected to a master control chip for control.

[0034] The third control end is connected to a control power supply.

[0035] Alternatively, the third control end is connected to a master control chip for control.

[0036] The second control end and the third control end are used to adjust the source voltage of the MOS tube through an upgrade reading end and an upgrade sending end of the master control chip to control the turn-on of the MOS tube.

[0037] In some embodiments, the second upgrade circuit further comprises a fourth resistor, a fifth resistor, a ninth resistor, and a second capacitor; one end of the fifth resistor is connected to the second control end, and the other end of the fifth resistor is connected to a control power supply; one end of the fourth resistor is connected to the control power supply, and the other end of the fourth resistor is connected to an upgrade reading end; one end of the ninth resistor is connected to a charging positive input end; the other end of the ninth resistor is connected to the second control output end; one end of the second capacitor is connected to the charging positive input end, and the other end of the second capacitor is connected to a low potential.

[0038] The third upgrade circuit further comprises a sixth resistor, a seventh resistor, an eighth resistor, and a voltage stabilizing diode; one end of the seventh resistor is connected to the third control end, and the other end of the seventh resistor is connected to the control power supply; one end of the sixth resistor is connected to the control power supply, and the other end of the sixth resistor is connected to an upgrade sending end; one end of the eighth resistor is connected to the charging positive input end; the other end of the eighth resistor is connected to the third control output end; one end of the voltage stabilizing diode is connected to the charging positive input end, and the other end of the voltage stabilizing diode is connected to the low potential.

[0039] The third upgrade circuit and the fourth upgrade circuit are consistent with the first circuit structure, and a voltage stabilizing diode is added to prevent damage caused by overvoltage.

[0040] The utility model discloses a charging upgrade multiplexing circuit's beneficial effect is:

[0041] Through being provided with charging circuit in main control chip, charging circuit sets up charging positive input, charging negative input and links with external charging power supply, and main control chip still is provided with upgrade end, and is provided with first upgrade circuit on upgrade end, and the input of first upgrade circuit is connected with charging positive input, and decides first upgrade circuit on-off through first control circuit according to whether the voltage of charging positive input, through charging positive input, first upgrade circuit multiplexing, and through the switching of first control circuit, realize the upgrade function of circuit, avoid the simultaneous performance of upgrade and charging function simultaneously. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 It is the frame diagram of the utility model disciously a charging upgrade multiplexing circuit;

[0043] Figure 2 It is the circuit principle of the utility model disciously a charging upgrade multiplexing circuit Figure One ;

[0044] Figure 3 It is the circuit principle of the utility model disciously a charging upgrade multiplexing circuit Figure Two ;

[0045] REFERENCE NUMERALS:

[0046] R1, first resistance;R2, second resistance;R3, third resistance;R4, fourth resistance;R5, fifth resistance;R6, sixth resistance;R7, seventh resistance;R8, eighth resistance;R9, ninth resistance;

[0047] C1, first capacitor;C2, second capacitor;Z1, voltage stabilizing diode;

[0048] C+, charging positive input;C-, charging negative input;

[0049] Q1, first MOS tube;Q1_1, first control end;Q1_2, first control input end;Q1_3, first control output end;Q2, second MOS tube;Q2_1, second control end;Q2_2, second control input end;Q2_3, second control output end;Q3, third MOS tube;Q3_1, third control end;Q3_2, third control input end;Q3_3, third control output end;

[0050] U1, main control chip;U1_COM, upgrade end;U1_TX, upgrade sending end;U1_RX, upgrade reading end;VCC, control power supply. DETAILED DESCRIPTION

[0051] The preferred embodiments of the present application will be described in detail below with reference to the drawings, so that the advantages and features of the present application can be more clearly understood by those skilled in the art, and the scope of protection of the present application can be more clearly defined.

[0052] Reference will now be made to the drawings, wherein like components generally will be designated with the same reference numerals, which reference numeral usually corresponds to an equivalent component. The principles described herein are illustrated in the preferred embodiments in which the principles are implemented in a suitable computing environment. The following description is based on the preferred embodiments of the present application, which should not be considered as limiting the other embodiments of the present application not described in detail herein.

[0053] As used herein, the term "module" can be a software or hardware object that is executed on the computing system. The different components, modules, engines, and services described herein can be implemented as implemented objects on the computing system. The apparatuses and methods described herein can be implemented in software, and of course, can be implemented in hardware, and in software-hardware combinations, all within the scope of the present application.

[0054] Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a common embodiment.

[0055] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection or can communicate with each other; can be directly connected, or indirectly connected through an intermediate medium; can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0056] Embodiment 1:

[0057] As Figure 1 shown, the embodiment provides a charging upgrade multiplexing circuit, which comprises:

[0058] A master control chip U1 is provided with an upgrade end U1_1;

[0059] A charging circuit is provided with a charging positive input end C+ and a charging negative input end C-. The charging positive input end C+ is connected with the positive pole of a power supply, and the charging negative input end C- is connected with the negative pole of the power supply; and

[0060] The first upgrade circuit is provided with a first upgrade input end, a first upgrade output end; the first upgrade input end is connected with the charging positive input end C+; the first upgrade output end is connected with the upgrade end U1_1.

[0061] The first upgrade circuit is provided with a first control circuit, and the first control circuit determines the on-off of the first upgrade circuit according to whether the charging positive input end C+ has voltage.

[0062] Specifically, the main control chip U1 is generally an MCU, and the main control chip U1 is provided with the charging positive input end C+, the negative connection end and the upgrade end U1_1; the charging positive input end C+ is connected with the positive pole of the power supply, and the charging negative input end C- is connected with the negative pole of the power supply, so as to realize the internal charging of the product by the external power supply. The charging positive input end C+ and the negative connection end can be connected with the plug respectively, and the plug is provided with two metal conductive sheets connected with the power supply; or it can be the positive and negative charging ports of the USB charging head. The first upgrade input end of the first upgrade circuit is connected with the charging positive input end C+, so that the charging positive input end C+ is used with the first upgrade input end, and the function that the product can be charged and upgraded is realized. The first control circuit is arranged in the first upgrade input end to control the on-off of the first upgrade input end, and the first control circuit can be a switch-related circuit, such as a relay, a multi-stage switch circuit, a switch circuit and the like, and can be a switch chip, such as a relay-related chip, such as a transistor chip and the like. The first control circuit controls the on-off of the first upgrade circuit, realizes the switching of the overall circuit in the upgrade and charging functions, and the on-off of the first control circuit can be according to whether the voltage is detected. According to the voltage, it is judged that the current product is in the upgrade or charging state, so as to control the on-off of the first control circuit.

[0063] In some embodiments, the first control circuit can be a selection circuit, which selects to access the first upgrade circuit and the charging circuit through a selection switch.

[0064] The main control chip U1 is provided with a charging circuit, the charging circuit is provided with the charging positive input end C+ and the charging negative input end C- and is connected with the external charging power supply, and the main control chip U1 is also provided with the upgrade end U1_1, the first upgrade circuit is arranged on the upgrade end U1_1, the input end of the first upgrade circuit is connected with the charging positive input end C+, and the first control circuit determines the on-off of the first upgrade circuit according to whether the charging positive input end C+ has voltage. The charging positive input end C+ and the first upgrade circuit are multiplexed, and the switching of the first control circuit is realized, so as to realize the upgrade function of the circuit while avoiding the simultaneous performance of the upgrade and charging functions.

[0065] Embodiment 2:

[0066] As Figure 2As shown, based on the circuit structure mentioned in embodiment 1, the circuit structure proposed in embodiment 1 is further optimized and explained in this embodiment, and the difference of this embodiment is that:

[0067] In some embodiments, the first control circuit includes a first control element, the first control element includes a first control end Q1_1, a first control output end Q1_3 and a first control input end Q1_2; the first control output end Q1_3 is a first upgrade output end, the first control input end Q1_2 is a first upgrade input end, and the first control end Q1_1 controls the first control element to make the first upgrade circuit on-off.

[0068] Specifically, the first control circuit includes a first control element, which at least includes a first control output end Q1_3 and a first control input end Q1_2, so that the control element is connected into the upgrade circuit and needs to be provided with a controllable first control end Q1_1, the first control end Q1_1 can turn on and off the first control element, and the first control element can be an electronic device with a switching type, such as a high-side switch, a MOS tube, a relay, etc. The first control end Q1_1 can be further provided, which can control the on-off of the first control element, such as the gate of a triode, the on-off of a high-side switch, the on-off of a relay, to realize the control of the circuit.

[0069] Through the first control element, the on-off of the first upgrade circuit is controlled, and the data loss caused by simultaneous upgrading and charging is avoided.

[0070] In some embodiments, the first control element includes a first MOS tube Q1, the first MOS tube Q1 is an N-channel MOS tube, the gate of the first MOS tube Q1 is the first control end Q1_1; the source of the first MOS tube Q1 is the first control input end Q1_2; and the drain of the first MOS tube Q1 is the first control output end Q1_3.

[0071] Specifically, the first MOS tube Q1 is an N-channel MOS tube, the source of the first MOS tube Q1 is the first control input end Q1_2, the drain of the first MOS tube Q1 is the first control input end Q1_2, and the gate of the first MOS tube Q1 is the first control end Q1_1. The on-off of the MOS tube can be controlled through the gate of the first MOS tube Q1, and the control mode can be selected as main control chip U1 control, or the on-off of the first MOS tube Q1 can be realized by changing the source voltage of the first MOS tube Q1. More specifically, the MOS tube can be a commonly used NMOS tube model, such as SI2312DS, BSH103, etc. In this embodiment, the use of the MOS tube in the circuit can also prevent the reverse surge of the charging current from the upgrade end U1_1 to the main control chip U1 through the cut-off protection of the MOS tube when charging, thereby preventing the main control chip U1 from being burned out.

[0072] By setting the MOS tube to turn on and off, the first control end Q1_1 can disconnect the communication circuit and the charging positive input end C+ when communicating, avoiding simultaneous communication and charging, and preventing the main control chip U1 from being damaged by reverse surge of the charging voltage through the MOS tube.

[0073] In some embodiments, the first control end Q1_1 can be connected to the control power supply VCC.

[0074] Alternatively, the first control end Q1_1 can be connected to the main control chip U1 for control.

[0075] Specifically, the first control end Q1_1 can be connected to the control power supply VCC, and the control power supply VCC can be a power supply providing a pull-up voltage, such as 3.3V, 5V, etc., which needs to be able to meet the conduction condition of the MOS tube. Alternatively, the voltage of the first control end Q1_1 is controlled by the main control chip U1 so that the voltage reaches the conduction or cutoff.

[0076] When the first control end Q1_1 is connected to the control power supply VCC to provide a pull-up voltage, the source voltage of the MOS tube can be controlled to make the MOS tube cutoff. When the first control end Q1_1 is controlled by the main control chip U1 to turn on and off, the gate voltage of the MOS tube can be directly controlled to turn on.

[0077] In some embodiments, the first upgrade circuit further includes a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1; one end of the first resistor R1 is connected to the first control end Q1_1, and the other end of the first resistor R1 is connected to the control power supply VCC; one end of the second resistor R2 is connected to the control power supply VCC, and the other end of the second resistor R2 is connected to the upgrade end U1_1; one end of the third resistor R3 is connected to the charging positive input end C+; the other end of the third resistor R3 is connected to the first control output end Q1_3; one end of the first capacitor C1 is connected to the charging positive input end C+, and the other end of the first capacitor C1 is connected to the low potential.

[0078] Specifically, the first upgrade circuit further comprises a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1. The first resistor R1 and the second resistor R2 serve to divide the voltage of the control power supply VCC to stabilize the voltage to reach the on state of the MOS tube. More specifically, 5V can be selected as the control power supply VCC, and 4.7KΩ or the like can be selected, and the resistance value of the voltage dividing resistor is determined according to the gate on voltage required by the selected MOS tube. The control power supply VCC is connected to the gate of the MOS tube to make the MOS tube in the on state under normal circumstances, and the MOS tube is turned off by changing the source voltage of the MOS tube to cause the VGS voltage of the MOS tube to fail to reach the on state, thereby turning off the MOS tube. The third resistor R3 can serve as a current limiting resistor, and the resistance value thereof is determined according to the specific circuit, such as 4.7K or the like. The main purpose is also to prevent damage to circuit devices caused by excessive current. The first capacitor C1 is provided, and the size of the first capacitor C1 is determined according to the actual situation and can be 0.1uF or the like, which is used for filtering and stabilizing the upgrade information transmission signal.

[0079] The first resistor R1 and the second resistor R2 serve to divide the voltage, and the third resistor R3 serves to limit the current, and the first capacitor C1 serves to filter and protect.

[0080] Embodiment 3:

[0081] As shown in Figure 3 The embodiment is further optimized and described for some circuit with multiple upgrade pins of the main control chip U1, and the difference lies in that:

[0082] In some embodiments, a second upgrade circuit and a third upgrade circuit are further included; the main control chip U1 is provided with an upgrade reading end U1_RX and an upgrade transmission end U1_TX; the second upgrade circuit is provided with a second upgrade output end and a second upgrade input end; the third upgrade circuit is provided with a third upgrade input end and a third upgrade output end; the second upgrade input end and the third upgrade input end are connected to the charging positive input end C+; the second upgrade output end is connected to the upgrade reading end U1_RX; and the third upgrade output end is connected to the upgrade transmission end U1_TX.

[0083] The second upgrade circuit further comprises a second control circuit, which determines the on-off of the second upgrade circuit according to whether the charging positive input end C+ has voltage.

[0084] The third upgrade circuit further comprises a third control circuit, which determines the on-off of the third upgrade circuit according to whether the charging positive input end C+ has voltage.

[0085] Specifically, in some master control chip U1 with two or more upgrade pins, such as the upgrade reading end U1_RX, the upgrade sending end U1_TX and the like mentioned in the embodiment, which are different from the single upgrade end U1_1 in the embodiment 1. The embodiment designs an upgrade circuit for each upgrade pin, that is, a second upgrade circuit, a third upgrade circuit, and the number of upgrade circuits is determined according to the number of required upgrade pins. And each upgrade circuit corresponds to have an upgrade input end, that is, a second upgrade input end, a third upgrade output end; each upgrade circuit has an upgrade output end, that is, a second upgrade output end, a third upgrade output end. And all the upgrade input ends of the upgrade circuit, that is, the second upgrade input end, the third upgrade input end are connected to the charging positive input end C+. And the output end of the upgrade circuit is connected to different upgrade pins, that is, the upgrade reading end U1_RX, the upgrade sending end U1_TX; during the upgrade, the upgrade data is transmitted through the charging positive input end C+, and it should be noted that this method usually needs to stagger the transmission of data by the upgrade circuit to avoid interference between data. And each upgrade circuit is provided with a control circuit, that is, a second control circuit, a third control circuit; the second control circuit, the third control circuit and the first control circuit have the same function, that is, to turn on and off the corresponding upgrade circuit to avoid data instability and loss caused by data transmission during charging.

[0086] Through the second upgrade circuit and the third upgrade circuit, the upgrade receiving and sending port can also be input and output through the charging positive input end C+ when the upgrade receiving and sending port is separated.

[0087] In some embodiments, the second control circuit includes a second control member, and the second control member includes a second control end Q2_1, a second control output end Q2_3 and a second control input end Q2_2; the second control output end Q2_3 is the second upgrade input end, the upgrade reading end U1_RX is the second upgrade output end, and the second control end Q2_1 controls the second control member to turn on and off the second upgrade circuit;

[0088] The third control circuit includes a third control member, and the third control member includes a third control end Q3_1, a third control output end Q3_3 and a third control input end Q3_2; the third control output end Q3_3 is the third upgrade input end, the upgrade sending end U1_TX is the third upgrade output end, and the third control end Q3_1 controls the third control member to turn on and off the third upgrade circuit.

[0089] Specifically, the second control member and the third control member can be configured to be consistent with the first control member mentioned in Embodiment 2, and can be high-side switches, MOS tubes, relays, and the like, and further can be set to be the gate of a triode, the on-off of a high-side switch, or the on-off of a relay through the second control terminal Q2_1 and the third control terminal Q3_1, so as to control the line. Further, the second control member and the third control member can also be configured to be different, such as the second control member being a MOS tube and the third control member being a relay, and the type of electronic device and the on-off mode can be determined according to the characteristics of the upgrade pin.

[0090] The first upgrade circuit and the second upgrade circuit respectively control the on-off of the upgrade circuit through the second control member and the third control member, so as to avoid the simultaneous performance of the charging and upgrade functions.

[0091] In some embodiments, the second control member includes a second MOS tube Q2, the second MOS tube Q2 being an N-channel MOS tube, the gate of the second MOS tube Q2 being the second control terminal Q2_1; the source of the second MOS tube Q2 being the second control input terminal Q2_2; and the drain of the second MOS tube Q2 being the second control output terminal Q2_3.

[0092] The third control member includes a third MOS tube Q3, the third MOS tube Q3 being an N-channel MOS tube, the gate of the third MOS tube Q3 being the third control terminal Q3_1; the source of the third MOS tube Q3 being the third control input terminal Q3_2; and the drain of the third MOS tube Q3 being the third control output terminal Q3_3.

[0093] Specifically, the second control member and the third control member can be N-channel MOS tubes like the first control member, and the structure thereof can also be configured to be consistent with the structure of the first control member, which will not be described herein.

[0094] The second MOS tube Q2 and the third MOS tube Q3 are used to control the conduction of the second upgrade circuit and the third upgrade circuit.

[0095] In some embodiments, the second control terminal Q2_1 can be connected to a control power supply VCC.

[0096] Alternatively, the second control terminal Q2_1 can be connected to a master control chip U1 for control.

[0097] The third control terminal Q3_1 can be connected to a control power supply VCC.

[0098] Alternatively, the third control terminal Q3_1 can be connected to a master control chip U1 for control.

[0099] Specifically, the second control end Q2_1 and the third control end Q3_1 can be set in the same manner as the first control end Q1_1, or can be set in different manners, for example, the second control end Q2_1 is connected to the control power supply VCC, and the third control end Q3_1 is controlled by the main control chip U1. By setting different control end control modes, interference caused by simultaneous sending of upgrade data by two upgrade pins can be avoided, and the on-off of the second MOS tube Q2 and the third MOS tube Q3 can be indirectly controlled by controlling the second control end Q2_1 and the third control end Q3_1, so as to realize the staggered sending of data.

[0100] The second control end Q2_1 and the third control end Q3_1 can control the on-off of the MOS tube by adjusting the source voltage through the upgrade reading end U1_RX and the upgrade sending end U1_TX of the main control chip U1, or can control the on-off of the MOS tube through the two control pins of the main control chip U1.

[0101] In some embodiments, the second upgrade circuit further comprises a fourth resistor R4, a fifth resistor R5, a ninth resistor R9, and a second capacitor C2; one end of the fifth resistor R5 is connected to the second control end Q2_1, and the other end of the fifth resistor R5 is connected to the control power supply VCC; one end of the fourth resistor R4 is connected to the control power supply VCC, and the other end of the fourth resistor R4 is connected to the upgrade reading end U1_RX; one end of the ninth resistor R9 is connected to the charging positive input end C+, and the other end of the ninth resistor R9 is connected to the second control output end Q2_3; one end of the second capacitor C2 is connected to the charging positive input end C+, and the other end of the second capacitor C2 is connected to the low potential.

[0102] The third upgrade circuit further comprises a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a voltage stabilizing diode Z1; one end of the seventh resistor R7 is connected to the third control end Q3_1, and the other end of the seventh resistor R7 is connected to the control power supply VCC; one end of the sixth resistor R6 is connected to the control power supply VCC, and the other end of the sixth resistor R6 is connected to the upgrade sending end U1_TX; one end of the eighth resistor R8 is connected to the charging positive input end C+, and the other end of the eighth resistor R8 is connected to the third control output end Q3_3; one end of the voltage stabilizing diode Z1 is connected to the charging positive input end C+, and the other end of the voltage stabilizing diode Z1 is connected to the low potential.

[0103] Specifically, the resistance distribution in the second upgrade circuit and the third upgrade circuit can be understood as consistent with the structure in the first upgrade circuit, wherein the functions of the electronic devices and the selection of the resistors can be the same as in the first upgrade circuit, and can be further explained as the second upgrade circuit and the third upgrade circuit being connected in parallel at the charging positive input end C+. In order to ensure the stability of the data, a capacitor filter can be arranged in the main circuit before parallel connection in the first upgrade circuit, or a filter circuit can be arranged in each branch, i.e. in the upgrade circuit. Arranging the filter circuit in the branch can select the size of the capacitor according to the type of data that can be transmitted by the upgrade pin, so that the circuit design is more flexible and the data transmission is more stable. A bidirectional voltage stabilizing diode Z1 can be further arranged to avoid breakdown of the circuit.

[0104] The third upgrade circuit and the fourth upgrade circuit can be consistent with the first circuit structure, and a voltage stabilizing diode Z1 is added to prevent damage caused by overvoltage.

[0105] The embodiments of the present application are described in detail above in combination with the drawings, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the purpose of the present application.

Claims

1. A charging upgrade multiplexing circuit, characterized in that: include: The main control chip (U1) is provided with an upgrade terminal (U1_1); The charging circuit is provided with a charging positive input terminal (C+) and a charging negative input terminal (C-); the charging positive input terminal (C+) is connected to the positive electrode of the power supply, and the charging negative input terminal (C-) is connected to the negative electrode of the power supply; as well as a first upgrade circuit, provided with a first upgrade input terminal and a first upgrade output terminal; the first upgrade input terminal is connected to the charging positive input terminal (C+); the first upgrade output terminal is connected to the upgrade terminal (U1_1); The first upgrade circuit is provided with a first control circuit, and the first control circuit determines whether the first upgrade circuit is turned on or off according to whether there is a voltage at the charging positive input terminal (C+).

2. The charging upgrade multiplexing circuit according to claim 1, characterized in that: The first control circuit includes a first control element, which includes a first control terminal (Q1_1), a first control output terminal (Q1_3), and a first control input terminal (Q1_2); the first control output terminal (Q1_3) is the first upgrade output terminal, the first control input terminal (Q1_2) is the first upgrade input terminal, and the first control terminal (Q1_1) controls the first control element to turn the first upgrade circuit on and off.

3. The charging upgrade multiplexing circuit according to claim 2, characterized in that: The first control element comprises a first MOS transistor (Q1), the first MOS transistor (Q1) being an N-channel MOS transistor, the gate of the first MOS transistor (Q1) being the first control end (Q1_1), the source of the first MOS transistor (Q1) being the first control input end (Q1_2), and the drain of the first MOS transistor (Q1) being the first control output end (Q1_3).

4. The charging upgrade multiplexing circuit according to claim 3, characterized in that: The first control terminal (Q1_1) can be connected to a control power supply (VCC); Alternatively, the first control terminal (Q1_1) can be connected to a main control chip (U1) for control.

5. The charging upgrade multiplexing circuit according to claim 4, characterized in that: The first upgrade circuit further includes a first resistor (R1), a second resistor (R2), a third resistor (R3), and a first capacitor (C1); one end of the first resistor (R1) is connected to the first control terminal (Q1_1), and the other end of the first resistor (R1) is connected to the control power supply (VCC); one end of the second resistor (R2) is connected to the control power supply (VCC), and the other end of the second resistor (R2) is connected to the upgrade terminal (U1_1); one end of the third resistor (R3) is connected to the charging positive input terminal (C+); the other end of the third resistor (R3) is connected to the first control output terminal (Q1_3); one end of the first capacitor (C1) is connected to the charging positive input terminal (C+), and the other end of the first capacitor (C1) is connected to a low potential.

6. The charging upgrade multiplexing circuit according to claim 1, characterized in that: It also includes a second upgrade circuit and a third upgrade circuit; the main control chip (U1) is provided with an upgrade reading end (U1_RX) and an upgrade sending end (U1_TX); the second upgrade circuit is provided with a second upgrade output end and a second upgrade input end; the third upgrade circuit is provided with a third upgrade input end and a third upgrade output end; the second upgrade input end and the third upgrade input end are both connected to the charging positive input end (C+); the second upgrade output end is connected to the upgrade reading end (U1_RX); and the third upgrade output end is connected to the upgrade sending end (U1_TX); The second upgrade circuit further includes a second control circuit, which determines whether the second upgrade circuit is turned on or off according to whether there is a voltage at the charging positive input terminal (C+); The third upgrading circuit further includes a third control circuit, and the third control circuit determines whether the third upgrading circuit is turned on or off according to whether there is a voltage at the charging positive input terminal (C+).

7. The charging upgrade multiplexing circuit according to claim 6, characterized in that: The second control circuit includes a second control element, which includes a second control terminal (Q2_1), a second control output terminal (Q2_3), and a second control input terminal (Q2_2); the second control output terminal (Q2_3) is the second upgrade input terminal, the upgrade reading terminal (U1_RX) is the second upgrade output terminal, and the second control terminal (Q2_1) controls the second control element to turn the second upgrade circuit on and off; The third control circuit includes a third control element, which includes a third control terminal (Q3_1), a third control output terminal (Q3_3) and a third control input terminal (Q3_2); the third control output terminal (Q3_3) is the third upgrade input terminal, the upgrade sending terminal (U1_TX) is the third upgrade output terminal, and the third control terminal (Q3_1) controls the third control element to turn the third upgrade circuit on and off.

8. The charging upgrade multiplexing circuit according to claim 7, characterized in that: The second control element comprises a second MOS transistor (Q2), the second MOS transistor (Q2) being an N-channel MOS transistor, the gate of the second MOS transistor (Q2) being the second control terminal (Q2_1); the source of the second MOS transistor (Q2) being the second control input terminal (Q2_2); and the drain of the second MOS transistor (Q2) being the second control output terminal (Q2_3); The third control element comprises a third MOS tube (Q3), the third MOS tube (Q3) being an N-channel MOS tube, the gate of the third MOS tube (Q3) being the third control terminal (Q3_1), the source of the third MOS tube (Q3) being the third control input terminal (Q3_2), and the drain of the third MOS tube (Q3) being the third control output terminal (Q3_3).

9. The charging upgrade multiplexing circuit according to claim 8, characterized in that: The second control terminal (Q2_1) can be connected to a control power supply (VCC); Alternatively, the second control terminal (Q2_1) can be connected to the main control chip (U1) for control The third control terminal (Q3_1) can be connected to a control power supply (VCC); Alternatively, the third control terminal (Q3_1) can be connected to a main control chip (U1) for control.

10. The charging upgrade multiplexing circuit according to claim 9, characterized in that: The second upgrade circuit further includes a fourth resistor (R4), a fifth resistor (R5), a ninth resistor (R9) and a second capacitor (C2); one end of the fifth resistor (R5) is connected to the second control terminal (Q2_1), and the other end of the fifth resistor (R5) is connected to the control power supply (VCC); one end of the fourth resistor (R4) is connected to the control power supply (VCC), and the other end of the fourth resistor (R4) is connected to the upgrade reading terminal (U1_RX); one end of the ninth resistor (R9) is connected to the charging positive input terminal (C+); the other end of the ninth resistor (R9) is connected to the second control output terminal (Q2_3); one end of the second capacitor (C2) is connected to the charging positive input terminal (C+), and the other end of the second capacitor (C2) is connected to a low potential; The third upgrade circuit further includes a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8) and a voltage stabilizing diode (Z1); one end of the seventh resistor (R7) is connected to the third control terminal (Q3_1), and the other end of the seventh resistor (R7) is connected to the control power supply (VCC); one end of the sixth resistor (R6) is connected to the control power supply (VCC), and the other end of the sixth resistor (R6) is connected to the upgrade sending terminal (U1_TX); one end of the eighth resistor (R8) is connected to the charging positive input terminal (C+); the other end of the eighth resistor (R8) is connected to the third control output terminal (Q3_3); one end of the voltage stabilizing diode (Z1) is connected to the charging positive input terminal (C+), and the other end of the voltage stabilizing diode (Z1) is connected to a low potential.

Images