Electronic structure
By forming a reinforcing layer and protruding conductive bumps on the first side of the electronic body, the problems of warpage and cracking in semiconductor packaging are solved, improving the reliability and yield of the product.
Patent Information
- Application Number
- CN202422644384.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-24
- Filing Date
- 2024-10-31
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-10-31
AI Technical Summary
In existing semiconductor packaging, the thinness of the electronic components and the large differences in their coefficients of thermal expansion lead to warping and cracking, affecting product reliability and yield.
A reinforcing layer is formed on the first side of the electronic body, and the height of the first conductive bump is greater than the thickness of the reinforcing layer, so that it protrudes and is exposed to improve the overall structural strength. At the same time, a conductive bump is formed on the second side and electrically connected through conductive perforations.
By strengthening the electronic structure with a reinforcing layer, the overall strength of the electronic structure is improved, warping problems are reduced, and the electronic body is prevented from cracking in subsequent processes, thus ensuring product reliability and yield.
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Figure CN223450892U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor device, and more particularly to an electronic structure. Background Art
[0002] To ensure the continued miniaturization and multifunctionality of electronic products and communications equipment, semiconductor packaging must evolve towards miniaturization to facilitate multi-pin connections. To this end, the industry has developed numerous advanced packaging technologies. For example, common advanced packaging methods include 2.5D packaging processes and processes combining fan-out wiring with embedded bridge components (FO-EB).
[0003] Figure 1 FIG. 1 is a cross-sectional view of a conventional semiconductor package 1. Figure 1 As shown, a wiring structure 14 on a carrier board 1b includes an electronic structure 1a and a plurality of conductive pillars 13. The electronic structure 1a includes an electronic body 11, a plurality of conductive bumps 111, a circuit portion 12, a plurality of external bumps 122, and a protective layer 19. The electronic body 11 has a plurality of conductive through-holes 110 formed therein, connecting its first surface 11a with its second surface 11b. The plurality of conductive bumps 111 are formed on the first surface 11a of the electronic body 11 and electrically connect the plurality of conductive through-holes 110. The circuit portion 12 is provided on the second surface 11b of the electronic body 11 and includes at least one insulating layer 120 and a conductive trace 121 bonded to the insulating layer 120. A plurality of external bumps 122 are formed on the circuit portion 12 and electrically connect the plurality of conductive through-holes 110 via the conductive traces 121. The protective layer 19 is formed on the first surface 11a of the electronic body 11 and covers the plurality of conductive bumps 111.
[0004] The electronic structure 1a is mounted on the wiring structure 14 via a plurality of external bumps 122. However, due to the thinness of the electronic body 11 and the presence of a protective layer 19 on the first surface 11a of the electronic body 11, the significant difference in the coefficient of thermal expansion (CTE) between the protective layer 19 and the electronic body 11 can easily cause the electronic structure 1a to warp and crack, leading to reduced quality reliability and yield issues in subsequent products.
[0005] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Utility Model Content
[0006] In view of the aforementioned deficiencies of the prior art, the present application provides an electronic structure, comprising: an electronic body having opposite first and second sides; a plurality of first conductive bumps formed on the first side; a plurality of second conductive bumps formed on the second side; and a reinforcing layer formed on the first side, wherein each of the first conductive bumps has a height greater than a thickness of the reinforcing layer, so that each of the first conductive bumps protrudes out of the reinforcing layer.
[0007] The present application also provides a method for manufacturing an electronic structure, comprising: providing an electronic body having opposite first and second sides, and a plurality of first conductive bumps formed on the first side; forming a reinforcing layer on the first side, wherein each of the first conductive bumps has a height greater than a thickness of the reinforcing layer, so that each of the first conductive bumps protrudes out of the reinforcing layer; and forming a plurality of second conductive bumps on the second side, and electrically connecting the plurality of second conductive bumps to the plurality of first conductive bumps.
[0008] In the aforementioned electronic structure and method, the electronic body has a plurality of conductive vias formed therein.
[0009] In the aforementioned electronic structure and method, the plurality of second conductive bumps are electrically connected to the plurality of first conductive bumps through the plurality of conductive vias.
[0010] In the aforementioned electronic structure and method, the plurality of first conductive bumps and the plurality of second conductive bumps are metal pillars.
[0011] In the aforementioned electronic structure and method, the ratio of the thickness of the reinforcing layer to the height of the first conductive bumps is 0.4-0.8.
[0012] In the aforementioned electronic structure and method, an adhesive layer is formed on the reinforcing layer, so that the reinforcing layer and the adhesive layer cover the plurality of first conductive bumps.
[0013] In the aforementioned electronic structure and method, the electronic structure serves as a bridge element for electrically connecting at least two electronic elements.
[0014] In the aforementioned electronic structure and method, the electronic body is disposed on a first carrier with the first side having the plurality of first conductive bumps through a first adhesive layer, and then the second side is thinned so that the plurality of conductive vias in the electronic body protrude out of the second side.
[0015] In the aforementioned electronic structure and method, a conductive circuit is formed on the second side of the electronic body, and the plurality of second conductive bumps are formed on the conductive circuit, wherein the conductive circuit is electrically connected to the conductive vias, so that the plurality of second conductive bumps are electrically connected to the plurality of first conductive bumps through the conductive circuit and the plurality of conductive vias.
[0016] The aforementioned electronic structure and method of fabricating the same further include disposing the electronic body on the second carrier with the second side having the second conductive bumps via a second adhesive layer, and removing the first carrier and the first adhesive layer to expose the plurality of first conductive bumps outside the reinforcement layer.
[0017] The aforementioned electronic structure and method of fabricating the same further include disposing the electronic body on the third carrier with the first side having the plurality of first conductive bumps, and removing the second carrier and the second adhesive layer.
[0018] As can be seen, in the electronic structure and method of fabricating the same, the reinforcement layer is formed on the first side of the electronic body having the plurality of first conductive bumps, and the height of each first conductive bump is greater than the thickness of the reinforcement layer, so that each first conductive bump protrudes outside the reinforcement layer to improve the overall strength of the electronic structure via the reinforcement layer, reduce warping problems, and avoid breakage problems of the electronic body due to being too thin during subsequent processes. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 FIG. 1 is a cross-sectional view of a conventional semiconductor package.
[0020] Figures 2A to 2F FIG. 1 is a cross-sectional view of a conventional semiconductor package.
[0021] Figures 3A to 3C FIG. 1 is a cross-sectional view of a conventional semiconductor package.
[0022] BRIEF DESCRIPTION OF DRAWINGS
[0023] 1 semiconductor package
[0024] 1a electronic structure
[0025] 1b carrier plate
[0026] 11 electronic body
[0027] 11a first surface
[0028] 11b second surface
[0029] 110 conductive via
[0030] 111 conductive bump
[0031] 12 circuit portion
[0032] 120 insulating layer
[0033] 121 conductive trace
[0034] 122 external bump
[0035] 13 electrically conductive post
[0036] 14 wiring structure
[0037] 19 protective layer
[0038] 2 electronic structure
[0039] 2a electronic module
[0040] 20 electronic body
[0041] 20a first side
[0042] 20b second side
[0043] 200 electrically conductive via
[0044] 21 first electrically conductive bump
[0045] 22 second electrically conductive bump
[0046] 23 strengthening layer
[0047] 24 electrically conductive line
[0048] 25 first carrier
[0049] 250 first adhesive layer
[0050] 26 second carrier
[0051] 260 second adhesive layer
[0052] 27 third carrier
[0053] 3 electronic package
[0054] 30 carrier
[0055] 301 release layer
[0056] 302 metal layer
[0057] 31 carrier structure
[0058] 32 electrically conductive post
[0059] 33 cladding layer
[0060] 34 line structure
[0061] 35 electronic element
[0062] 36 encapsulation layer
[0063] 37 electrically conductive element. DETAILED DESCRIPTION
[0064] The present application will be described in detail by specific embodiments, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of the present specification.
[0065] It should be noted that the structures, proportions, sizes, etc. shown in the accompanying drawings of the present specification are only used to understand and read the disclosure of the present specification by those skilled in the art, and are not used to limit the conditions that can be implemented by the present application, and therefore do not have technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technology disclosed by the present application. At the same time, the terms such as "upper", "first", "second", "one" and the like used in the present specification are only for the convenience of clear description, and are not used to limit the scope of the present application, and the change or adjustment of the relative relationship without substantially changing the technical content is also considered as the scope of the present application.
[0066] Figures 2A to 2F A cross-sectional schematic view of a method for manufacturing an electronic structure of the present application.
[0067] As shown in Figure 2A , an electronic module 2a is provided, which includes a plurality of electronic bodies 20 (two electronic bodies 20 are shown in the present figure). In the present embodiment, the electronic module 2a is, for example, a wafer, and the electronic bodies 20 are, for example, semiconductor chips.
[0068] The electronic body 20 has opposite first and second sides 20a and 20b, a plurality of first conductive bumps 21 are formed on the first side 20a, and a plurality of conductive vias 200 are formed in the electronic body 20, and the plurality of conductive vias 200 are electrically connected to the plurality of first conductive bumps 21. The first conductive bumps 21 are, for example, metal pillars of copper pillars.
[0069] As shown in Figure 2B , a reinforcing layer 23 is formed on the first side 20a to improve the overall structural strength of the electronic body 20, so as to avoid the problem of cracking of the electronic body 20 in subsequent processes.
[0070] In the present embodiment, polyimide (PI) is coated on the first side 20a to form the reinforcing layer 23, wherein the height of each first conductive bump 21 is greater than the thickness of the reinforcing layer 23, so that each first conductive bump 21 protrudes out of the reinforcing layer 23. In an embodiment, the ratio of the thickness of the reinforcing layer 23 to the height of the first conductive bump 21 is about 0.4-0.8.
[0071] As shown in Figure 2CAs shown, the electronic bodies 20 are placed on a first carrier 25 with the side (first side 20a) having the first conductive bumps 21 thereon via a first adhesive layer 250. That is, the electronic bodies 20 have a strengthening layer 23 and a first adhesive layer 250 formed on the first side 20a to cover the first conductive bumps 21. Next, the second side 20b is thinned (e.g., by a grinding process) to expose the conductive through-vias 200. The conductive through-vias 200 are, for example, through-silicon vias (TSVs).
[0072] like Figure 2D As shown, a conductive circuit 24 is formed on the second side 20b of the electronic body 20, and a plurality of second conductive bumps 22 are formed on the conductive circuit 24. The conductive circuit 24 is electrically connected to the plurality of conductive through-vias 200, so that the plurality of second conductive bumps 22 can be electrically connected to the plurality of first conductive bumps 21 through the conductive circuit 24 and the plurality of conductive through-vias 200. The second conductive bumps 22 include, for example, copper pillars and solder material.
[0073] like Figure 2E As shown, the electronic bodies 20 are placed on the second carrier 26 with the side (second side 20b) having the second conductive bumps 22 through the second adhesive layer 260, and the first carrier 25 and the first adhesive layer 250 are removed to expose the first conductive bumps 21 outside the strengthening layer 23.
[0074] like Figure 2F As shown, a plurality of electronic bodies 20 are placed on a third carrier 27 with the side (first side 20a) having the plurality of first conductive bumps 21, and the second carrier 26 and the second adhesive layer 260 are removed. Then, a singulation process is performed to separate each of the electronic bodies 20, thereby obtaining a plurality of electronic structures 2.
[0075] Through the aforementioned manufacturing method, the electronic structure 2 of the present application includes: an electronic body 20 having a first side 20a and a second side 20b opposite to each other; a plurality of first conductive bumps 21 formed on the first side 20a; a plurality of second conductive bumps 22 formed on the second side 20b; and a strengthening layer 23 formed on the first side 20a, wherein the height of each first conductive bump 21 is greater than the thickness of the strengthening layer 23, so that each first conductive bump 21 protrudes and is exposed from the strengthening layer 23.
[0076] The strengthening layer 23 is, for example, polyimide (PI), wherein a ratio of the thickness of the strengthening layer 23 to the height of the first conductive bump 21 is approximately 0.4-0.8.
[0077] In one embodiment, the electronic structure 2 further comprises a first adhesive layer 250 formed on the reinforcing layer 23, so that the reinforcing layer 23 and the first adhesive layer 250 cover the plurality of first conductive bumps 21.
[0078] Referring to Figures 3A to 3C For the manufacturing method of the electronic package integrating the electronic structure of the present application, the aforementioned electronic structure is mainly used as a bridge element to be integrated in the electronic package.
[0079] As Figure 3A shown, a carrier 30 is provided, and a carrier structure 31, an electronic structure 2 and a plurality of conductive pillars 32 are disposed on the carrier 30.
[0080] The carrier 30 is, for example, a plate body of semiconductor material (such as silicon or glass), on which a release layer 301 and a metal layer 302 (such as titanium / copper) are sequentially formed by, for example, coating, so as to form the carrier structure 31 on the metal layer 302.
[0081] In the present embodiment, the carrier structure 31 comprises a dielectric layer and a circuit layer combined with the dielectric layer. The material forming the dielectric layer is, for example, a dielectric material such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or the like, and the circuit layer and the dielectric layer can be formed by a redistribution layer (RDL) process.
[0082] The electronic structure 2 is disposed on the circuit layer of the carrier structure 31 through a plurality of second conductive bumps 22.
[0083] The conductive pillars 32 are disposed on the carrier structure 31 and electrically connected to the circuit layer. In the present embodiment, the material forming the conductive pillars 32 can be, for example, a metal material such as copper or a solder material.
[0084] As Figure 3B shown, a covering layer 33 is formed on the carrier structure 31, so that the covering layer 33 covers the electronic structure 2 and the conductive pillars 32. It should be understood that part of the material of the covering layer 33, part of the material of the conductive pillars 32 and part of the material of the first conductive bumps 21 can be removed by a planarization process (polishing), so that the end surface of the first conductive bumps 21 and the end surface of the conductive pillars 32 are exposed and flush with the upper surface of the covering layer 33.
[0085] In this embodiment, the encapsulation layer 33 is an insulating material, such as polyimide (PI), dry film, encapsulation glue or molding compound, such as epoxy. For example, the encapsulation layer 33 can be formed on the carrier structure 31 by liquid compound, lamination or compression molding.
[0086] Next, a circuit structure 34 is formed on the encapsulation layer 33, so that the circuit structure 34 electrically connects the plurality of conductive pillars 32 and the plurality of first conductive bumps 21.
[0087] In this embodiment, the circuit structure 34 includes an insulating layer and a redistribution layer (RDL) disposed on the insulating layer, so that the redistribution layer electrically connects the plurality of conductive pillars 32 and the plurality of first conductive bumps 21. Furthermore, the redistribution layer is formed of copper, and the insulating layer is formed of, for example, polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).
[0088] After that, a plurality of electronic elements 35 are disposed on the circuit structure 34, and a packaging layer 36 is formed to encapsulate the electronic elements 35.
[0089] In this embodiment, the electronic elements 35 are active elements, passive elements, or a combination thereof. The active elements are, for example, semiconductor chips, and the passive elements are, for example, resistors, capacitors, and inductors. In one embodiment, the electronic elements 35 are, for example, semiconductor chips such as graphics processing units (GPUs) and high bandwidth memories (HBM), and the electronic structure 2 is a bridge element (bridge chip) that electrically connects the circuit structure 34 through the first conductive bumps 21, thereby electrically bridging at least two of the electronic elements 35.
[0090] In addition, the packaging layer 36 is an insulating material, such as polyimide (PI), dry film, encapsulation glue or molding compound, such as epoxy, which can be formed on the circuit structure 34 by lamination or molding. It should be understood that the material forming the packaging layer 36 can be the same as or different from the material forming the encapsulation layer 33.
[0091] As shown in FIG. 1, the electronic structure 2 includes a carrier structure 31, a plurality of conductive pillars 32, a plurality of first conductive bumps 21, a circuit structure 34, a plurality of electronic elements 35, and a packaging layer 36. Figure 3CAs shown, the carrier 30 and the release layer 301 thereon are removed, and then the metal layer 302 is removed to expose the carrier structure 31.
[0092] Next, a plurality of conductive elements 37 are formed on the carrier structure 31, and the conductive elements 37 are electrically connected to the circuit layer. Then, a singulation process is performed to obtain the electronic package 3. The electronic package 3 can be disposed on an external electronic device such as a packaging substrate or a circuit board through the conductive elements 37. In the present embodiment, the conductive elements 37 include metal bumps made of copper and solder materials formed on the metal bumps.
[0093] In summary, according to the electronic structure and the manufacturing method thereof, a reinforcing layer is formed on the first side of the electronic body provided with a plurality of first conductive bumps. The height of each first conductive bump is greater than the thickness of the reinforcing layer, and each first conductive bump protrudes out of the reinforcing layer. The overall strength of the electronic structure is improved through the reinforcing layer, the warping problem is reduced, and the electronic body is not damaged due to being too thin during subsequent processes. In addition, the electronic structure and the electronic package and the manufacturing method thereof can be completed by using existing processes and equipment, without incurring additional costs.
[0094] The above embodiments are used to illustrate the principles and effects of the present application, and are not intended to limit the present application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be subject to the claims.
Claims
1. An electronic structure, characterized in that include: an electronic body having a first side and a second side opposite to each other; a plurality of first conductive bumps formed on the first side; a plurality of second conductive bumps formed on the second side; as well as A strengthening layer is formed on the first side, wherein the height of each of the first conductive bumps is greater than the thickness of the strengthening layer, so that each of the first conductive bumps protrudes out of the strengthening layer.
2. The electronic structure according to claim 1, wherein A plurality of conductive through holes are formed in the electronic body.
3. The electronic structure according to claim 2, wherein The plurality of second conductive bumps are electrically connected to the plurality of first conductive bumps through the plurality of conductive through-holes.
4. The electronic structure according to claim 1, wherein The plurality of first conductive bumps and the plurality of second conductive bumps are metal pillars.
5. The electronic structure according to claim 1, wherein The ratio of the thickness of the strengthening layer to the height of the first conductive bump is 0.4-0.
8.
6. The electronic structure according to claim 1, wherein The electronic structure further includes an adhesive layer formed on the strengthening layer, so that the strengthening layer and the adhesive layer cover the plurality of first conductive bumps.
7. The electronic structure according to claim 1, wherein The electronic structure serves as a bridge element to electrically connect at least two electronic elements.