Semiconductor structure and memory device

Abstract

Various embodiments of the utility model relate to a semiconductor structure, which comprises a two-port static random access memory (SRAM) cell, and the SRAM cell is provided with a write-in port part and a read port part electrically coupled to the write-in port part. The read port portion includes a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure also includes a first plurality of metal lines including write bit lines and complementary write bit lines, where the first plurality of metal lines are located at a first metal interconnect layer, where the first metal interconnect layer is located over the first source / drain feature. The semiconductor structure also includes a read bit line at a second metal interconnect layer, wherein the second metal interconnect layer is under the first source / drain feature.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor structure and a memory device. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. As a result of this growth, the functionality, performance, and the use of ICs have increased dramatically. In their quest to increase the performance of their products, designers have been driven to create ICs with smaller feature sizes. In order to reduce the size of features, new materials, processing techniques, and structures have been used in the construction of ICs.

[0003] Such size reduction has also increased the complexity of processing and manufacturing integrated circuits. For example, the substantial reduction in the size of ICs has resulted in closely spaced source / drain features and gate structures, as well as closely spaced source / drain contacts and gate vias. In some IC circuits (e.g., memory devices), a multi-layer interconnect structure providing metal traces (metal lines) for interconnecting power lines and signal lines within and between memory cells of a memory device is formed over transistors of the memory cells. With ever decreasing device size and closely spaced transistors, some metal traces (e.g., landing pads for signal lines) are formed with reduced dimensions, which can result in increased parasitic resistance, increased parasitic capacitance, high process risk, and / or poor connectivity; some signal lines can be disposed in metal lines that are far away from the memory cells, which can degrade the speed of the memory device. All of these issues present challenges in terms of performance, yield, and cost. Thus, while existing memory devices are generally capable of fulfilling their intended purposes, they are not in all respects satisfactory. SUMMARY

[0004] One aspect of the present application provides a semiconductor structure. The semiconductor structure includes a two-port static random access memory (SRAM) cell, the SRAM cell including a write port portion and a read port portion, the read port portion electrically coupled to the write port portion and including a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure further includes a first plurality of metal lines, the first plurality of metal lines including a write bit line and a complementary write bit line, wherein the first plurality of metal lines is at a first metal interconnect layer, wherein the first metal interconnect layer is over the first source / drain feature, and a read bit line is at a second metal interconnect layer, wherein the second metal interconnect layer is below the first source / drain feature.

[0005] Another aspect of the present application provides a memory device. The memory device includes a memory cell coupled to a read bit line and a write bit line. The memory device also includes a first interconnect structure located above the memory cell and including the write bit line. The memory device also includes a second interconnect structure located below the memory cell and including the read bit line.

[0006] Yet another aspect of the present application provides a semiconductor structure. The semiconductor structure includes a memory cell including a write port portion and a read port portion, the read port portion including a transistor having a first source / drain feature and a second source / drain feature, wherein the first source / drain feature is electrically connected to the write port portion. The semiconductor structure also includes a contact via located directly below the second source / drain feature and electrically coupled to the second source / drain feature. The semiconductor structure also includes a first metal interconnect layer located below the contact via and in direct contact with the contact via, wherein the read bit line is located at the first metal interconnect layer.

[0007] So that the foregoing features and advantages of the present application can be understood in more detail, a more particular description will be rendered by reference to specific embodiments thereof, which are illustrated in the appended drawings and will be described herein below. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1A is a schematic plan view of portions or all of an IC chip in accordance with various aspects of the present application.

[0009] FIG. 1B is a schematic plan view of portions or all of an array of memory cells (e.g., static random access memory (SRAM) cells) in accordance with various aspects of the present application.

[0010] FIG. 2 is a circuit diagram of a memory cell (e.g., an SRAM cell) that can be implemented in the IC chip of FIG. 1 in accordance with various aspects of the present application.

[0011] FIG. 3 illustrates cross-sectional views of various layers of portions or all of a memory device in accordance with various aspects of the present application.

[0012] FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 and FIG. 8 illustrates different portions of a layout of a memory device having FIG. 2 an SRAM cell in accordance with various aspects of the present application.

[0013] FIG. 9 illustrates along FIG. 4 andFIG. 6 a cross-sectional view of a portion or the entirety of the memory device taken along the line A-A' as shown.

[0014] FIG. 10 illustrating an alternative layout of a portion or the entirety of the memory device having FIG. 4 and FIG. 6 a cross-sectional view of a portion or the entirety of the memory device taken along the line B-B' as shown.

[0015] FIG. 11 illustrating an alternative layout of a portion or the entirety of the memory device having FIG. 12 SRAM cells according to various aspects of the present disclosure.

[0016] FIG. 13 illustrating a layout of various layers of another memory device according to various aspects of the present disclosure.

[0017] FIG. 12 illustrating a first alternative layout of various layers of a portion or the entirety of the memory device in FIG. 14 according to various aspects of the present disclosure.

[0018] FIG. 12 illustrating a second alternative layout of various layers of a portion or the entirety of the memory device in FIG. 15 according to various aspects of the present disclosure.

[0019] FIG. 12 illustrating a third alternative layout of various layers of a portion or the entirety of the memory device in FIG. 16 according to various aspects of the present disclosure.

[0020] FIG. 1A is a circuit diagram of another memory cell that can be implemented in the IC chip of FIG. 1 according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0021] The present utility model content provides many different embodiments or examples for implementing different features of the disclosure. Specific examples of components and arrangements are set forth in the following description of the present utility model content to simplify the present utility model content. Such examples, of course, are not meant to limit the present utility model content. For example, the formation of one feature on another feature, the formation of one feature as connected to another feature, and / or the formation of one feature as coupled to another feature in the following description of the present utility model content can include embodiments in which the features are formed directly contacting each other, and can also include embodiments in which intervening additional features can be formed between the features such that the features can not directly contact each other. In addition, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "below," "up," "down," "top," "bottom," and the like, can be used herein for ease of describing the present utility model content, one feature from another feature. The spatially relative terms are intended to encompass different orientations of the device in which the features can be present.

[0022] In addition, when describing a number or a range of numbers with "about," "approximately," or the like, the language is intended to encompass numbers that are within a reasonable range given the inherent variability of the manufacturing process, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic related to the number, the number or range of numbers encompasses a reasonable range including the described number, such as within ±10% of the described number. For example, a material layer having a thickness of "about 5 nm" can encompass a range of sizes from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer is known to be ±15% by one of ordinary skill in the art. Still further, the present utility model content can repeatedly use reference numerals and / or letters in various instances. Such repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0023] IC fabrication processes can generally be classified into three categories: front-end-of-line (FEOL) processes, middle-end-of-line (MEOL) processes, and back-end-of-line (BEOL) processes. FEOL processes generally encompass processes related to fabricating IC devices, such as transistors. For example, FEOL processes can include forming isolation features, gate structures, and source / drain features. Source / drain features can individually or collectively refer to sources or drains, depending on the context. The introduction of multi-gate devices, such as fin field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors, is a way to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). MBC transistors have gate structures that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. Because of their gate structures surrounding the channel region, MBC transistors can also be referred to as surrounding gate transistors (SGTs) or gate-all-around (GAA) transistors. The channel region of an MBC transistor can be formed from nanowires, nanosheets, or other nanostructures, and for this reason, MBC transistors can also be referred to as nanowire transistors or nanosheet transistors. MEOL processes generally encompass processes related to fabricating contacts to conductive features of an IC device, such as gate vias to gate structures and / or source / drain contacts to source / drain features. BEOL processes generally encompass processes related to fabricating multilayer interconnect structures that interconnect the IC features fabricated by the FEOL and MEOL processes, enabling the IC device to function. Features fabricated by the FEOL processes can be referred to as FEOL features. Features fabricated by the MEOL processes can be referred to as MEOL features. Features fabricated by the BEOL processes can be referred to as BEOL features.

[0024] To perform satisfactory functions, static random access memory (SRAM) cells are electrically coupled to signal lines and power lines. For example, a two-port SRAM cell formed by seven transistors (i.e., a 7T SRAM cell) is electrically coupled to signal lines including a read port bit line R BL, a read port word line R WL, a write port bit line W BL, a write port word line W WL, and power lines configured to provide predetermined voltages VDD and VSS (which can be referred to as VDD lines and VSS lines, respectively). In some technologies, all of these signal lines and power lines and associated landing pads are formed in metal lines disposed on a front side of the SRAM cell. In the context of the present disclosure, a landing pad generally refers to a metal line in a metal interconnect layer that provides intermediate local interconnections for the SRAM cell, such as (1) intermediate local interconnections between device-level features (e.g., gates or source / drain) and bit lines, bit line bars, word lines, voltage lines, or (2) intermediate local interconnections between bit lines, word lines, or power lines. As noted above, the substantial reduction in IC size results in closely spaced transistors and, thus, closely spaced, reduced-size BEOL features, which can result in increased parasitic resistance, increased parasitic capacitance, increased process risk, and / or reduced speed.

[0025] The present disclosure provides a memory device including a contact via and a read port bit line formed below a back side of an SRAM cell, rather than forming the read port bit line above a front side of the SRAM cell, to relax constraints on process window and optimization of SRAM performance. In one embodiment, the memory device includes a 7T SRAM cell having a write portion and a read portion, and a transistor of the read portion has a first source / drain feature coupled to the write portion and a second source / drain feature electrically coupled to the read port bit line. In a cross-sectional view, the read port bit line is disposed below the second source / drain feature. Forming the read port bit line below the second source / drain feature frees up space that would otherwise be occupied by a front side landing pad for the front side read port bit line, thus allowing for increased design flexibility of metal lines disposed above the SRAM cell and allowing for increased size of the back side read port bit line and front side signal lines (e.g., front side write port bit lines) to optimize performance.

[0026] Various aspects of the present disclosure will now be described in greater detail. To this end, FIG. 1B is a schematic plan view of an exemplary IC chip. FIG. 2 is a schematic plan view of a portion or all of an array of memory cells (e.g., static random access memory (SRAM) cells) in accordance with various aspects of the present disclosure. FIG. 3 is a circuit diagram of a 7T SRAM cell that can be implemented in the IC chip of FIG. 1. FIG. 4A cross-sectional view illustrating various layers of a portion or the entirety of a memory device according to various aspects of the present disclosure is shown. FIG. 5 、 FIG. 6 、 FIG. 7 、 FIG. 8 and FIG. 9 Different portions of a layout of a memory device 1000 having 7T SRAM cells according to various aspects of the present disclosure are illustrated. FIG. 4 The diagram shows various aspects of the present invention along FIG. 6 and FIG. 10 The memory device 1000 is partially or entirely cross-sectionally viewed along line AA′. FIG. 4 to FIG. 6 The diagram shows various aspects of the present invention along FIG. 11 The memory device 1000 is partially or entirely cross-sectionally viewed along line BB′. FIG. 12 Alternative layouts of part or all of the memory device 1000 are illustrated according to various aspects of the present disclosure. FIG. 13 The diagram illustrates the layout of various layers of a portion or the entirety of a memory device 2000 according to various aspects of the present disclosure. FIG. 14 A first alternative layout of various layers of a portion or the entirety of a memory device 2000 according to various aspects of the present disclosure is illustrated. FIG. 15 A second alternative layout of various layers of a portion or the entirety of the memory device 2000 according to various aspects of the present disclosure is illustrated. FIG. 16 A third alternative layout of various layers of a portion or the entirety of the memory device 2000 according to various aspects of the present disclosure is illustrated. FIG. 1A 1 is a circuit diagram of an SRAM cell with eight transistors (8T SRAM cell) that can be implemented in the IC chip of FIG1 according to various aspects of the present invention. For the avoidance of doubt, the X-axis, Y-axis, and Z-axis in the figure are perpendicular to each other and are used consistently throughout the present invention. Throughout the present invention, similar reference numerals represent similar features unless otherwise specified. In the present invention, front-side features (e.g., front-side source / drain contacts, front-side source / drain vias) may refer to features formed above the top surface of a workpiece, and rear-side features (e.g., rear-side read port bit lines R_BL) may refer to features formed below the bottom surface of a workpiece.

[0027] refer to FIG. 1BThe utility model discloses an IC chip 10 formed over a substrate and including at least an array 20 of memory cells. The array 20 can include static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, non-volatile random access memory (NVRAM) cells, flash memory cells, other suitable memory cells, or combinations thereof. The IC chip 10 can also include a number of other components, such as an array 30 of standard logic (STD) cells configured to provide various standard logic devices, such as inverters, AND, NAND, OR, XOR, NOR, other suitable devices, or combinations thereof. In addition, the IC chip 10 can include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, bipolar transistors, high voltage transistors, high frequency transistors, other suitable devices, or combinations thereof. Additional features can be added to the IC chip 10, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the IC chip 10.

[0028] In the present embodiment, reference is made to FIG. 1B The array 20 includes a plurality of SRAM cells (e.g., SRAM cells 100A, 100B, 100C, and 100D), which generally provide memory or storage capable of retaining data when power is applied. Accordingly, the array 20 is referred to as an SRAM array 20 hereinafter. The array 20 can also be referred to as a memory device 20 or a semiconductor structure 20. In the present utility model content, the memory device 20 can include one or more SRAM cells and frontside and backside interconnect structures associated with the one or more SRAM cells. In the present embodiment, each of the SRAM cells 100A-100D includes one or more GAA transistors, which are discussed in detail hereinafter.

[0029] In the present embodiment, reference is still made to FIG. 2 The SRAM cells 100A, 100B, 100C, and 100D together define a two-by-two grid that exhibit mirror symmetry and / or rotational symmetry with respect to one another. For example, using the SRAM cell 100C as a reference (denoted as "R0"), the layout of the SRAM cell 100A (denoted as "M X ") is a mirror of the layout of the SRAM cell 100C with respect to the X-axis. Similarly, the layout of the SRAM cell 100B is a mirror of the layout of the SRAM cell 100A, and the layout of the SRAM cell 100D (denoted as "M Y ") is a mirror of the layout of the SRAM cell 100C, both with respect to the Y-axis. In other words, the layout of the SRAM cell 100B (denoted as "R 180The layout of SRAM cell 100C is 180-degree symmetric about the geometric center of the grid, which is defined as the intersection of the imaginary line that bisects the rectangular grid along the Y-axis and the imaginary line that bisects the rectangular grid along the X-axis. In addition, in the illustrated embodiment, the dimensions of SRAM cells 100A-100D are substantially the same, i.e., have substantially the same horizontal (long) pitch S1 along the X-axis and substantially the same vertical (short) pitch S2 along the Y-axis. Thus, for simplicity, each of SRAM cells 100A-100D can be referred to as SRAM cell 100 hereinafter.

[0030] FIG. 3 The icon includes an exemplary circuit schematic of a seven-transistor (7T) two-port SRAM cell 100. Two-port SRAM cell 100 includes a write port portion 100W. In the present embodiment, write port portion 100W includes pull-up transistors PU-1, PU-2, pull-down transistors PD-1, PD-2, and channel gate transistors PG-1, PG-2. In the embodiment of the icon, transistors PU-1 and PU-2 are p-type transistors, and transistors PG-1, PG-2, PD-1, and PD-2 are n-type transistors. The drains of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled together, and the drains of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled together. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form a data latch. The gates of transistors PU-1 and PD-1 are coupled together and to the shared drain of transistors PU-2 and PD-2 to form a storage node SN, and the gates of transistors PU-2 and PD-2 are coupled together and to the shared drain of transistors PU-1 and PD-1 to form a complementary storage node SNB. The sources of pull-up transistors PU-1 and PU-2 are coupled to a power supply line configured to provide a first voltage VDD (this power supply line can be referred to as a VDD line), and the sources of pull-down transistors PD-1 and PD-2 are coupled to a power supply line configured to provide a second voltage VSS (this power supply line can be referred to as a VSS line), which in some embodiments can be electrical ground.

[0031] The storage node SN of the data latch is coupled to a bit line W BL (which can be referred to as a write bit line W BL or a write port bit line W BL) of the write port portion 100W through a pass gate transistor PG-2, and the complementary storage node SNB is coupled to a complementary bit line W BLB (which can be referred to as a complementary write bit line W BLB or a complementary write port bit line W BLB) of the write port portion 100W through a pass gate transistor PG-1. The storage node SN and the complementary storage node SNB are complementary nodes that are often at opposite logic levels (logic high or logic low). The gates of the pass gate transistors PG-1 and PG-2 are coupled to a word line W WL (which can be referred to as a write word line W WL or a write port word line W WL) of the write port portion 100W.

[0032] The two-port SRAM cell 100 also includes a read port portion 100R coupled to the write port portion 100W. The read port portion 100R of the SRAM cell 100 includes a read port pass gate transistor R-PG. One source / drain terminal of the read port pass gate transistor R-PG is electrically coupled to a bit line R BL of the read port portion 100R. The bit line of the read port portion 100R can be referred to as a read port bit line R BL or a read bit line R BL. The other source / drain terminal of the read port pass gate transistor R-PG is electrically coupled to the storage node SN (or the gates of the transistors PU-1 and PD-1). The gate of the read port pass gate transistor R-PG is coupled to a word line R WL of the read port portion 100R. The word line R WL of the read port portion 100R can be referred to as a read word line R WL or a read port word line R WL. In the illustrated embodiment, the transistor R-PG is a p-type transistor. That is, in the two-port SRAM cell 100, the pass gate transistors in the write port portion 100W are n-type transistors, and the pass gate transistor in the read port portion 100R is a p-type transistor.

[0033] FIG. 3 are schematic partial cross-sectional views of various layers (levels) that can be fabricated on a semiconductor substrate (or wafer) 60 to form a portion of a memory device (such as the IC chip 10 of FIG. 1) in accordance with various aspects of the present disclosure. As FIG. 3As shown, each layer includes a device layer DL and a multilayer interconnect structure MLI disposed above the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain features). In some embodiments, the device layer DL includes a substrate 60, doped regions 62 (e.g., n-wells and / or p-wells) disposed in the substrate 60, isolation features 64, and transistors T. In the depicted embodiment, the transistors T include a suspended channel layer 70 disposed between source / drain features 72 and a gate structure 68, where the gate structure 68 wraps around and / or surrounds the suspended channel layer 70. Each gate structure 68 has a metal gate stack formed by a gate 74 disposed above a gate dielectric layer 76 and a gate spacer 78 disposed along sidewalls of the metal gate stack. The multilayer interconnect structure MLI electrically couples various devices and / or components of the device layer DL so that they can operate in a manner specified by design requirements of the memory device.

[0034] In the depicted embodiment, the multilayer interconnect structure MLI includes a contact interconnect layer (CO level), a via zero interconnect layer (V0 level), a metal zero (M0) interconnect layer, a via one interconnect layer (VI level), a metal one interconnect layer (Ml level), a via two interconnect layer (V2 level), a metal two interconnect layer (M2 level), a via three interconnect layer (V3 level), and a metal three interconnect layer (M3 level). Each interconnect layer can be referred to as a metal interconnect layer. Metal lines formed at the M0 level can be referred to as M0 metal lines. Similarly, vias or metal lines formed at the VI level, the Ml level, the V2 level, the M2 level, the V3 level, and the M3 level can be referred to as VI vias, Ml metal lines, V2 vias, M2 metal lines, V3 vias, and M3 metal lines, respectively. The present subject matter contemplates multilayer interconnect structures MLI having more or fewer layers and / or levels, e.g., a multilayer interconnect structure MLI having a total of N metal interconnect layers (levels), where N is an integer ranging from 2 to 10. Each level of the multilayer interconnect structure MLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., interlayer dielectric (ILD) layers and etch stop layers (ESLs)). The dielectric layers of the multilayer interconnect structure MLI are collectively referred to as a dielectric structure 66. In some embodiments, conductive features at the same level of the multilayer interconnect structure MLI (e.g., the M0 level) are formed simultaneously. In some embodiments, conductive features at the same level of the multilayer interconnect structure MLI have substantially planar top surfaces and / or substantially planar bottom surfaces with respect to each other.

[0035] In FIG. 3In the illustrated embodiment, the CO level includes a source / drain contact (MD) disposed in the dielectric structure 66. The source / drain contact (MD) can be formed on and in direct contact with a silicide layer disposed directly on the source / drain feature. The VO level includes a gate via VG disposed on the gate structure and a source / drain contact via VD disposed on the source / drain contact MD, where the gate via VG connects the gate structure to the M0 metal line and the source / drain contact via VD connects the source / drain contact MD to the M0 metal line. In some embodiments, the VO level can also include a landing contact disposed in the dielectric structure 66. The VI level includes a VI via disposed in the dielectric structure 66, where the VI via connects the M0 metal line to the Ml metal line. The Ml level includes an Ml metal line disposed in the dielectric structure 66. The V2 level includes a V2 via disposed in the dielectric structure 66, where the V2 via connects the Ml metal line to the M2 metal line. The M2 level includes an M2 metal line disposed in the dielectric structure 66. The V3 level includes a V3 via disposed in the dielectric structure 66, where the V3 via connects the M2 metal line to the M3 metal line. For clarity, FIG. 3 The application has been simplified to better illustrate the inventive concept of the present application. Additional features can be added in each level of the memory, and some of the features described can be replaced, modified, or eliminated in other embodiments of the memory. FIG. 2 to FIG. 10 The cross-sectional view is merely an example and can not reflect the actual cross-sectional view of the IC chip 10 and / or the memory device 1000 described in further detail below.

[0036] In FIG. 4In the illustrated embodiment, the SRAM cell 100 of the memory device 1000 is electrically coupled to a write port bit line W_BL, a complementary write port bit line W_BLB, a write port word line W_WL, a read port word line R_WL, a read port bit line R_BL, a VSS line, and a VDD line. In this embodiment, the write port bit line W_BL and the complementary write port bit line W_BLB are located at the M2 level, and various bonding pads are formed between the M2 level and the device layer DL to provide a conductive path. The read port word line R_WL and the write port word line W_WL are located at the M1 level, and various bonding pads are formed between the M1 level and the device layer DL to provide a conductive path. The VSS line and the VDD line are located at the M0 level, and various conductive features are provided at the CO level and the V0 level to provide a conductive path. In this embodiment, as described above, in order to relax the process window for forming SRAM cells and conductive features (e.g., pads) in the multi-layer interconnect structure MLI and to ease restrictions on SRAM performance optimization, the read port bit line R_BL is located below the device layer DL of the SRAM cell 100. In other words, the read port bit line R_BL is located below the back side of the SRAM cell 100, while other signal lines and power lines, such as the write port bit line W_BL, the complementary write port bit line W_BLB, the write port word line W_WL, the read port word line R_WL, the VSS line, the VDD line, and associated pads, are formed above the front side of the SRAM cell 100.

[0037] FIG. 5 、 FIG. 6 、 FIG. 7 、 FIG. 8 and FIG. 2 Some embodiments according to the present invention include FIG. 4 More specifically, FIG. 5 FIG. 1 illustrates the layout of the device layer DL, CO layer, and V0 layer of the memory device 1000. FIG. 6 FIG. 1 illustrates the layout of the V0 and M0 levels of the memory device 1000. FIG. 7 FIG. 1 illustrates a partial portion of the layout of the device layer DL and the backside metal interconnect layer of the memory device 1000 . FIG. 8 FIG memory device 1000 is a partial layout of the M0 level, V1 level, and M1 level, and FIG. 9 FIG. 1 shows a partial portion of the layout of the M1 level, the V2 level, and the M2 level of the memory device 1000 . FIG. 4 The diagram shows some embodiments according to the present invention. FIG. 6 and FIG. 10 A partial cross-sectional view of the memory device taken along line AA' in FIG. FIG. 4 to FIG. 6The diagram shows some embodiments according to the present invention. FIG. 4 A partial cross-sectional view of the memory device taken along line BB' is shown.

[0038] First reference FIG. 4 At the device level DL, the two-port SRAM cell 100 (as part of the memory device 1000 ) includes active regions 102 and 104 located above the substrate 902 . FIG. 9 In the illustrated embodiment, active regions 102 and 104 each extend lengthwise along the X-axis and are separated from each other along the Y-axis by an isolation structure 904 (e.g., a shallow trench isolation (STI) feature). In this embodiment, active region 102 is a three-dimensional fin-shaped active region (hereinafter referred to as N-type fin 102) disposed in a doped region or well (e.g., a P-well, not shown) and is configured to provide a channel region for an N-type transistor (e.g., a pull-down transistor or a channel gate transistor), and active region 104 is a three-dimensional fin-shaped active region (hereinafter referred to as P-type fin 104) disposed in another doped region (e.g., an N-well, not shown) and is configured to provide a channel region for a P-type transistor (e.g., a pull-up transistor). In one embodiment, each of N-type fin 102 and P-type fin 104 includes a set of vertically stacked semiconductor layers (e.g., FIG. 4 The semiconductor layer 908 shown) or nanostructure.

[0039] Still refer to FIG. 4 The SRAM cell 100 further includes gate structures, such as gate structures 112, 114, 116, 118, and 120, which are oriented longitudinally along the Y axis and disposed over the N-type fin 102 and / or the P-type fin 104 to form various transistors. Each of the gate structures 112, 114, 116, 118, and 120 spans the channel region of the N-type fin 102 and / or the channel region of the P-type fin 104. In the illustrated embodiment, reference is made to FIG. 4As an example, gate structure 112 engages N-type fin 102 to form channel gate transistor PG-1. Gate structure 114 engages N-type fin 102 and P-type fin 104 to form pull-down transistor PD-1 and pull-up transistor PU-1, respectively. Gate structure 116 engages N-type fin 102 and P-type fin 104 to form pull-down transistor PD-2 and pull-up transistor PU-2, respectively. Gate structure 118 engages P-type fin 104 to form read port channel gate transistor R-PG. Gate structure 120 engages N-type fin 102 to form channel gate transistor PG-2. In one embodiment, gate structure 118 and gate structure 120 are portions of a continuous gate structure similar to gate structure 114 / 116. To achieve the desired functionality, an isolation structure can be formed to split the continuous gate structure into two electrically and physically isolated portions. That is, the sidewalls of gate structures 118 and 120 are aligned along the Y-axis. In this embodiment, pull-up transistors PU-1, PU-2, and read port channel gate transistor R-PG are P-type GAA transistors, and pull-down transistors PD-1 and PD-2, channel gate transistors PG-1 and PG-2 are N-type GAA transistors. The area utilization at device layer DL of SRAM cell 100 is considered efficient because only one unit area is not used to form functional transistors but accommodates the intersection of dielectric feature 110 and the active regions. Broken lines are used to illustrate the boundary 190 of two-port SRAM cell 100. Note that at least some of active regions 102, 104 and gate structures 112, 114, 116, 118, and 120 can extend beyond the illustrated boundary 190 because these active regions and gate structures can also form components of SRAM cells that are adjacent in other locations.

[0040] Still referring to FIG. 4 , memory device 1000 includes conductive features of CO and VO levels formed over SRAM cell 100. Gate via 150A is formed on gate structure 118 of read port channel gate transistor R-PG and is configured to electrically connect gate structure 118 of read port channel gate transistor R-PG to read port word line R_WL. Gate via 150C is formed on gate structure 112 of channel gate transistor PG-1 and is configured to electrically connect gate structure 112 of channel gate transistor PG-1 to write port word line W_WL. Gate via 150D is formed on gate structure 120 of channel gate transistor PG-2 and is configured to electrically connect gate structure 120 of channel gate transistor PG-2 to write port word line W_WL. Gate via 150E is formed on gate structure 114 and electrically connects gate structure 114 to a storage node (SN) located at a higher metal level. Gate via 150F is formed on gate structure 116 and electrically connects gate structure 116 to a complementary storage node (SNB) located at a higher metal level.

[0041] Still referring to FIG. 5 At the CO level and the VO level, the memory device 1000 also includes a dummy source / drain contact 160A next to the source / drain feature 182 of the channel gate transistor R-PG and held electrically floating because there is no corresponding source / drain contact via next to it. The memory device 1000 also includes another dummy source / drain contact 160B adjacent to the dielectric feature 110 and held electrically floating. A source / drain contact 160C and a source / drain contact via 170C next to it electrically connect the source region of the channel gate transistor PG-1 to the complementary write port bit line (W BLB). A source / drain contact 160D and a source / drain contact via 170D next to it electrically connect the source region of the channel gate transistor PG-2 to the write port bit line (W BL). A source / drain contact 160E and a source / drain contact via 170E next to it electrically connect the shared drain region of the channel gate transistor PG-1 and the pull-down transistor PD-1 along with the drain region of the pull-up transistor PU-1 to the complementary storage node (SNB). A source / drain contact 160F and a source / drain contact via 170F next to it electrically connect the shared drain region of the channel gate transistor PG-2 and the pull-down transistor PD-2 along with the shared drain region of the pull-up transistor PU-2 and the read port channel gate transistor R-PG to the storage node (SN). A source / drain contact 160G and a source / drain contact via 170G next to it electrically connect the shared source region of the pull-down transistor PD-1 and the pull-down transistor PD-2 to the VSS line. A source / drain contact 160H and a source / drain contact via 170H next to it electrically connect the shared source region of the pull-up transistor PU-1 and the pull-up transistor PU-2 to the VDD line. In the illustrated embodiment, the source / drain contacts 160A-160H are all elongated and have a length direction along the Y-axis that is parallel to the direction of extension of the gate structures 112-120.

[0042] The storage node SN includes a gate via 150E and a source / drain contact via 170F located on opposite sides of the gate structure 116. As will be described in further detail below, a metal line at the M0 level extends along the X-axis to connect the gate via 150E and the source / drain contact via 170F. In other words, the M0 metal line overhangs the gate structure 116 and provides the function of cross-coupling between the gate via 150E and the source / drain contact via 170F. Thus, in the layout, the gate via 150E and the source / drain contact via 170F are positioned at the same level along the Y-axis so that a metal line extending along the X-axis can connect both. Similarly, a complementary storage node (storage node bar) SNB includes a gate via 150F and a source / drain contact via 170E located on opposite sides of the gate structure 114. As will be described in further detail below, another metal line at the M0 level extends along the X-axis to span the gate structure 114 and connect the gate via 150F and the source / drain contact via 170E. In other words, the other M0 metal line overhangs the gate structure 114 and provides the function of cross-coupling between the gate via 150F and the source / drain contact via 170E. Thus, in the layout, the gate via 150F and the source / drain contact via 170E are positioned at the same level along the Y-axis so that a metal line extending along the X-axis can connect both.

[0043] Reference is now made to FIG. 5 The memory device 1000 includes conductive features at the M0 level formed over the SRAM cell 100. FIG. 5 The V0 level and the M0 level of the layout of the multi-level interconnect structure of the memory device 1000 are shown. At the M0 level, the memory device 1000 includes a plurality of metal tracks arranged in parallel. Specifically, in the layout embodiment shown, the memory device 1000 includes six metal tracks arranged in order from a first (M0 track 1) to a sixth (M0 track 6) along the Y-axis. In the present context, a metal line whose length dimension is smaller than the dimensions of the SRAM cell 100 (e.g., a dimension along the X-axis that is smaller than the cell width and a dimension along the Y-axis that is smaller than the cell height) is referred to as a local metal line, while a metal line whose length dimension is not smaller than the dimensions of the SRAM cell 100 (e.g., a dimension along the X-axis that is not smaller than the cell width along the X-axis or a dimension along the Y-axis that is not smaller than the cell height along the Y-axis) is referred to as a global metal line.

[0044] As FIG. 6As illustrated, the first metal track "M0 Track 1" includes a global metal line 510, which is a VSS line, disposed on and electrically coupled to the source / drain contact via 170G. The VSS line 510 is disposed on the upper edge of the SRAM cell 100 and can be shared by adjacent SRAM cells.

[0045] The second metal track "M0 Track 2" includes a local metal line 520 as a continuation pad for the write port word line W WL at a higher metal level. In the top view, the local metal line 520 is entirely within the boundary 190 of the SRAM cell 100. The local metal line 520 is disposed over and in direct contact with the gate via 150C and the gate via 150D.

[0046] The third metal track "M0 Track 3" includes 3 local metal lines 530A, 530B, and 530C. The local metal line 530A provides a continuation pad for the write port bit line W BLB at a higher metal level. In the top view, the local metal line 530A extends beyond the left edge of the SRAM cell 100 and can be shared by adjacent SRAM cells. In the top view, the local metal line 530B is entirely within the boundary 190 of the SRAM cell 100, which is a storage node (SN) and provides a cross-coupling between the gate via 150E and the source / drain contact via 170F. As mentioned above, the local metal line 530B crosses the gate structure 116 when viewed from the top. The local metal line 530C provides a continuation pad for the write port bit line W BL at a higher metal level. In the top view, the local metal line 530C extends beyond the right edge of the SRAM cell 100 and can be shared by adjacent SRAM cells.

[0047] The fourth metal track "M0 Track 4" includes 2 local metal lines 540A and 540B. In the top view, the local metal line 540A is entirely within the boundary 190 of the SRAM cell 100 and is electrically floating. Thus, the local metal line 540A is a non-functional metal line, primarily to improve uniformity of metal density in the layout. The local metal line 540B provides a continuation pad for the read port word line R WL at a higher metal level. In the top view, the local metal line 540B is entirely within the boundary 190 of the SRAM cell 100.

[0048] The fifth metal track, "M0 track 5," includes one local metal line 550. In the top view, the local metal line 550 is entirely within the boundary 190 of the SRAM cell 100, belongs to the complementary storage node (SNB), and provides cross-coupling between the gate via 150F and the source / drain contact via 170E. As noted above, the local metal line 550 crosses the gate structure 116 when viewed from the top. Each of the metal lines 520, 530A-530C, 540A-540B, 550, and 560 has the same width Wl along the Y axis.

[0049] The sixth metal track, "M0 track 6," includes a global metal line 560 electrically coupled to the source / drain contact via 170H, which is a VDD line. The VDD line 560 is disposed directly over the lower edge of the SRAM cell 100 and can be shared by adjacent SRAM cells. In the illustrated embodiment, the local metal lines in the M0 level (e.g., local metal lines 520, 530A, 530C, 540A-540B) have length dimensions along the X axis that are large enough to provide sufficient landing area for the vias over them (thereby minimizing the overlap problem and providing greater patterning flexibility). In the illustrated embodiment, the length dimensions of the landing pads at the M0 level are less than the dimensions of the SRAM cell 100, e.g., less than the cell width W along the X axis and less than the cell height H along the Y direction. In contrast to the landing pads, the length dimensions of the VSS line 510 and the VDD line 560 along the X axis are greater than the cell width of the SRAM cell 100.

[0050] Reference is now made to FIG. 2 The memory device 1000 also includes conductive features formed below the SRAM cell 100. As referenced above with respect to FIG. 4 and FIG. 9 to FIG. 10The depicted read port channel gate transistor R-PG has a source / drain feature 181 electrically coupled to the drains of transistors PU-2 and PD-2 and a source / drain feature 182 electrically connected to the read port bit line R BL. In this embodiment, to improve the design flexibility of the metal lines at the M0 level and to reduce leakage and coverage issues, as described above, instead of forming the read port bit line R BL and its subsequent pads above the device layer DL of the SRAM cell 100, a source / drain contact via 610 is formed directly underneath the source / drain feature 182 of the read port channel gate transistor R-PG to electrically connect the source / drain feature 182 to a metal line 620, which is the read port bit line R BL disposed underneath the source / drain contact via 610. The source / drain contact via 610 can be referred to as a backside contact via 610 or a backside contact via VB, and the metal line 620 can be referred to as a backside metal line 620 or a backside metal line BM0. By forming the backside contact via 610 and the read port bit line R BL (i.e., the backside metal line 620) underneath the source / drain and gate of the read port channel gate transistor R-PG, the leakage and shorting issues associated with the subsequent pads of the read port bit line R BL can be eliminated, the metal lines in the M0 level can be relaxed, and the design flexibility of the metal lines (including the subsequent pads) in the M0 level can be improved accordingly. In an embodiment, the metal line 620 is a global metal line and its length along the X-axis is greater than the cell width. The metal line 620 has a width W2 along the Y-axis. The ratio of the width W2 to the width Wl (i.e., W2 / Wl) can be in the range of about 0.3 to about 5. The N-type fin 102 has a width Dl along the Y-axis, and the P-type fin 104 has a width D2 along the Y-axis. The width D2 can be equal to or different from the width Dl. In some embodiments, the ratio of the width W2 to the width D2 (i.e., W2 / D2) can be in the range of about 0.3 to about 2. Referring to FIG. 7 The backside contact via 610 and the backside metal line 620 are described in more detail with reference to the depicted cross-sectional view of the memory device 1000.

[0051] Reference is now made to FIG. 7 , FIG. 7M0 level, a VI level, and an Ml level of a layout of a multilayer interconnect structure of the icon memory device 1000. At the VI level, the memory device 1000 includes a plurality of vias formed above and in direct contact with the M0 level. For example, the VI level of the memory device 1000 includes a via 710A formed above and in direct contact with the local metal line 530A, and the via 710A electrically couples the local metal line 530A to a complementary write port bit line W BLB at a higher metal interconnect layer. The VI level of the memory device 1000 also includes a via 710B formed above and in direct contact with the local metal line 520, and the via 710B electrically couples the local metal line 520 to a write port word line W WL at a higher metal interconnect layer. The VI level of the memory device 1000 also includes a via 710C formed above and in direct contact with the global metal line 510, and the via 710C electrically couples the global metal line 510 to a metal line at a higher metal interconnect layer. The VI level of the memory device 1000 also includes a via 710D formed above and in direct contact with the local metal line 540B, and the via 710D electrically couples the local metal line 540B to a read port word line R WL at a higher metal interconnect layer. The VI level of the memory device 1000 also includes a via 710E formed above and in direct contact with the local metal line 530C, and the via 710E electrically couples the local metal line 530C to a write port bit line W BL at a higher metal interconnect layer.

[0052] At the Ml level, the memory device 1000 includes a plurality of metal lines formed above the VI level. For example, the Ml level of the memory device 1000 includes a local metal line 720A formed above and in direct contact with the via 710A, and the local metal line 720A electrically couples the via 710A to a complementary write port bit line W BLB at a higher metal interconnect layer. The local metal line 720A can also be referred to as a continuation pad of the complementary write port bit line W BLB. The local metal line 720A can extend beyond the left edge of the SRAM cell 100 and can be shared by an adjacent SRAM cell.

[0053] The M1 level of the memory device 1000 also includes a global metal line 720B disposed on and electrically coupled to the via 710B, which is a write port word line W_WL. The write port word line W_WL can extend beyond the upper edge and / or lower edge of the SRAM cell 100 and can be shared between adjacent SRAM cells. The M1 level of the memory device 1000 also includes a global metal line 720C formed above and in direct contact with the via 710C. The M1 level of the memory device 1000 also includes a global metal line 720D disposed on and electrically coupled to the via 710D, which is a read port word line R_WL. The read port word line R_WL can extend beyond the upper edge and / or lower edge of the SRAM cell 100 and can be shared between adjacent SRAM cells. The M1 level of memory device 1000 includes a local metal line 720E formed above and in direct contact with via 710E. Local metal line 720E electrically couples via 710E to a write port bit line W_BL located at a higher metal interconnect layer. Local metal line 720E can also be referred to as a pad for write port bit line W_BL. Local metal line 720E can extend beyond the right edge of SRAM cell 100 and can be shared by adjacent SRAM cells.

[0054] like FIG. 7 As shown in the top view, all metal lines of the M1 level (including global metal lines 720B, 720C, 720D and local metal lines 720A, 720E) extend longitudinally along the Y axis. In an embodiment, since the read port bit line R_BL is placed at the back side of the memory cell and no bonding pad for the read port bit line R_BL is formed above the memory cell 100, as shown in FIG. FIG. 8 As shown, local metal line 720E may thus vertically overlap local metal line 540B.

[0055] Now refer to FIG. 8 , FIG. 8 FIG1 illustrates the layout of the multi-layer interconnect structure of memory device 1000, including the M1 level, the V2 level, and the M2 level. At the V2 level, memory device 1000 includes a plurality of vias formed above the M1 level. For example, the V2 level of memory device 1000 includes a via 810A formed above and in direct contact with local metal line 720A, and via 810A electrically couples local metal line 720A to a complementary write-port bit line W_BLB located at a higher metal interconnect level. The V2 level of memory device 1000 also includes a via 810B formed above and in direct contact with local metal line 720E, and via 810B electrically couples local metal line 720E to a write-port bit line W_BL located at a higher metal interconnect level.

[0056] At the M2 level, the memory device 1000 includes a plurality of metal lines formed above the V2 level. In this embodiment, the memory device 1000 includes a global metal line 820A formed above and directly contacting the via 810A, which is a complementary write port bit line W BLB. The memory device 1000 includes a global metal line 820B formed above and directly contacting the via 810B, which is a write port bit line W BL. The write port bit line W BL and the complementary write port bit line W BLB both extend lengthwise along the X-axis, can extend beyond the left and / or right edges of the SRAM cell 100, and can be shared by adjacent SRAM cells. In some prior art, a read port bit line R BL can be formed above the SRAM cell and also at the M2 level. Thus, in this embodiment, forming the read port bit line R BL below the SRAM cell can relax the design flexibility of the write port bit line W BL and the complementary write port bit line W BLB. For example, the width of the write port bit line W BL and the complementary write port bit line W BLB can be increased, the parasitic resistance can be reduced, and the write speed of the memory device can be advantageously improved.

[0057] Compared to embodiments in which the read port bit line R BL is formed above the SRAM cell (e.g., along with the write port bit line W BL and the complementary write port bit line W BLB at the M2 level), forming the read port bit line R BL below the SRAM cell can relax the design flexibility of the write port bit line W BL and the complementary write port bit line W BLB. For example, the width of the complementary write port bit line W BLB and the write port bit line W BL in this embodiment can be increased, thus the parasitic resistance can be reduced and the write speed of the memory device can be advantageously improved. In some embodiments, as shown in FIG. 7A, to reduce parasitic capacitance, the metal line 720A does not vertically overlap the write port bit line W BL, and the metal line 720E does not vertically overlap the complementary write port bit line W BLB. FIG. 9

[0058] FIG. 4 FIG. 8 illustrates a cross-sectional view of the memory device 1000 taken along line A-A’ in FIG. 7A and FIG. 7B, according to some embodiments consistent with the subject disclosure. FIG. 6 FIG. 10 FIG. 9 illustrates a cross-sectional view of the memory device 1000 taken along line B-B’ in FIG. 7A and FIG. 7B, according to some embodiments consistent with the subject disclosure. FIG. 4 to FIG. 6 FIG. 10 illustrates a cross-sectional view of the memory device 1000 taken along line B-B’ in FIG. 7A and FIG. 7B, according to some embodiments consistent with the subject disclosure. FIG. 9 FIG. 11 illustrates a cross-sectional view of the memory device 1000 taken along line B-B’ in FIG. 7A and FIG. 7B, according to some embodiments consistent with the subject disclosure. FIG. 9 to FIG. 10 ​​The cross-sectional views of the illustrated memory device 1000 are similar, and duplicate descriptions are omitted for the sake of brevity.

[0059] like FIG. 9 to FIG. 10 As shown, SRAM cell 100 (as part of memory device 1000) is formed on a substrate (or wafer) 902. In one embodiment, substrate 902 comprises silicon. Substrate 902 includes a plurality of p-wells (not shown) and n-wells (not shown) formed therein (and / or above) according to various design requirements of memory device 1000. The n-well is configured to provide at least one p-type field effect transistor (PFET), such as a pull-up transistor, and the p-well is configured to provide at least one n-type field effect transistor (NFET), such as a pull-down transistor or a pass-gate transistor. In some embodiments, substrate 902 may include additional doped regions configured to provide one or more transistors according to the design requirements of memory device 1000.

[0060] exist FIG. 10 In the embodiment shown, the transistors of the SRAM cell 100 (e.g., pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and channel gate transistors PG-1, PG-2, and R-PG) comprise GAA transistors, and the P-type fin 104 comprises a stack of semiconductor layers 908; similarly, the N-type fin 102 comprises a stack of semiconductor layers. In the illustrated embodiment, the semiconductor layers 908 are stacked vertically along the Z-axis. Each stack of semiconductor layers 908 of the P-type fin 104 is inserted between P-type source / drain (S / D) features 910P, and each stack of semiconductor layers of the N-type fin 102 is inserted between N-type source / drain (S / D) features 910N (shown in FIG. FIG. 10 ). The semiconductor layer 908 may include Si, Ge, SiC, SiGe, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof. In the present embodiment, each semiconductor layer 908 includes a nanosheet, a nanowire (e.g., a nanowire having a hexagonal cross-section), a nanorod (e.g., a nanorod having a square or circular cross-section), or other suitable structures. In some embodiments, the N-type fin 102 and the P-type fin 104 each include 2 to 10 channel layers 908. For example, the N-type fin 102 and the P-type fin 104 may each include 3 channel layers 908. Of course, the present invention is not limited to this configuration, and the number of semiconductor layers may be adjusted according to the design requirements of the memory device 1000.

[0061] The SRAM cell 100 further includes N-type source / drain features 910N (shown in FIG. 1 ) coupled to the channel layer of the N-type fin 102. FIG. 3) and P-type source / drain features 910P coupled to the channel layer of the P-type fin 104. The source / drain features can individually or collectively refer to either a source or a drain, depending on the context. Exemplary N-type source / drain features 910N can include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and can be in-situ doped during an epitaxy process by introducing an N-type dopant (e.g., phosphorus, arsenic, or antimony), or ex-situ doped using a junction implant process. Exemplary P-type source / drain features 910P can include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and can be in-situ doped during an epitaxy process by introducing a P-type dopant (e.g., boron or gallium), or ex-situ doped using a junction implant process. In some embodiments, the N-type source / drain features 910N and / or the P-type source / drain features 910P can each be a multi-layer structure including an undoped semiconductor layer, a lightly-doped semiconductor layer on the undoped semiconductor layer, and a heavily-doped semiconductor layer on the lightly-doped semiconductor layer.

[0062] In the present embodiment, each gate structure (including gate structures 112, 114, 116, 118, 120) includes at least a high-k gate dielectric layer (e.g., FIG. 3 The gate dielectric layer 76 shown) and a metal gate (e.g., FIG. 9The gate 74) is shown. In this embodiment, portions of the high-k gate dielectric surround each channel layer, such that each gate structure engages multiple channel layers (e.g., channel layers 908) in each GAA transistor. The high-k gate dielectric can include silicon oxynitride, aluminum silicon oxide, a high-k dielectric material such as hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate, other suitable dielectric materials, or combinations thereof. Although not shown, each metal gate can also include a bulk-conductive layer disposed above at least one work function metal layer. The bulk-conductive layer can include Cu, W, Ru, Co, Al, Ti, Ta, other suitable metals, or combinations thereof. In some examples, each gate structure can include one or more work function metal layers of the same conductivity type or different conductivity types. Examples of work function metal layers can include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function materials, or combinations thereof. The various work function metal layers can be deposited first and then patterned to meet different threshold voltage requirements in different GAA FETs. Additional material layers can also be included in each gate structure, such as an interface layer, a barrier layer, a capping layer, other suitable material layers, or combinations thereof. The various layers of the gate structure can be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, other suitable methods, or combinations thereof. The SRAM cell 100 can also include top spacers 912a and 912b and an inner spacer 912c disposed on the sidewalls of the gate structure, where the top spacers 912a and 912b are disposed above the channel layers 908 and the inner spacer 912c is disposed in the space between two of the vertically-stacked channel layers 908. As shown, the 7T SRAM cell 100 also includes a dielectric feature 110. The dielectric feature 110 can be formed by a continuous-poly-on-diffusion-edge (CPODE) process. In the CPODE process, at least a portion of the polysilicon gate and the channel region thereunder are replaced by a dielectric feature, and the remaining portion of the polysilicon gate can be replaced by a functional gate structure. For purposes of the present disclosure, a "diffusion edge" can be equated to an active edge, where the active edge, for example, abuts an adjacent active region. The dielectric feature 110 is also referred to as a CPODE feature 110. The CPODE feature 110 extends into the substrate 902. FIG. 9 to FIG. 10 As shown, the 7T SRAM cell 100 also includes a dielectric feature 110. The dielectric feature 110 can be formed by a continuous-poly-on-diffusion-edge (CPODE) process. In the CPODE process, at least a portion of the polysilicon gate and the channel region thereunder are replaced by a dielectric feature, and the remaining portion of the polysilicon gate can be replaced by a functional gate structure. For purposes of the present disclosure, a "diffusion edge" can be equated to an active edge, where the active edge, for example, abuts an adjacent active region. The dielectric feature 110 is also referred to as a CPODE feature 110. The CPODE feature 110 extends into the substrate 902.

[0063] Still referring to FIG. 9The memory device 1000 also includes a contact etch stop layer (CESL) 914 and a first interlayer dielectric (ILD) layer 916 deposited over the N-type source / drain features 910N and the P-type source / drain features 910P. The CESL 914 can include silicon nitride, silicon oxynitride, and / or other materials known in the art, and can be formed by an ALD, plasma-enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation process. After deposition of the CESL 914, the first ILD layer 916 can be deposited by a PECVD process or other suitable deposition technique. The first ILD layer 916 can include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The memory device 1000 also includes an etch stop layer 918 and a second interlayer dielectric (ILD) layer 920 deposited over the first ILD layer 916 and the gate structures (including the gate structures 112, 114, 116, 118, 120). The etch stop layer 918 and the second ILD layer 920 are formed and composed similarly to the CESL 914 and the first ILD layer 916, respectively.

[0064] Still referring to FIG. 10 and FIG. 10 The memory device 1000 includes source / drain contacts (including the source / drain contacts 160E, 160H, 160F) extending through the etch stop layer 918, the first ILD layer 916, the second ILD layer 920, and the CESL 914. Each front-side source / drain contact (including the source / drain contacts 160E, 160H, 160F) is formed over a respective source / drain feature and is electrically coupled to the respective source / drain feature via a silicide layer 922. The source / drain contacts (including the source / drain contacts 160E, 160H, 160F) can include any suitable conductive material, such as Cu, W, Ru, Co, Al, Ti, Ta, other suitable metals, or combinations thereof, and can also include a barrier layer including any suitable material, such as Ti, Ta, TiN, TaN, other suitable materials, or combinations thereof. In some embodiments, the silicide layer 922 can include nickel silicide, titanium silicide, cobalt silicide, other suitable silicides, or combinations thereof.

[0065] Referring to FIG. 9 to FIG. 10Memory device 1000 includes an interconnect structure 924. Interconnect structure 924 includes a source / drain contact via 170H connected to source / drain contact 160H at the V0 level. Interconnect structure 924 also includes a source / drain contact via 170G connected to source / drain contact 160G at the V0 level. Interconnect structure 924 also includes a VSS line 510 disposed on source / drain contact via 170G at the M0 level, metal lines 520, 530B, 540A, and 550 disposed on a dielectric layer (e.g., a low-k dielectric material, silicon oxide, or other suitable dielectric material) at the M0 level, and a VDD line 560 disposed on source / drain contact via 170H at the M0 level.

[0066] In order to increase the design flexibility of the metal lines at the M0 level and alleviate the leakage and overlap problems, the read port bit line R_BL of the memory device 1000 is set below the SRAM cell 100. FIG. 9 As shown, the memory device 1000 includes a backside contact via 610 disposed below the source / drain features of the SRAM cell 100. More specifically, the backside contact via 610 is disposed below the source / drain features 182 of the read port channel gate transistor R-PG of the SRAM cell 100. A silicide layer 926 is disposed between the backside contact via 610 and the source / drain features 182 of the read port channel gate transistor R-PG. In other words, the backside contact via 610 is electrically connected to the source / drain features 182 of the read port channel gate transistor R-PG through the silicide layer 926. The composition of the silicide layer 926 may be similar to that of the silicide layer 922.

[0067] The memory device 1000 includes a backside metal line 620 disposed below the source / drain features 182 of the read port pass-gate transistor R-PG of the SRAM cell 100, which is the read port bit line R_BL. FIG. 9 to FIG. 10 As shown, the backside metal line 620 is disposed below the backside contact via 610 and is in direct contact with the backside contact via 610. The memory device 1000 further includes a dielectric liner 928. In some embodiments, the dielectric liner 928 may include silicon nitride or other suitable materials. FIG. 10 In the illustrated embodiment, the dielectric liner 928 includes a first portion that is in direct contact with the backside contact via 610 and a second portion that is in direct contact with the backside metal line 620. In other words, the backside contact via 610 and the backside metal line 620 are physically and electrically isolated from the substrate 902 by the dielectric liner 928. The backside metal line 620 is embedded in the dielectric layer 930 (shown in FIG. FIG. 11). The dielectric layer 930 may be similar to the first ILD layer 916. The backside metal line 620 has a thickness T1 along the Z axis, and the metal lines at the M0 level (including metal lines 510-550) each have a thickness T2 along the Z axis. Since the backside metal line 620 is formed below the SRAM cell 100 rather than above the SRAM cell 100, the size of the backside metal line 620 can be flexibly adjusted to achieve satisfactory performance. In other words, the parasitic capacitance and parasitic resistance of the memory device 1000 can be optimized by adjusting the size (e.g., width, thickness) of the backside metal line 620. For example, the width W2 of the backside metal line 620 can be adjusted to provide a satisfactory parasitic capacitance. In some embodiments, the ratio of the width W2 to the width D2 can be in a range between about 0.3 and about 2. In one embodiment, the ratio of the thickness T1 to the thickness T2 (i.e., T1 / T2) is in a range between about 1.5 and about 3. Due to this thickness relationship, the critical dimensions of the metal lines at the M0 level (including metal lines 510-550) can be reduced without substantially changing the overall parasitic resistance of the memory device 1000, since the thicker backside metal lines 620 provide reduced parasitic resistance. In other words, by forming the read port bit line R_BL on the backside of the SRAM cell 100, the dimensions of the metal lines at the M0 level (including metal lines 510-550) can be further reduced to accommodate future cell size reductions.

[0068] FIG. 2 The diagram shows some embodiments according to the present invention. FIG. 11 Alternative layouts of a portion or the entire memory device 1000 of an SRAM cell. FIG. 4 The layout of the memory device 1000 is shown in FIG. FIG. 11 The layout shown is similar, with one difference including FIG. 12 The illustrated memory device 1000 does not include dummy source / drain contacts 160A and 160B.

[0069] FIG. 12 The diagram shows the layout of each layer of a portion or the entirety of a memory device 2000 according to various aspects of the present invention. FIG. 4 As shown, the memory device 2000 includes two SRAM cells. For example, the memory device 2000 includes an SRAM cell 100A and an SRAM cell 100C. The layout of the SRAM cell 100A is basically the same as that of the reference cell 100. FIG. 6The layout of the SRAM cell 100 is identical to that of the SRAM cell 100, and the layout of the SRAM cell 100C is a mirror image of the layout of the SRAM cell 100A about the X-axis. The SRAM cell 100C includes pull-up transistors PU-1′ and PU-2′ formed by gate structures 112′, 114′, 116′, 118′, and 120′ and N-type fins 102′ and P-type fins 104′, pull-down transistors PD-1′ and PD-2′, pass-gate transistors PG-1′ and PG-2′, and a read port pass-gate transistor R-PG′.

[0070] The memory device 2000 includes a backside contact via 610 and a backside metal line 620 formed below the SRAM cell 100A, as described above with reference to FIG. FIG. 12 As described. Similarly, the memory device 2000 includes a backside contact via 610' and a backside metal line 620' formed below the SRAM cell 100C. The backside contact via 610' and the backside metal line 620' are similar to the backside contact via 610 and the backside metal line 620, respectively. That is, the backside contact via 610' is disposed directly below and electrically coupled to the source / drain features of the read port channel gate transistor R-PG', and the backside metal line 620' is disposed directly below and in direct contact with the backside contact via 610'.

[0071] exist FIG. 13 In the illustrated embodiment, each of the backside metal lines 620 and 620' extends lengthwise along the X-axis and has a uniform width. When viewed from the top, each of the backside metal lines 620 and 620' has a rectangular shape. The backside metal line 620 is separated from the backside metal line 620' by a distance S1. In some embodiments, the ratio of the distance S1 to the width D1 of the N-type fin 102 (i.e., S1 / D1) is in a range between approximately 0.3 and approximately 3. Each of the backside metal lines 620 and 620' also vertically overlaps the CPODE features 110 / 110', gate structures 114 / 114', 116 / 116', and 118 / 118', respectively. The layout of the C0 level, V0 level, M0 level, V1 level, M1 level, V2 level, and M2 level of the memory device 2000 includes a first portion substantially identical to that of the memory device 1000 and a second portion that is a mirror image of the first portion with respect to the X-axis. For the sake of brevity, repeated descriptions are omitted.

[0072] FIG. 14 、 FIG. 15 and FIG. 12 Illustrations of various aspects of the present invention FIG. 13 An alternative layout of the various layers of the memory device 2000, in part or in whole.FIG. 14 , FIG. 15 and FIG. 12 The layout of the memory device 2000 as represented by FIG. 12 to FIG. 15 is similar to the layout of the memory device 2000 as represented by FIG. 12 for clarity and brevity, like features in the illustrated embodiments as shown by are labeled with the same reference numbers, and such similar aspects are not described again.

[0073] FIG. 13 to FIG. 15 and FIG. 13 to FIG. 15 One difference between the layouts in FIG. 12 and FIG. 12 is the shape of the top view of the backside metal lines 620 and 620' in FIG. 13 to FIG. 15 . More specifically, unlike the backside metal lines 620 / 620' in FIG. 13 to FIG. 15 which have a rectangular shape and uniform width, the backside metal lines 620 / 620' in FIG. 13 to FIG. 15 have a non-uniform width. FIG. 12 The backside metal lines 620 / 620' in include a main portion 1200a that extends lengthwise along the X-axis and has a uniform width D3, and an edge portion 1200b that protrudes from the main portion 1200a along the Y-axis. That is, the backside metal lines 620 / 620' in

[0074] have a non-uniform width from left to right. In one embodiment, the ratio of the width D3 to the width Dl of the N-type fin 102 / 102' is between about 0.3 and about 3. FIG. 13 to FIG. 15 FIG. 13 The main portion 1200a of the backside metal line 620 is spaced apart from the main portion 1200a of the backside metal line 620' by a distance S2. In one embodiment, to significantly reduce the parasitic capacitance of the memory device, the ratio of the distance S2 to the distance SI (shown in FIG. 13 to FIG. 15 ) is greater than 5. In the present embodiment as represented by , to further reduce the parasitic capacitance of the memory device 2000, the main portion 1200a of the backside metal line 620 / 620' is placed directly over the center of the SRAM cell 100A / 100C. In other words, as shown from the top, the distance S3 between the centerline of the backside metal line 620 / 620' (represented by the dashed line 620c) and the N-type fin 102 / 102' is substantially equal to the distance S4 between the centerline of the backside metal line 620 / 620' and the P-type fin 104 / 104'.

[0075] FIG. 13 to FIG. 15 The edge portion 1200b of the backside metal line 620 / 620' is formed under and in direct contact with the backside contact via 610 / 610'. InIn the illustrated embodiment, the edge portion 1200b has a width D4 along the Y-axis, and the ratio of the width D4 to the width D2 is in a range between about 0.3 and about 3. As FIG. 14 As shown, the edge portion 1200b of the backside metal line 620 vertically overlaps with the P-type fin 104 portion. In some embodiments, the ratio of the width D5 of the portion of the edge portion 1200b formed directly below the P-type fin 104 (as shown) to the width D2 is in a range between about 0.3 and about 1. FIG. 13 to FIG. 15

[0076] FIG. 13 Three different positional relationships between the edge portion 1200b and the backside contact via 610 / 610’ are illustrated. More specifically, in FIG. 14 In the illustrated embodiment, the bottom edge 1200e of the edge portion 1200b of the backside metal line 620 is aligned with the bottom edge 610e of the backside contact via 610 when viewed from the top, with the SRAM cell 100A as an example. In FIG. 15 In the illustrated embodiment, the bottom edge 1200e of the edge portion 1200b of the backside metal line 620 is not aligned with the bottom edge 610e of the backside contact via 610, and the edge portion 1200b vertically overlaps with the backside contact via 610 portion of the SRAM cell 100A. In FIG. 4 to FIG. 15 In the illustrated embodiment, the bottom edge 1200e of the edge portion 1200b of the backside metal line 620 is not aligned with the bottom edge 610e of the backside contact via 610, and the backside contact via 610 of the SRAM cell 100A is completely vertically overlapped by the edge portion 1200b of the backside metal line 620. That is, the edge portion 1200b extends beyond the backside contact via 610 when viewed from the top.

[0077] In the above-described embodiments described with reference to FIG. 16 In the above-described embodiments described with reference to ​ is a circuit diagram of an 8T SRAM cell 100’ that can be implemented in the IC chip of FIG. 1 in accordance with various aspects of the present disclosure. The 8T SRAM cell 100’ is similar to the 7T SRAM cell 100, with one difference between the two SRAM cells being that the 8T SRAM cell 100’ includes another read port channel gate transistor R-PG2. The read port bit line R BL of a memory device including the 8T SRAM cell 100’ can be formed below the 8T SRAM cell 100’.

[0078] ​While not intending to be limited, one or more embodiments of the present inventive subject matter provide a number of benefits for memory devices and formation thereof. However, it should be understood that other embodiments can provide additional benefits, and that not all embodiments necessarily exhibit the same advantages, and that certain advantages can be exhibited by both all embodiments and certain embodiments. For example, the present inventive subject matter provides a memory device that includes an SRAM cell and a read port bit line disposed below the SRAM cell. Forming the read port bit line disposed below the SRAM cell relaxes design flexibility for front side conductive features (e.g., metal lines) formed above the SRAM cell, mitigates leakage and shorting issues associated with the front side conductive features, and provides scaling capability to accommodate device fabrication at advanced technology nodes. In some embodiments, forming the read port bit line disposed below the SRAM cell allows for reduction of parasitic capacitance and parasitic resistance of the memory device, thereby improving overall performance.

[0079] The present inventive subject matter provides a number of different embodiments. Disclosed herein are semiconductor structures and methods of manufacturing the same. In one exemplary aspect, the present inventive subject matter is directed to a semiconductor structure. The semiconductor structure includes a two-port static random access memory (SRAM) cell including a write port portion and a read port portion, the read port portion electrically coupled to the write port portion and including a transistor having a first source / drain feature and a second source / drain feature. The semiconductor structure further includes a first plurality of metal lines including a write bit line and a complementary write bit line, wherein the first plurality of metal lines are at a first metal interconnect layer, wherein the first metal interconnect layer is above the first source / drain feature, and a read bit line at a second metal interconnect layer, wherein the second metal interconnect layer is below the first source / drain feature.

[0080] In some embodiments, the semiconductor structure further includes a first silicide layer located below and directly contacting a first source / drain feature of the transistor and a first via located below and directly contacting the first silicide layer, wherein the second metal interconnect layer is located below and directly contacting the first via. In some embodiments, the semiconductor structure further includes a first source / drain contact located directly above the first source / drain feature of the transistor. In some embodiments, the semiconductor structure further includes a second silicide layer located above and directly contacting a second source / drain feature of the transistor and a second source / drain contact located directly above and electrically coupled to the second source / drain feature of the transistor. In some embodiments, the transistor can include a vertical stack of nanos structures located between the first source / drain feature and the second source / drain feature and a gate structure that wraps each nanos structure of the vertical stack of nanos structures and extends lengthwise along a first direction. The second metal interconnect layer can extend lengthwise along a second direction substantially perpendicular to the first direction. In some embodiments, the semiconductor structure can further include a gate via electrically coupled to the gate structure, a read word line next pad located in a third metal interconnect layer and electrically coupled to the gate via, and a read word line located in a fourth metal interconnect layer and electrically coupled to the read word line next pad, wherein the fourth metal interconnect layer can be located between the third metal interconnect layer and the first metal interconnect layer. In some embodiments, a ratio of a thickness of the second metal interconnect layer to a thickness of the third metal interconnect layer can be in a range between 1.5 and 3. In some embodiments, the read bit line can include a main portion extending lengthwise along the first direction and an end portion extending lengthwise along a second direction substantially perpendicular to the first direction, the end portion can at least partially vertically overlap the first source / drain feature of the transistor. In some embodiments, the read bit line can include a uniform width and in a top view, a shape of the read bit line can include a rectangular shape.

[0081] In another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a memory cell coupled to a read bit line and a write bit line, a first interconnect structure located above the memory cell and including the write bit line, and a second interconnect structure located below the memory cell and including the read bit line.

[0082] In some embodiments, the memory cell includes a first active region and a second active region extending lengthwise along a first direction, and a first gate structure and a second gate structure extending lengthwise along a second direction perpendicular to the first direction. The first gate structure is joined with the first active region to form an N-type transistor, and a source / drain feature of the N-type transistor is electrically coupled to a write bit line, and the second gate structure is joined with the second active region to form a P-type transistor, where an edge of the second gate structure is aligned with an edge of the first gate structure along the second direction, and a source / drain feature of the P-type transistor is electrically coupled to a read bit line. In some embodiments, the second interconnect structure can include a contact via located directly below the source / drain feature of the P-type transistor, and a metal interconnect layer located below the contact via and in direct contact with the contact via. The read bit line can be located at the metal interconnect layer. In some embodiments, the read bit line can include a main portion extending lengthwise along the first direction and an end portion protruding from the main portion along the second direction, and the end portion is in direct contact with the contact via. In some embodiments, in a top view, a distance between the main portion and the first active region can be substantially equal to a distance between the main portion and the second active region. In some embodiments, in a top view, the read bit line can extend completely through the memory cell. In some embodiments, the read bit line can have a uniform width.

[0083] In yet another example aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes a memory cell including a write port portion and a read port portion, the read port portion including a transistor having a first source / drain feature and a second source / drain feature, where the first source / drain feature is electrically connected to the write port portion. The semiconductor structure further includes a contact via located directly below the second source / drain feature and electrically coupled to the second source / drain feature, and a first metal interconnect layer located below the contact via and in direct contact with the contact via, where a read bit line is located at the first metal interconnect layer.

[0084] In some embodiments, the memory cell is connected to a first power line for receiving a first power voltage and a second power line for receiving a second power voltage, the first power line and the second power line can be located at a second metal interconnect layer above the first source / drain feature.

[0085] In some embodiments, the memory cell can include a seven-transistor static random access memory (SRAM) cell. In some embodiments, the memory cell can include an eight-transistor static random access memory (SRAM) cell.

[0086] Finally, it should be noted that: the above embodiments are used to illustrate the technical solutions of the present application, but not limited to them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that include: A two-port static random access memory cell comprising: Write port section; and a read port portion electrically coupled to the write port portion and comprising a transistor having first source / drain characteristics and second source / drain characteristics; a first plurality of metal lines comprising a write bit line and a complementary write bit line, wherein the first plurality of metal lines is located at a first metal interconnect layer, wherein the first metal interconnect layer is located above the first source / drain feature; and A read bit line is located at a second metal interconnect layer, wherein the second metal interconnect layer is located below the first source / drain feature.

2. The semiconductor structure according to claim 1, wherein: The transistor further includes: a vertical stack of nanostructures between the first source / drain feature and the second source / drain feature; and a gate structure covering each nanostructure of the vertical stack of nanostructures and extending longitudinally along a first direction, The second metal interconnection layer extends longitudinally along a second direction perpendicular to the first direction.

3. The semiconductor structure according to claim 2, wherein: Also includes: a gate via electrically coupled to the gate structure; a read word line pad located in the third metal interconnect layer and electrically coupled to the gate via; as well as A read word line is located in a fourth metal interconnection layer and electrically coupled to the read word line pad, wherein the fourth metal interconnection layer is located between the third metal interconnection layer and the first metal interconnection layer.

4. The semiconductor structure according to claim 1, wherein: The read bit line includes a main portion extending lengthwise along a first direction and an end portion extending lengthwise along a second direction perpendicular to the first direction, wherein the end portion at least partially vertically overlaps the first source / drain feature of the transistor.

5. A memory device, characterized in that: include: a memory cell connected to a read bit line and a write bit line; a first interconnect structure located above the memory cell and including the write bit line; as well as A second interconnect structure is located below the memory cell and includes the read bit line.

6. The memory device according to claim 5, wherein: The memory cell comprises: The first active region and the second active region extend longitudinally along a first direction; and The first gate structure and the second gate structure extend longitudinally in a second direction perpendicular to the first direction. wherein the first gate structure is joined to the first active region to form an N-type transistor, and the source / drain features of the N-type transistor are electrically coupled to the write bit line, and The second gate structure is joined to the second active region to form a P-type transistor, wherein an edge of the second gate structure is aligned with an edge of the first gate structure along the second direction, and the source / drain features of the P-type transistor are electrically coupled to the read bit line.

7. The memory device according to claim 6, wherein: The second interconnect structure includes a contact via located directly below the source / drain features of the P-type transistor and a metal interconnect layer located below and in direct contact with the contact via, wherein the read bit line is located at the metal interconnect layer.

8. The memory device according to claim 7, wherein: The read bit line includes a main portion extending longitudinally along the first direction and an end portion protruding from the main portion along the second direction, and the end portion is in direct contact with the contact via.

9. A semiconductor structure, characterized in that include: Memory cells, including: Write port section; and a read port portion comprising a transistor having first source / drain characteristics and second source / drain characteristics, wherein the first source / drain characteristics are electrically connected to the write port portion; a contact via directly beneath and electrically coupled to the second source / drain feature; and A first metal interconnection layer is located below the contact via and in direct contact with the contact via, wherein a read bit line is located at the first metal interconnection layer.

10. The semiconductor structure according to claim 9, wherein: The memory cell is connected to a first power line for receiving a first power supply voltage and a second power line for receiving a second power supply voltage, wherein the first power line and the second power line are located at a second metal interconnect layer above the first source / drain feature.

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