TBC battery with locally doped back surface

Abstract

The utility model discloses a TBC battery with a locally doped back surface, which belongs to the field of TBC batteries, and is characterized in that spacer regions are arranged on the back surface of a silicon wafer alternately, P + regions and N + regions are arranged between the P + regions and the N + regions, P + + heavily doped polycrystalline silicon layers and P + lightly doped polycrystalline silicon layers are arranged in the P + regions, or N + + heavily doped polycrystalline silicon layers and N + lightly doped polycrystalline silicon layers are arranged in the N + regions; according to the invention, the photoelectric conversion efficiency of the TBC cell can be effectively improved, the process is relatively simple, the cost increase is less, and the control difficulty is low.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of TBC battery, specifically, relate to a back partial doping's TBC battery. BACKGROUND

[0002] At present, a new generation of battery technology is rising rapidly, among which the back contact battery (BC battery) is widely recognized by the industry due to its significant efficiency advantage, and through continuous evolution and improvement, it has been recognized as the main path of high-efficiency photovoltaic cell technology.

[0003] The front of the BC battery structure is not blocked by the grid line, thereby increasing the light receiving area and improving the utilization rate of incident light. Therefore, in the past 50 years, BC battery has always maintained a clear advantage in conversion efficiency. In terms of process compatibility, BC process is an open and highly scalable process that can be combined with TOPCon, HJT and other processes to further optimize the passivation structure, fully utilize the front surface and continuously improve the conversion efficiency of the battery. Among them, TBC battery combines the high short-circuit current of IBC and the excellent passivation contact characteristics of TOPCon, improves the conversion efficiency through good passivation structure, and opens up a new road for the future development of BC battery.

[0004] The diffusion of the P region and the N region of the current TBC battery is mostly carried out in a diffusion furnace, which utilizes the principle of thermal diffusion to make impurity atoms diffuse into the crystalline silicon body under heat. However, the diffusion furnace heats the entire surface of the battery piece, and cannot heat specified local areas. Therefore, the doping concentration and diffusion depth of the entire plane of the battery piece are the same. However, for photovoltaic cells, a high impurity concentration at the contact between the metal electrode and the doped layer can reduce the contact resistance, but the Auger recombination rate of the battery increases, reducing the battery efficiency. If the impurity concentration is too low, it will cause the contact resistance between the metal and the doped layer to be too large, increasing the electrical loss. Therefore, the ideal situation is to heavily dope the area where the metal and the doped layer are in contact, and lightly dope other areas, i.e. selective doping (SE). Laser not only has a high-energy light beam that can heat impurity sources and promote impurity particles to diffuse into the crystalline silicon, but also can precisely locate and apply different energies to different areas to control impurity concentration and diffusion depth, achieving selective doping. In order to further improve the conversion efficiency of the battery, the industry has proposed various advanced laser technologies, such as laser SE, laser-induced sintering (LIF), etc. Therefore, the utility model combines laser SE with BC battery to adjust the structure of the battery, which can further improve the conversion efficiency of TBC battery.

[0005] Therefore, the utility model person carries out the in-depth research in view of this demand, and then has the case. UTILITY MODEL CONTENT

[0006] In order to improve the photoelectric conversion efficiency of TBC cells, the utility model provides a TBC cell with local doping on the back side. On the basis of the existing BC cell structure and equipment, SE technology is added to form a heavily doped area, and the other areas are lightly doped areas. While improving the efficiency, the process is relatively simple, the cost increase is small, and the control difficulty is low. The SE technology is effectively applied to the back side of the BC cell to improve the cell efficiency.

[0007] In order to achieve the purpose of this utility model, the following technical solutions are adopted:

[0008] The utility model provides a TBC cell with local back doping, comprising a crystalline silicon substrate, wherein the front side of the crystalline silicon substrate includes, from the inside to the outside, a front passivation layer and a front anti-reflection layer; the back surface of the crystalline silicon substrate is provided with a P+ region and an N+ region arranged alternately, and a spacing region is provided between the P+ region and the N+ region; the P+ region includes, from the inside to the outside, a dielectric layer, a P+ doped polysilicon layer, a back anti-reflection layer and a first electrode on the back surface of the crystalline silicon substrate; the N+ region includes, from the inside to the outside, a dielectric layer, an N+ region doped polysilicon layer, a back anti-reflection layer and a second electrode on the back surface of the crystalline silicon substrate; the N+ region doped polysilicon layer includes an N+ lightly doped polysilicon layer and an N++ heavily doped polysilicon layer, and the surface concentration of the N++ heavily doped polysilicon layer is greater than the surface concentration of the N+ lightly doped polysilicon layer; the first electrode penetrates the back anti-reflection layer to form an ohmic contact with the P+ doped polysilicon layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the N++ heavily doped polysilicon layer.

[0009] Preferably, the N++ heavily doped polysilicon layer is inside the N+ lightly doped polysilicon layer, and the volume of the N++ heavily doped polysilicon layer accounts for 2% to 70% of the volume of the N+ lightly doped polysilicon layer.

[0010] More preferably, the volume of the N++ heavily doped polysilicon layer accounts for 2% to 55% of the volume of the N+ lightly doped polysilicon layer.

[0011] Preferably, the junction depth of the N+ region is 0.05-0.5 μm; the ECV surface concentration of the N+ lightly doped polysilicon layer is 2E19-4E20 cm -3 , the square resistance is 30~400Ω; the ECV surface concentration of the N++ heavily doped polysilicon layer is 2E20~1E21cm -3 , the square resistance is 20~60Ω.

[0012] Preferably, the junction depth of the P+ region is 0.1-0.5 μm; the ECV surface concentration of the P+ doped polysilicon layer is 2E19-5E20 cm -3 , the square resistance is 20~400Ω.

[0013] Preferably, the N+ region comprises, from inside to outside, the dielectric layer, the N+ region doped polysilicon layer, the back passivation layer, the back anti-reflection layer and the second electrode on the back surface of the crystalline silicon substrate; the N+ region doped polysilicon layer comprises the N+ lightly doped polysilicon layer and the N++ heavily doped polysilicon layer, and the surface concentration of the N++ heavily doped polysilicon layer is greater than that of the N+ lightly doped polysilicon layer; the second electrode forms an ohmic contact with the N++ heavily doped polysilicon layer through the back anti-reflection layer and the back passivation layer.

[0014] Preferably, the thickness of the front passivation layer and the back passivation layer is 1-10 nm.

[0015] Preferably, the thickness of the front anti-reflection layer and the back anti-reflection layer is 20-200 nm.

[0016] The utility model also provides a kind of preparation method of the above-mentioned back local doping TBC battery, comprising the following steps:

[0017] Step one, N / P type silicon wafer is put into tank type alkali solution and is polished;

[0018] Step two, the P+ region is formed: first form the dielectric layer on the back of silicon wafer, then form an amorphous silicon layer or a polysilicon layer or an amorphous silicon and polysilicon mixed layer on the dielectric layer, then carry out boron doping, to obtain the P+ doped polysilicon layer;

[0019] Step three, the P+ region is partially removed;

[0020] Step four, the N+ region is formed: first form the dielectric layer on the back of silicon wafer, then form an amorphous silicon layer or a polysilicon layer or an amorphous silicon and polysilicon mixed layer on the dielectric layer, then carry out phosphorus doping, to obtain the N+ lightly doped polysilicon layer;Then, with the PSG on the surface of the N+ lightly doped polysilicon layer as doping source, phosphorus source is secondly pushed, and under local heat treatment, the N++ heavily doped polysilicon layer is formed in the N+ lightly doped polysilicon layer;

[0021] Step five, the N+ region above P+ region and the part of N+ region adjacent to P+ region above P+ region are partially removed;

[0022] Step six, the front of silicon wafer is textured to form pyramid structure;

[0023] Step seven, the front passivation layer is deposited on the front of silicon wafer or the front passivation layer and the back passivation layer are deposited on the front and back of silicon wafer respectively;

[0024] Step eight, depositing the front surface anti-reflective layer and the back surface anti-reflective layer on the front and back surfaces of the silicon wafer respectively;

[0025] Step nine, preparing the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0026] Preferably, the local heat treatment in step four includes two ways, the first way is to locally heat the PSG on the surface of the N+ lightly doped polysilicon layer by laser, and then to perform heat treatment promotion, the temperature is 850-960℃, the time is 10-60min, and the N++ heavily doped polysilicon layer is formed in the N+ lightly doped polysilicon layer; the second way is to remove part of the PSG on the surface of the N+ lightly doped polysilicon layer by local cleaning, to perform heat treatment by taking the PSG which is not removed as a doping source, the temperature is 850-960℃, the time is 10-60min, and the N++ heavily doped polysilicon layer is formed in the N+ lightly doped polysilicon layer.

[0027] Preferably, the power of the laser in the laser doping technology in step four is 1-70W, the wavelength is 300-700nm, the scanning speed is 5000-60000mm / s, and the frequency is 200-2000kHz.

[0028] The utility model also provides a kind of TBC battery of back surface local doping, including crystalline silicon substrate, the front surface of the crystalline silicon substrate includes front surface passivation layer and front surface anti-reflection layer from inside to outside in proper order;The back surface of the crystalline silicon substrate is provided with the P+ region and N+ region alternately arranged and there is interval region between the P+ region and the N+ region, the N+ region includes dielectric layer, N+ doped polysilicon layer, back surface anti-reflection layer and first electrode from inside to outside in proper order on the back surface of the crystalline silicon substrate, the P+ region includes dielectric layer, P+ region doped polysilicon layer, back surface anti-reflection layer and second electrode from inside to outside in proper order on the back surface of the crystalline silicon substrate;The P+ region doped polysilicon layer includes P+ lightly doped polysilicon layer and P++ heavily doped polysilicon layer, the surface concentration of the P++ heavily doped polysilicon layer is greater than the surface concentration of the P+ lightly doped polysilicon layer;The first electrode penetrates the back surface anti-reflection layer and the N+ doped polysilicon layer and forms ohmic contact, and the second electrode penetrates the back surface anti-reflection layer and the P++ heavily doped polysilicon layer and forms ohmic contact.

[0029] Preferably, the P++ heavily doped polysilicon layer is in the P+ lightly doped polysilicon layer, and the volume of the P++ heavily doped polysilicon layer accounts for 2%-70% of the P+ lightly doped polysilicon layer.

[0030] More preferably, the volume of the P++ heavily doped polysilicon layer accounts for 2%-55% of the P+ lightly doped polysilicon layer.

[0031] Preferably, the junction depth of the P+ region is 0.05-0.5 μm; the ECV surface concentration of the P+ lightly-doped polysilicon layer is 2E19-5E20 cm -3 , and the sheet resistance is 20-400 Ω; the ECV surface concentration of the P++ heavily-doped polysilicon layer is 2E20-8E20 cm -3 , and the sheet resistance is 20-80 Ω.

[0032] Preferably, the junction depth of the N+ region is 0.1-0.5 μm, and the ECV surface concentration of the N+ doped polysilicon layer is 2E19-4E20 cm -3 , and the sheet resistance is 30-400 Ω.

[0033] Preferably, the P+ region is sequentially provided with the dielectric layer, the P+ region doped polysilicon layer, the back passivation layer, the back anti-reflection layer and the second electrode from inside to outside on the back surface of the crystalline silicon substrate; the P+ region doped polysilicon layer comprises the P+ lightly-doped polysilicon layer and the P++ heavily-doped polysilicon layer, the surface concentration of the P++ heavily-doped polysilicon layer is greater than that of the P+ lightly-doped polysilicon layer; the second electrode forms an ohmic contact with the P++ heavily-doped polysilicon layer by penetrating the back anti-reflection layer and the back passivation layer.

[0034] Preferably, the thickness of the front passivation layer and the back passivation layer is 1-10 nm.

[0035] Preferably, the thickness of the front anti-reflection layer and the back anti-reflection layer is 20-200 nm.

[0036] The utility model also provides a preparation method of the back local doping TBC battery, which comprises the following steps:

[0037] Step one, put the N / P type silicon wafer into a tank type alkali solution for polishing;

[0038] Step two, form the N+ region: first form the dielectric layer on the back surface of the silicon wafer, then form an amorphous silicon layer or a polysilicon layer or an amorphous silicon and polysilicon mixed layer on the dielectric layer, and then perform phosphorus doping to obtain the N+ doped polysilicon layer;

[0039] Step three, locally remove the N+ region;

[0040] Step four, the P+ region is formed: first, forming the dielectric layer on the back of the silicon wafer, then forming an amorphous silicon layer or a polysilicon layer or a mixed layer of amorphous silicon and polysilicon on the dielectric layer, and then performing boron doping to obtain the P+ lightly doped polysilicon layer; and then taking the BSG on the surface of the P+ lightly doped polysilicon layer as a doping source, and performing secondary boron source pushing, and forming the P++ heavily doped polysilicon layer in the P+ lightly doped polysilicon layer under local heat treatment;

[0041] Step five, partially removing the P+ region above the N+ region and the adjacent part of the p+ region above the N+ region;

[0042] Step six, performing texturing on the front surface of the silicon wafer to form a pyramid structure;

[0043] Step seven, depositing the front passivation layer on the front surface of the silicon wafer or depositing the front passivation layer and the back passivation layer on the front and back surfaces of the silicon wafer respectively;

[0044] Step eight, depositing the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer respectively;

[0045] Step nine, preparing the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0046] Preferably, the local heat treatment in step four includes two modes, the first mode is to perform local laser heating on the BSG on the surface of the P+ lightly doped polysilicon layer by using a laser, and then performing heat treatment pushing, the temperature is 850-960 DEG C, the time is 10-60 min, and the P++ heavily doped polysilicon layer is formed in the P+ lightly doped polysilicon layer; the second mode is to remove part of the BSG on the surface of the P+ lightly doped polysilicon layer by local cleaning, taking the remaining BSG as a doping source, and performing heat treatment, the temperature is 850-960 DEG C, the time is 10-60 min, and the P++ heavily doped polysilicon layer is formed in the P+ lightly doped polysilicon layer.

[0047] Preferably, the power of the laser in the laser doping technology in step four is 1-70 W, the wavelength is 300-700 nm, the scanning speed is 5000-60000 mm / s, and the frequency is 200-2000 kHz.

[0048] The beneficial effects of the technical scheme of the utility model are as follows:

[0049] (1)The utility model discloses a N++ heavy doped polysilicon layer and N+ light doped polysilicon layer are arranged in N+ area, make P+ area and N++ heavy doped polysilicon layer more wide apart, and when N+ light doped polysilicon layer concentration is lower, can reduce the electric leakage, and the parallel resistance is higher, improves the fill factor, promotes open circuit voltage. Similarly, through setting P++ heavy doped polysilicon layer and P+ light doped polysilicon layer in P+ area, make N+ area and P++ heavy doped polysilicon layer more wide apart, and when P+ light doped polysilicon layer concentration is lower, can reduce the electric leakage, and the parallel resistance is higher, improves the fill factor, promotes open circuit voltage.

[0050] (2)The utility model discloses a P++ heavy doped polysilicon layer or N++ heavy doped polysilicon layer is set up, forms P++ / P+ or N++ / N+ high low knot, and contacts metal electrode, has reduced the contact resistance between back metal electrode and doped polysilicon, is favorable to the collection of carrier, further improves open pressure, promotes the conversion efficiency of TBC battery, and moreover helps to solve the burn -through damage problem of high temperature metal slurry to ultrathin passivation contact. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical scheme of the embodiments of the utility model, the following will be to the drawings needed in the embodiment used briefly introduces, should understand, the following drawings only shows some embodiments of the utility model, therefore should not be regarded as the limitation to the scope, for ordinary skilled person in the art comes, under the premise of not paying the creative labor, can also obtain other related drawings according to these drawings.

[0052] Figure 1 It is one of TBC battery structure schematic diagram in the utility model;

[0053] Figure 2 It is the second TBC battery structure schematic diagram in the utility model.

[0054] In the drawing, 1, crystalline silicon substrate;2, front passivation layer;3, front antireflection layer;4, dielectric layer;5, P+ doped polysilicon layer;6, back antireflection layer;7, first electrode;8, second electrode;9, N+ light doped polysilicon layer;10, N++ heavy doped polysilicon layer;11, back passivation layer;12, N+ doped polysilicon layer;13, P+ light doped polysilicon layer;14, P++ heavy doped polysilicon layer. DETAILED DESCRIPTION

[0055] In order to make the purposes, technical schemes and advantages of the embodiments of the present application clearer, the technical schemes of the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present application.

[0056] In order to improve the photoelectric conversion efficiency of the TBC cell, the present embodiment provides a TBC cell with local back surface doping. Based on the existing BC cell structure and equipment, a heavily doped region is formed, and other regions are lightly doped regions. While improving the efficiency, the process is relatively simple, the cost increase is less, the control difficulty is low, and the SE technology is effectively applied to the back surface of the BC cell to improve the cell efficiency. The specific implementation is as follows:

[0057] As shown in Figure 1 A TBC cell with local back surface doping, the TBC cell includes a crystalline silicon substrate 1, the front surface of the crystalline silicon substrate 1 includes a front surface passivation layer 2 and a front surface anti-reflection layer 3 from inside to outside; the back surface of the crystalline silicon substrate 1 is provided with alternately arranged P+ regions and N+ regions, and there is a spacing region between the P+ regions and the N+ regions, the P+ regions on the back surface of the crystalline silicon substrate 1 include a dielectric layer 4, a P+ doped polysilicon layer 5, a back surface anti-reflection layer 6 and a first electrode 7 from inside to outside, the N+ regions on the back surface of the crystalline silicon substrate 1 include a dielectric layer 4, an N+ region doped polysilicon layer, a back surface anti-reflection layer 6 and a second electrode 8 from inside to outside; the N+ region doped polysilicon layer includes an N+ lightly doped polysilicon layer 9 and an N++ heavily doped polysilicon layer 10, and the surface concentration of the N++ heavily doped polysilicon layer 10 is greater than that of the N+ lightly doped polysilicon layer 9; the first electrode 7 penetrates the back surface anti-reflection layer 6 and forms an ohmic contact with the P+ doped polysilicon layer 5, and the second electrode 8 penetrates the back surface anti-reflection layer 6 and forms an ohmic contact with the N++ heavily doped polysilicon layer 10.

[0058] As a preferred embodiment, the N++ heavily doped polysilicon layer 10 is inside the N+ lightly doped polysilicon layer 9, and the volume of the N++ heavily doped polysilicon layer 10 accounts for 2% to 70% of the N+ lightly doped polysilicon layer 9.

[0059] As a more preferred embodiment, the volume of the N++ heavily doped polysilicon layer 10 accounts for 2% to 55% of the N+ lightly doped polysilicon layer 9.

[0060] As a preferred embodiment, the N+ region has a junction depth of 0.05-0.5 μm; the N+ lightly-doped polysilicon layer 9 has an ECV surface concentration of 2E19-4E20 cm -3 and a sheet resistance of 30-400 Ω; the N++ heavily-doped polysilicon layer 10 has an ECV surface concentration of 2E20-1E21 cm -3 and a sheet resistance of 20-60 Ω.

[0061] As a preferred embodiment, the P+ region has a junction depth of 0.1-0.5 μm; the P+ doped polysilicon layer 5 has an ECV surface concentration of 2E19-5E20 cm -3 and a sheet resistance of 20-400 Ω.

[0062] As a preferred embodiment, the N+ region comprises, from inside to outside on the back surface of the crystalline silicon substrate 1, a dielectric layer 4, the N+ region doped polysilicon layer, a back passivation layer 11, a back anti-reflection layer 6 and a second electrode 8; the N+ region doped polysilicon layer comprises an N+ lightly-doped polysilicon layer 9 and an N++ heavily-doped polysilicon layer 10, and the surface concentration of the N++ heavily-doped polysilicon layer 10 is greater than that of the N+ lightly-doped polysilicon layer 9; the second electrode 8 penetrates the back anti-reflection layer 6 and the back passivation layer 11 to form an ohmic contact with the N++ heavily-doped polysilicon layer 10.

[0063] As a preferred embodiment, the front passivation layer 2 and the back passivation layer 11 have a thickness of 1-10 nm.

[0064] As a preferred embodiment, the front anti-reflection layer 3 and the back anti-reflection layer 6 have a thickness of 20-200 nm.

[0065] The utility model also provides a preparation method of the back local doping TBC battery, which comprises the following steps:

[0066] Step one, place the N / P type silicon wafer in a tank type alkali solution for polishing;

[0067] Step two, form the P+ region: first form a dielectric layer 4 on the back of the silicon wafer, then form an amorphous silicon layer or a polysilicon layer or a mixed layer of amorphous silicon and polysilicon on the dielectric layer 4, and then perform boron doping to obtain the P+ doped polysilicon layer 5;

[0068] Step three, locally remove the P+ region;

[0069] Step four, the N+ region is formed: first, a dielectric layer 4 is formed on the back of the silicon wafer, then a layer of amorphous silicon or polycrystalline silicon or a mixed layer of amorphous silicon and polycrystalline silicon is formed on the dielectric layer 4, and then phosphorus doping is performed to obtain an N+ lightly doped polycrystalline silicon layer 9; and then the PSG on the surface of the N+ lightly doped polycrystalline silicon layer 9 is used as a doping source, a phosphorus source is secondly pushed, and under local heat treatment, an N++ heavily doped polycrystalline silicon layer 10 is formed in the N+ lightly doped polycrystalline silicon layer 9;

[0070] Step five, the N+ region above the P+ region and the adjacent part of the N+ region above the P+ region are partially removed;

[0071] Step six, the front surface of the silicon wafer is etched to form a pyramid structure;

[0072] Step seven, a front passivation layer 2 is deposited on the front surface of the silicon wafer or a front passivation layer 2 and a back passivation layer 11 are respectively deposited on the front and back surfaces of the silicon wafer;

[0073] Step eight, a front anti-reflection layer 3 and a back anti-reflection layer 6 are respectively deposited on the front and back surfaces of the silicon wafer;

[0074] Step nine, a first electrode 7 and a second electrode 8 are respectively prepared on the P+ region and the N+ region.

[0075] As a preferred embodiment, the local heat treatment in step four includes two ways, the first way is to use a laser to locally heat the PSG on the surface of the N+ lightly doped polycrystalline silicon layer 9, and then perform heat treatment pushing, the temperature is 850-960℃, the time is 10-60min, and the N++ heavily doped polycrystalline silicon layer 10 is formed in the N+ lightly doped polycrystalline silicon layer 9; the second way is to locally clean to remove part of the PSG on the surface of the N+ lightly doped polycrystalline silicon layer 9, and then use the remaining PSG as a doping source to perform heat treatment, the temperature is 850-960℃, the time is 10-60min, and the N++ heavily doped polycrystalline silicon layer 10 is formed in the N+ lightly doped polycrystalline silicon layer 9.

[0076] As a preferred embodiment, the power of the laser in the laser doping technology in step four is 1-70W, the wavelength is 300-700nm, the scanning speed is 5000-60000mm / s, and the frequency is 200-2000kHz.

[0077] The utility model discloses still provide a kind of TBC battery of back partial doping, including crystalline silicon substrate 1, the front surface of crystalline silicon substrate 1 from inside to outside includes front passivation layer 2 and front antireflection layer 3 in proper order;The back surface of crystalline silicon substrate 1 is provided with the P+ area and N+ area of alternate arrangement and there is interval area between the P+ area and the N+ area, the N+ area on the back surface of crystalline silicon substrate 1 from inside to outside includes dielectric layer 4, N+ doped polysilicon layer 12, back antireflection layer 6 and first electrode 7 in proper order, the P+ area on the back surface of crystalline silicon substrate 1 from inside to outside includes dielectric layer 4, P+ area doped polysilicon layer, back antireflection layer 6 and second electrode 8 in proper order;The P+ area doped polysilicon layer includes P+ lightly doped polysilicon layer 13 and P++ heavily doped polysilicon layer 14, the surface concentration of P++ heavily doped polysilicon layer 14 is greater than the surface concentration of P+ lightly doped polysilicon layer 13;First electrode 7 penetrates back antireflection layer 6 and N+ doped polysilicon layer 12 and forms ohmic contact, and second electrode 8 penetrates back antireflection layer 6 and P++ heavily doped polysilicon layer 14 and forms ohmic contact.

[0078] As a preferred embodiment, P++ heavily doped polysilicon layer 14 is inside P+ lightly doped polysilicon layer 13, and the volume of P++ heavily doped polysilicon layer 14 accounts for 2% to 70% of P+ lightly doped polysilicon layer 13.

[0079] As a more preferred embodiment, the volume of P++ heavily doped polysilicon layer 14 accounts for 2% to 55% of P+ lightly doped polysilicon layer 13.

[0080] As a preferred embodiment, the junction depth of the P+ area is 0.05 to 0.5 μm; the ECV surface concentration of P+ lightly doped polysilicon layer 13 is 2E19 to 5E20 cm -3 , and the square resistance is 20 to 400 Ω; the ECV surface concentration of P++ heavily doped polysilicon layer 14 is 2E20 to 8E20 cm -3 , and the square resistance is 20 to 80 Ω.

[0081] As a preferred embodiment, the junction depth of the N+ area is 0.1 to 0.5 μm; the ECV surface concentration of N+ doped polysilicon layer 12 is 2E19 to 4E20 cm -3 , and the square resistance is 30 to 400 Ω.

[0082] As a preferred embodiment, the P+ region is sequentially provided with a dielectric layer 4, the P+ region doped polysilicon layer, a back passivation layer 11, a back anti-reflection layer 6 and a second electrode 8 from inside to outside on the back surface of the crystalline silicon substrate 1; the P+ region doped polysilicon layer comprises a P+ lightly doped polysilicon layer 13 and a P++ heavily doped polysilicon layer 14, and the surface concentration of the P++ heavily doped polysilicon layer 14 is greater than that of the P+ lightly doped polysilicon layer 13; the second electrode 8 penetrates the back anti-reflection layer 6 and the back passivation layer 11 to form an ohmic contact with the P++ heavily doped polysilicon layer 14.

[0083] As a preferred embodiment, the thickness of the front passivation layer 2 and the back passivation layer 11 is 1-10 nm.

[0084] As a preferred embodiment, the thickness of the front anti-reflection layer 3 and the back anti-reflection layer 6 is 20-200 nm.

[0085] The utility model also provides a kind of preparation method of the above-mentioned back local doping TBC battery, comprising the following steps:

[0086] Step one, N / P type silicon wafer is put into tank type alkali solution to polish;

[0087] Step two, the N+ region is formed: first form dielectric layer 4 on the back of silicon wafer, then form a layer of amorphous silicon layer or polysilicon layer or amorphous silicon and polysilicon mixed layer on dielectric layer 4, then phosphorus doping is carried out, to obtain N+ doped polysilicon layer 12;

[0088] Step three, the N+ region is partially removed;

[0089] Step four, the P+ region is formed: first form dielectric layer 4 on the back of silicon wafer, form a layer of amorphous silicon layer or polysilicon layer or amorphous silicon and polysilicon mixed layer on dielectric layer 4, then boron doping is carried out, to obtain P+ lightly doped polysilicon layer 13;Then take BSG on the surface of P+ lightly doped polysilicon layer 13 as doping source, secondly promote boron source, form P++ heavily doped polysilicon layer 14 in the interior of P+ lightly doped polysilicon layer 13 under local heat treatment;

[0090] Step five, the P+ region above N+ region and the adjacent part of P+ region above N+ region are partially removed;

[0091] Step six, the front of silicon wafer is textured to form pyramid structure;

[0092] Step seven, front passivation layer 2 is deposited on the front of silicon wafer or front passivation layer 2 and back passivation layer 11 are deposited on the front and back of silicon wafer respectively;

[0093] Step eight, front anti-reflection layer 3 and back anti-reflection layer 6 are deposited on the front and back of silicon wafer respectively.

[0094] Step nine, respectively, on the P+ region and the N+ region on the first electrode 7 and the second electrode 8 are prepared.

[0095] As a preferred embodiment, the step four local heat treatment includes two ways, the first laser BSG on the surface of P+ lightly doped polysilicon layer 13 is locally heated by laser, and then heat treatment is promoted, the temperature is 850~960℃, the time is 10~60min, P++ heavily doped polysilicon layer 14 is formed in the inside of P+ lightly doped polysilicon layer 13;The second kind of local cleaning removes part of the BSG on the surface of P+ lightly doped polysilicon layer 13, and the heat treatment is carried out with the BSG as the doping source, the temperature is 850~960℃, the time is 10~60min, P++ heavily doped polysilicon layer 14 is formed in the inside of P+ lightly doped polysilicon layer 13.

[0096] Preferably, the power of the laser in the laser doping technology in the step four is 1~70W, the wavelength is 300~700nm, the scanning speed is 5000~60000mm / s, and the frequency is 200~2000kHz.

[0097] The beneficial effects of the back surface local doping TBC battery and the preparation method thereof in the utility model are further commented through several groups of examples.

[0098] Example 1:

[0099] A back surface local doping TBC battery is provided in this embodiment 1, which comprises a crystalline silicon substrate, the crystalline silicon substrate is an N-type silicon wafer, the front surface of the crystalline silicon substrate comprises a front passivation layer and a front antireflection layer from inside to outside;The back surface of the crystalline silicon substrate is provided with alternately arranged P+ region and N+ region, and there is a spacing region between the P+ region and the N+ region, the N+ region comprises a dielectric layer, an N+ doped polysilicon layer, a back antireflection layer and a first electrode from inside to outside on the back surface of the crystalline silicon substrate, the P+ region is provided with the dielectric layer, the P+ region doped polysilicon layer, the back antireflection layer and the second electrode from inside to outside on the back surface of the crystalline silicon substrate;The P+ region doped polysilicon layer comprises the P+ lightly doped polysilicon layer and the P++ heavily doped polysilicon layer, the surface concentration of the P++ heavily doped polysilicon layer is greater than that of the P+ lightly doped polysilicon layer;The first electrode penetrates the back antireflection layer and forms ohmic contact with the N+ doped polysilicon layer, and the second electrode penetrates the back antireflection layer and forms ohmic contact with the P++ heavily doped polysilicon layer.

[0100] The ECV surface concentration of the N+ doped polysilicon layer is 2E19cm-3 , the sheet resistance of the P+ region is 400Ω, and the junction depth of the P+ region is 0.1 μm; the ECV surface concentration of the P+ lightly-doped polysilicon layer is 2E19 cm -3 , the sheet resistance of the P+ region is 400Ω, and the junction depth of the P+ region is 0.1 μm; the ECV surface concentration of the P+ lightly-doped polysilicon layer is 2E19 cm -3 , the sheet resistance of the P+ region is 80Ω, the junction depth of the P+ region is 0.05 μm, and the volume of the P++ heavily-doped polysilicon layer accounts for 2% of the P+ lightly-doped polysilicon layer; the thickness of the front passivation layer is 1 nm; the thickness of the front anti-reflection layer and the back anti-reflection layer is 20 nm.

[0101] The preparation method of the back surface locally-doped TBC cell in Embodiment 1 comprises the following steps:

[0102] Step one, polish the N-type silicon wafer in a tank-type alkali solution;

[0103] Step two, form the N+ region: first form the dielectric layer on the back surface of the silicon wafer, then form an amorphous silicon layer on the dielectric layer, and then perform boron doping to obtain the N+ doped polysilicon layer;

[0104] Step three, after laser patterning on the back surface of the silicon wafer, perform alkali etching to locally remove the N+ region;

[0105] Step four, form the P+ region: first form the dielectric layer on the back surface of the silicon wafer, then form an amorphous silicon layer on the dielectric layer, and then perform boron doping to obtain the P+ lightly-doped polysilicon layer; then use the BSG on the surface of the P+ lightly-doped polysilicon layer as a doping source, and form the P++ heavily-doped polysilicon layer inside the P+ lightly-doped polysilicon layer by laser doping technology, in which the power of the laser is 35 W, the wavelength is 500 nm, the scanning speed is 32500 mm / s, the frequency is 1100 kHz, the phosphorus source is pushed twice, and then heat treatment is performed for pushing, at a temperature of 850°C for 10 min;

[0106] Step five, locally remove the P+ region above the N+ region and the adjacent part of the P+ region above the N+ region;

[0107] Step six, perform texturing on the front surface of the silicon wafer to form a pyramid structure;

[0108] Step seven, deposit the front passivation layer on the front surface of the silicon wafer;

[0109] Step eight, deposit the front anti-reflection layer and the back anti-reflection layer on the front and back surfaces of the silicon wafer, respectively;

[0110] Step nine, fabricating the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0111] Comparative Example 1:

[0112] A backside locally doped TBC cell is provided in Comparative Example 1, which comprises a crystalline silicon substrate, the crystalline silicon substrate is an N-type silicon wafer, the front surface of the crystalline silicon substrate comprises a front passivation layer and a front anti-reflective layer from inside to outside in sequence; the back surface of the crystalline silicon substrate is provided with P+ regions and N+ regions arranged alternately and there is a spacing region between the P+ regions and the N+ regions, the N+ region comprises a dielectric layer, an N+ doped polysilicon layer, a back anti-reflective layer and a first electrode from inside to outside on the back surface of the crystalline silicon substrate in sequence, the P+ region is provided with the dielectric layer, the P+ doped polysilicon layer, the back anti-reflective layer and the second electrode from inside to outside on the back surface of the crystalline silicon substrate in sequence; the first electrode forms an ohmic contact with the N+ doped polysilicon layer through the back anti-reflective layer, and the second electrode forms an ohmic contact with the P+ doped polysilicon layer through the back anti-reflective layer.

[0113] The ECV surface concentration of the N+ doped polysilicon layer is 2E19 cm-3, the sheet resistance is 400 Ω, the junction depth of the N+ region is 0.1 μm; the ECV surface concentration of the P+ doped polysilicon layer is 2E19 cm-3, the sheet resistance is 400 Ω, and the junction depth of the P+ region is 0.05 μm; the thickness of the front passivation layer is 1 nm; the thickness of the front anti-reflective layer and the back anti-reflective layer is 20 nm. -3 -3

[0114] The preparation method thereof is different from that of Example 1 only in that step four is to form the dielectric layer on the back surface of the silicon wafer first, then form an amorphous silicon layer on the dielectric layer, and then perform boron doping to obtain the P+ doped polysilicon layer. Other steps are the same as those of Example 1.

[0115] Example 2:

[0116] ​​A back surface locally doped TBC cell is provided in this embodiment 2, comprising a crystalline silicon substrate which is an N-type silicon wafer, the front surface of the crystalline silicon substrate comprises a front surface passivation layer and a front surface anti-reflection layer from inside to outside in sequence; the back surface of the crystalline silicon substrate is provided with P+ regions and N+ regions arranged alternately and there is a spacing region between the P+ regions and the N+ regions, the P+ regions comprise a dielectric layer, a P+ doped polysilicon layer, a back surface anti-reflection layer and a first electrode from inside to outside on the back surface of the crystalline silicon substrate in sequence, the N+ regions comprise the dielectric layer, an N+ doped polysilicon layer, a back surface passivation layer, the back surface anti-reflection layer and the second electrode from inside to outside on the back surface of the crystalline silicon substrate in sequence; the N+ doped polysilicon layer comprises the N+ lightly doped polysilicon layer and the N++ heavily doped polysilicon layer, and the surface concentration of the N++ heavily doped polysilicon layer is greater than that of the N+ lightly doped polysilicon layer; the first electrode forms an ohmic contact with the P+ doped polysilicon layer through the back surface anti-reflection layer, and the second electrode forms an ohmic contact with the N++ heavily doped polysilicon layer through the back surface anti-reflection layer and the back surface passivation layer.

[0117] wherein the ECV surface concentration of the P+ doped polysilicon layer is 2E19 cm -3 , the sheet resistance is 400 Ω, the junction depth of the P+ region is 0.1 μm; the ECV surface concentration of the N+ lightly doped polysilicon layer is 2E19 cm -3 , the sheet resistance is 400 Ω, the ECV surface concentration of the N++ heavily doped polysilicon layer is 2E20 cm -3 , the sheet resistance is 60 Ω, the junction depth of the N+ region is 0.05 μm, and the volume of the N++ heavily doped polysilicon layer accounts for 55% of the N+ lightly doped polysilicon layer; the thickness of the front surface passivation layer and the back surface passivation layer is 1 nm; the thickness of the front surface anti-reflection layer and the back surface anti-reflection layer is 20 nm.

[0118] A preparation method of a back surface locally doped TBC cell is provided in this embodiment 2, comprising the following steps:

[0119] Step one, placing the N-type silicon wafer into a tank type alkali solution for polishing;

[0120] Step two, forming the P+ regions: first forming the dielectric layer on the back surface of the silicon wafer, then forming a polysilicon layer on the dielectric layer, and then performing boron doping to obtain the P+ doped polysilicon layer;

[0121] Step three, after laser patterning on the back surface of the silicon wafer, performing alkali etching to locally remove the P+ regions;

[0122] Step four, the N+ region is formed: first, a dielectric layer is formed on the back surface of the silicon wafer, then a polysilicon layer is formed on the dielectric layer, and boron doping is performed to obtain the N+ lightly doped polysilicon layer; then, the BSG on the surface of the N+ lightly doped polysilicon layer is used as a doping source, and a laser doping technology is used, the power of the laser is 35 W, the wavelength is 500 nm, the scanning speed is 32500 mm / s, the frequency is 1100 kHz, the phosphorus source is pushed twice, and then heat treatment is performed to promote the pushing, the temperature is 960℃, and the time is 60 min, so that the N++ heavily doped polysilicon layer is formed in the N+ lightly doped polysilicon layer;

[0123] Step five, the N+ region above the P+ region and the adjacent part of the N+ region above the P+ region are partially removed;

[0124] Step six, the front surface of the silicon wafer is textured to form a pyramid structure;

[0125] Step seven, the front passivation layer and the back passivation layer are deposited on the front and back surfaces of the silicon wafer, respectively;

[0126] Step eight, the front anti-reflection layer and the back anti-reflection layer are deposited on the front and back surfaces of the silicon wafer, respectively;

[0127] Step nine, the first electrode and the second electrode are prepared on the P+ region and the N+ region, respectively.

[0128] Comparative Example 2:

[0129] A back surface locally doped TBC cell is provided in the present comparative example 2, which comprises a crystalline silicon substrate, the crystalline silicon substrate is an N-type silicon wafer, the front surface of the crystalline silicon substrate comprises a front passivation layer and a front anti-reflection layer from inside to outside; the back surface of the crystalline silicon substrate is provided with alternately arranged P+ regions and N+ regions and there is an interval region between the P+ regions and the N+ regions, the P+ region comprises a dielectric layer, a P+ doped polysilicon layer, a back anti-reflection layer and a first electrode from inside to outside on the back surface of the crystalline silicon substrate, the N+ region comprises the dielectric layer, the N+ doped polysilicon layer, the back passivation layer, the back anti-reflection layer and the second electrode from inside to outside on the back surface of the crystalline silicon substrate; the first electrode penetrates the back anti-reflection layer and the P+ doped polysilicon layer to form an ohmic contact, and the second electrode penetrates the back anti-reflection layer and the back passivation layer and the N+ doped polysilicon layer to form an ohmic contact.

[0130] The ECV surface concentration of the P+ doped polysilicon layer is 2E19 cm -3 , the square resistance is 400Ω, and the junction depth of the P+ region is 0.1μm; the ECV surface concentration of the N+ doped polysilicon layer is 2E19 cm-3 , the square resistance is 400Ω, the junction depth of the N+ region is 0.05μm; the thickness of the front passivation layer and the back passivation layer are both 1nm; the thickness of the front anti-reflection layer and the back anti-reflection layer are both 20nm.

[0131] The preparation method is the same as in Example 2 except that step 4 only involves first forming the dielectric layer on the back of the silicon wafer, then forming a polysilicon layer on the dielectric layer, and then performing phosphorus doping to obtain the N+ doped polysilicon layer.

[0132] Example 3:

[0133] In this embodiment 3, a TBC cell with local back doping is provided, comprising a crystalline silicon substrate, wherein the crystalline silicon substrate is a P-type silicon wafer, and the front surface of the crystalline silicon substrate includes a front passivation layer and a front anti-reflection layer in sequence from the inside to the outside; the back surface of the crystalline silicon substrate is provided with a P+ region and an N+ region arranged alternately, and there is a spacing region between the P+ region and the N+ region, and the N+ region includes a dielectric layer, an N+ doped polysilicon layer, a back anti-reflection layer and a first electrode in sequence from the inside to the outside of the back surface of the crystalline silicon substrate, and the P+ region is arranged on the back surface of the crystalline silicon substrate from the inside to the outside. The dielectric layer, the P+ region doped polysilicon layer, the back passivation layer, the back anti-reflection layer and the second electrode are arranged in sequence; the P+ region doped polysilicon layer includes the P+ lightly doped polysilicon layer and the P++ heavily doped polysilicon layer, and the surface concentration of the P++ heavily doped polysilicon layer is greater than the surface concentration of the P+ lightly doped polysilicon layer; the first electrode penetrates the back anti-reflection layer to form an ohmic contact with the N+ doped polysilicon layer, and the second electrode penetrates the back anti-reflection layer and the back passivation layer to form an ohmic contact with the P++ heavily doped polysilicon layer.

[0134] The ECV surface concentration of the N+ doped polysilicon layer is 4E20 cm -3 , the square resistance is 30Ω, the junction depth of the N+ region is 0.5μm; the ECV surface concentration of the P+ lightly doped polysilicon layer is 5E20cm -3 , the square resistance is 40Ω, and the ECV surface concentration of the P++ heavily doped polysilicon layer is 8E20cm -3 , square resistance 20Ω, the P+ region junction depth is 0.5μm, and the volume of the P++ heavily doped polysilicon layer accounts for 55% of the P+ lightly doped polysilicon layer; the thickness of the front passivation layer and the back passivation layer is 10nm; the thickness of the front anti-reflection layer and the back anti-reflection layer are both 200nm.

[0135] The method for preparing a TBC battery with local back-side doping in Example 3 includes the following steps:

[0136] Step one, put P-type silicon wafer into tank type alkali solution for polishing;

[0137] Step two, the N+ region is formed as follows: first form the dielectric layer on the back of the silicon wafer, then form a layer of amorphous silicon and polycrystalline silicon mixed layer on the dielectric layer, and then perform boron doping to obtain the N+ doped polycrystalline silicon layer;

[0138] Step three, after laser patterning on the back of the silicon wafer, perform alkali etching to locally remove the N+ region;

[0139] Step four, the P+ region is formed as follows: first form the dielectric layer on the back of the silicon wafer, then form a layer of amorphous silicon and polycrystalline silicon mixed layer on the dielectric layer, and then perform boron doping to obtain the P+ lightly doped polycrystalline silicon layer; then use the BSG on the surface of the P+ lightly doped polycrystalline silicon layer as a doping source, and perform laser doping technology, with the power of the laser being 35 W, the wavelength being 500 nm, the scanning speed being 32500 mm / s, the frequency being 1100 kHz, the phosphorus source being pushed twice, and then performing heat treatment to promote, with the temperature being 900℃ and the time being 35 min, to form the P++ heavily doped polycrystalline silicon layer inside the P+ lightly doped polycrystalline silicon layer;

[0140] Step five, locally remove the P+ region above the N+ region and the adjacent part of the P+ region above the N+ region;

[0141] Step six, perform texturing on the front of the silicon wafer to form a pyramid structure;

[0142] Step seven, deposit the front passivation layer and the back passivation layer on the front and back of the silicon wafer respectively;

[0143] Step eight, deposit the front anti-reflection layer and the back anti-reflection layer on the front and back of the silicon wafer respectively;

[0144] Step nine, prepare the first electrode and the second electrode on the P+ region and the N+ region respectively.

[0145] Comparative Example 3:

[0146] A back surface locally doped TBC cell is provided in Comparative Example 3, comprising a crystalline silicon substrate which is a P-type silicon wafer, the front surface of the crystalline silicon substrate comprises a front passivation layer and a front anti-reflective layer from inside to outside in sequence; the back surface of the crystalline silicon substrate is provided with P+ regions and N+ regions arranged alternately and there is a spacing region between the P+ regions and the N+ regions, the N+ regions comprise a dielectric layer, an N+ doped polysilicon layer, a back anti-reflective layer and a first electrode from inside to outside on the back surface of the crystalline silicon substrate in sequence, the P+ regions are provided with the dielectric layer, the P+ doped polysilicon layer, the back passivation layer, the back anti-reflective layer and the second electrode from inside to outside on the back surface of the crystalline silicon substrate in sequence; the first electrode forms an ohmic contact with the N+ doped polysilicon layer through the back anti-reflective layer, and the second electrode forms an ohmic contact with the P+ doped polysilicon layer through the back anti-reflective layer and the back passivation layer.

[0147] wherein the ECV surface concentration of the N+ doped polysilicon layer is 4E20 cm-3, the sheet resistance is 30 Ω, and the junction depth of the N+ region is 0.5 μm; the ECV surface concentration of the P+ doped polysilicon layer is 5E20 cm-3, the sheet resistance is 40 Ω, and the junction depth of the P+ region is 0.5 μm; the thickness of the front passivation layer and the back passivation layer is 10 nm; and the thickness of the front anti-reflective layer and the back anti-reflective layer is 200 nm. -3 -3

[0148] The preparation method thereof is different from that of Example 3 only in that step four is to form the dielectric layer on the back surface of the silicon wafer first, then form a mixed layer of amorphous silicon and polysilicon on the dielectric layer, and then perform boron doping to obtain the P+ doped polysilicon layer.

[0149] Example 4:

[0150] ​​A back surface locally doped TBC cell is provided in this embodiment 4, comprising a crystalline silicon substrate which is a P-type silicon wafer, the front surface of the crystalline silicon substrate comprises a front passivation layer and a front anti-reflection layer from inside to outside in sequence; the back surface of the crystalline silicon substrate is provided with P+ regions and N+ regions arranged alternately and there is a spacing region between the P+ regions and the N+ regions, the P+ regions comprise a dielectric layer, a P+ doped polysilicon layer, a back anti-reflection layer and a first electrode from inside to outside on the back surface of the crystalline silicon substrate in sequence, the N+ regions comprise the dielectric layer, an N+ doped polysilicon layer, the back passivation layer, the back anti-reflection layer and the second electrode from inside to outside on the back surface of the crystalline silicon substrate in sequence; the N+ doped polysilicon layer comprises the N+ lightly doped polysilicon layer and the N++ heavily doped polysilicon layer, and the surface concentration of the N++ heavily doped polysilicon layer is greater than that of the N+ lightly doped polysilicon layer; the first electrode forms an ohmic contact with the P+ doped polysilicon layer through the back anti-reflection layer, and the second electrode forms an ohmic contact with the N++ heavily doped polysilicon layer through the back anti-reflection layer and the back passivation layer.

[0151] wherein the ECV surface concentration of the P+ doped polysilicon layer is 5E20 cm -3 , the sheet resistance is 40Ω, the junction depth of the P+ region is 0.5μm; the ECV surface concentration of the N+ lightly doped polysilicon layer is 4E20 cm -3 , the sheet resistance is 30Ω, the ECV surface concentration of the N++ heavily doped polysilicon layer is 1E21 cm -3 , the sheet resistance is 20Ω, the junction depth of the N+ region is 0.5μm, and the volume of the N++ heavily doped polysilicon layer accounts for 70% of the N+ lightly doped polysilicon layer; the thickness of the front passivation layer and the back passivation layer is 5nm; the thickness of the front anti-reflection layer and the back anti-reflection layer is 100nm.

[0152] A preparation method of a back surface locally doped TBC cell is provided in this embodiment 4, comprising the following steps:

[0153] Step one, put the P-type silicon wafer into a tank type alkali solution for polishing;

[0154] Step two, the P+ region is formed: first form the dielectric layer on the back surface of the silicon wafer, then form a polysilicon layer on the dielectric layer, and then perform boron doping to obtain the P+ doped polysilicon layer;

[0155] Step three, after laser patterning on the back surface of the silicon wafer, perform alkali etching to locally remove the P+ region;

[0156] Step four, the N+ region is formed: first, a dielectric layer is formed on the back surface of the silicon wafer, then a polysilicon layer is formed on the dielectric layer, and boron doping is performed to obtain the N+ lightly doped polysilicon layer; then, the BSG on the surface of the N+ lightly doped polysilicon layer is used as a doping source, and a laser doping technology is used, the power of the laser is 35 W, the wavelength is 500 nm, the scanning speed is 32500 mm / s, the frequency is 1100 kHz, the phosphorus source is pushed twice, and then heat treatment is performed to promote the pushing, the temperature is 930°C, and the time is 50 min, so that the N++ heavily doped polysilicon layer is formed in the N+ lightly doped polysilicon layer;

[0157] Step five, the N+ region above the P+ region and the adjacent part of the N+ region above the P+ region are partially removed;

[0158] Step six, the front surface of the silicon wafer is textured to form a pyramid structure;

[0159] Step seven, the front passivation layer and the back passivation layer are deposited on the front surface and the back surface of the silicon wafer, respectively;

[0160] Step eight, the front anti-reflection layer and the back anti-reflection layer are deposited on the front surface and the back surface of the silicon wafer, respectively;

[0161] Step nine, the first electrode and the second electrode are prepared on the P+ region and the N+ region, respectively.

[0162] Comparative Example 4:

[0163] In this comparative example 4, a back surface locally doped TBC cell is provided, which comprises a crystalline silicon substrate, the crystalline silicon substrate is a P-type silicon wafer, the front surface of the crystalline silicon substrate comprises a front passivation layer and a front anti-reflection layer from inside to outside; the back surface of the crystalline silicon substrate is provided with alternately arranged P+ regions and N+ regions, and there is a spacing region between the P+ regions and the N+ regions, the P+ region comprises a dielectric layer, a P+ doped polysilicon layer, a back anti-reflection layer and a first electrode from inside to outside on the back surface of the crystalline silicon substrate, the N+ region comprises the dielectric layer, the N+ doped polysilicon layer, the back passivation layer, the back anti-reflection layer and the second electrode from inside to outside on the back surface of the crystalline silicon substrate; the first electrode penetrates the back anti-reflection layer and the P+ doped polysilicon layer to form an ohmic contact, and the second electrode penetrates the back anti-reflection layer and the back passivation layer and the N+ doped polysilicon layer to form an ohmic contact.

[0164] The ECV surface concentration of the P+ doped polysilicon layer is 5E20 cm -3 , the square resistance is 40Ω, the junction depth of the P+ region is 0.5μm, the ECV surface concentration of the N+ doped polysilicon layer is 4E20 cm-3 The N+ area has a junction depth of 0.5 μm; the front passivation layer and the back passivation layer each have a thickness of 5 nm; and the front anti-reflection layer and the back anti-reflection layer each have a thickness of 100 nm.

[0165] The preparation method is different from the embodiment 4 in that only step four is to form a dielectric layer on the back surface of the silicon wafer, then form an amorphous silicon layer or a polycrystalline silicon layer or a mixed layer of amorphous silicon and polycrystalline silicon on the dielectric layer, and then perform phosphorus doping to obtain the N+ doped polycrystalline silicon layer. The other steps are the same as those of the embodiment 4.

[0166] The TBC batteries obtained in the above four groups of examples and comparative examples are subjected to performance tests, and the results are as follows:

[0167] Table 1: Performance test results of the TBC batteries of examples 1-4 and comparative examples 1-4

[0168]

[0169]

[0170] As shown in Table 1, the TBC batteries prepared in the examples 1-4 of the present application have higher conversion efficiency, larger open circuit voltage, short circuit current and fill factor by forming a P++ heavily doped polycrystalline silicon layer on the surface of a P+ lightly doped polycrystalline silicon layer or forming an N++ heavily doped polycrystalline silicon layer on the surface of an N+ lightly doped polycrystalline silicon layer, compared with the comparative examples 1-4. In addition, when the volume of the heavily doped layer accounts for 2-55% of the volume of the lightly doped layer in the TBC batteries prepared in the examples 1-4, the TBC batteries have higher conversion efficiency.

[0171] The preferred embodiments of the present application are described above, but the present application is not limited to the above. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A TBC battery with local back doping, characterized in that: The invention comprises a crystalline silicon substrate, wherein the front surface of the crystalline silicon substrate comprises, from the inside to the outside, a front passivation layer and a front anti-reflection layer in sequence; the back surface of the crystalline silicon substrate is provided with a P+ region and an N+ region arranged alternately, with a spacing region between the P+ region and the N+ region; the P+ region comprises, from the inside to the outside, a dielectric layer, a P+ doped polysilicon layer, a back anti-reflection layer, and a first electrode in sequence on the back surface of the crystalline silicon substrate; and the N+ region comprises, from the inside to the outside, a dielectric layer, an N+ region doped polysilicon layer, a back anti-reflection layer, and a second electrode in sequence on the back surface of the crystalline silicon substrate; The N+ region doped polysilicon layer includes an N+ lightly doped polysilicon layer and an N++ heavily doped polysilicon layer, and the surface concentration of the N++ heavily doped polysilicon layer is greater than the surface concentration of the N+ lightly doped polysilicon layer; the first electrode penetrates the back anti-reflection layer to form an ohmic contact with the P+ doped polysilicon layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the N++ heavily doped polysilicon layer.

2. The TBC cell with local backside doping according to claim 1, characterized in that: The N++ heavily doped polysilicon layer is inside the N+ lightly doped polysilicon layer, and the volume of the N++ heavily doped polysilicon layer accounts for 2% to 70% of the volume of the N+ lightly doped polysilicon layer.

3. The TBC cell with local backside doping according to claim 1, characterized in that: The junction depth of the N+ region is 0.05-0.5 μm.

4. The TBC cell with local backside doping according to claim 1, characterized in that: The junction depth of the P+ region is 0.1-0.5 μm.

5. A TBC battery with local back doping, characterized in that: The invention comprises a crystalline silicon substrate, wherein the front surface of the crystalline silicon substrate comprises, from the inside to the outside, a front passivation layer and a front anti-reflection layer in sequence; the back surface of the crystalline silicon substrate is provided with a P+ region and an N+ region arranged alternately, with a spacing region between the P+ region and the N+ region; the N+ region comprises, from the inside to the outside, a dielectric layer, an N+ doped polysilicon layer, a back anti-reflection layer, and a first electrode in sequence on the back surface of the crystalline silicon substrate; and the P+ region comprises, from the inside to the outside, a dielectric layer, a P+ region doped polysilicon layer, a back anti-reflection layer, and a second electrode in sequence on the back surface of the crystalline silicon substrate; The P+ region doped polysilicon layer includes a P+ lightly doped polysilicon layer and a P++ heavily doped polysilicon layer, and the surface concentration of the P++ heavily doped polysilicon layer is greater than the surface concentration of the P+ lightly doped polysilicon layer; the first electrode penetrates the back anti-reflection layer to form an ohmic contact with the N+ doped polysilicon layer, and the second electrode penetrates the back anti-reflection layer to form an ohmic contact with the P++ heavily doped polysilicon layer.

6. The TBC cell with local backside doping according to claim 5, characterized in that: The P++ heavily doped polysilicon layer is inside the P+ lightly doped polysilicon layer, and the volume of the P++ heavily doped polysilicon layer accounts for 2% to 70% of the volume of the P+ lightly doped polysilicon layer.

7. The TBC cell with local backside doping according to claim 5, characterized in that: The junction depth of the P+ region is 0.05-0.5 μm.

8. The back-locally doped TBC cell according to claim 5, characterized in that: The junction depth of the P+ region is 0.1-0.5 μm.

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