Array substrate and display device

Abstract

The utility model discloses an array substrate and a display device. The array substrate comprises a substrate body and at least one test unit. The substrate is provided with a display area and a non-display area located on one side of the display area. The test unit is located in the non-display area; the test unit comprises a test element, a test bonding pad and a wire; each port of the test element corresponds to the test bonding pad and the wire, and is connected with the corresponding test bonding pad through the corresponding wire; and the orthographic projection of the test bonding pad on the substrate is circular.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display, and particularly relates to an array substrate and a display device. BACKGROUND

[0002] The array substrate is the main structure of a display, and relevant tests need to be performed on the array substrate to ensure the product yield of the display. Currently, the tests on the array substrate include electronic performance measurement (EPM) of thin film transistors (TFT). The EPM sets TFT test element groups (TEGs) on the array substrate, and a customized prober of an EPM device is inserted into square pads of the TEGs for testing. If one probe deviates from the square pad, the risk of direct scrapping will be faced. UTILITY MODEL CONTENT

[0003] The present application provides an array substrate and a display device, and aims to at least partly solve the problem that the probe is easy to deviate from the pad.

[0004] In a first aspect of the present application, an array substrate is provided, and the array substrate comprises:

[0005] A substrate substrate has a display area and a non-display area located on one side of the display area;

[0006] At least one test unit is located in the non-display area; the test unit comprises a test element, a test pad and a trace; each port of the test element corresponds to the test pad and the trace, and is connected to the corresponding test pad through the corresponding trace; the orthogonal projection of the test pad on the substrate substrate is circular.

[0007] In some embodiments, the test element is a transistor with three ports, the test unit comprises three test pads and three traces, and the three test pads and the three traces correspond to the three ports of the test element one by one.

[0008] In some embodiments, the centers of the orthogonal projections of the three test pads on the substrate substrate are not collinear.

[0009] In some embodiments, the projection of the two test pads on the substrate is located on a first side of the projection of the test element on the substrate; the projection of the other test pad on the substrate is located on a second side of the projection of the test element on the substrate, the second side is opposite to the first side.

[0010] In some embodiments, the non-display region comprises a test region corresponding to the test unit, the test unit is located in the corresponding test region; the projection of the test region on the substrate is a triangle.

[0011] In some embodiments, the line connecting the centers of the two test pads on the same side of the test element is parallel to one side of the triangle.

[0012] In some embodiments, the array substrate comprises a plurality of test units, a plurality of test regions are arranged in at least one row and a plurality of columns; the projections of two adjacent test regions in the same row on the substrate are point-symmetrical patterns.

[0013] In some embodiments, a plurality of test regions are arranged in at least two rows; the projections of two adjacent test regions in the same column on the substrate are axis-symmetrical patterns, and the axis of symmetry is parallel to the row direction.

[0014] In some embodiments, the projections of the three test pads on the substrate are equal-sized circles, and the distances between the centers of the projections of the three test pads on the substrate are equal.

[0015] In some embodiments, the projections of the three test pads on the substrate are arranged in a first direction.

[0016] In some embodiments, the projections of the three test pads on the substrate are located on the same side of the projection of the test element on the substrate; the projections of the test pads and the test element on the substrate are arranged in a second direction, and the second direction intersects the first direction.

[0017] In some embodiments, the non-display region comprises a test region corresponding to the test unit, the test unit is located in the corresponding test region; the projection of the test region on the substrate is a rectangle.

[0018] In some embodiments, the array substrate comprises a plurality of test units, a plurality of test regions are arranged in an array.

[0019] In some embodiments, the projections of the three test pads on the substrate substrate are equal in size and circular in shape, and the centers of the projections of the three test pads on the substrate substrate are collinear.

[0020] In some embodiments, one side of the projections of the two adjacent test areas on the substrate substrate coincide.

[0021] 1、In some embodiments, the array substrate further comprises:

[0022] A pixel circuit is located in the display area, and the pixel circuit comprises a plurality of thin film transistors, and the test element is consistent with the material, thickness and aspect ratio of the thin film transistors.

[0023] In a second aspect of the present application, a display device is provided, which comprises the array substrate provided in the first aspect.

[0024] According to the array substrate and the display device provided in one or more embodiments of the present application, the substrate substrate has a display area and a non-display area located on one side of the display area, and the test unit is located in the non-display area and does not affect normal display. The test unit comprises a test element, a test pad and a wire, each port of the test element corresponds to a test pad and a wire, and is connected to the corresponding test pad through the corresponding wire, and the customized probe of the EPM device is respectively inserted into each test pad of the test unit, so that the test element can be tested. The projection of the test pad on the substrate substrate is circular, compared with the square pad of the same area, the tolerance of the probe is improved, so as to increase the difficulty of the probe offsetting the pad and reduce the risk of the probe offsetting the square pad and being directly scrapped. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical scheme in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 A top view of a test element group in the related art is shown.

[0027] Figure 2 A structure schematic view of a test unit in the related art is shown. Figure 1

[0028] Figure 3 A schematic view of the offset of the pad insertion probe in the related art is shown. Figure 2

[0029] ​​Figure 4 A top view of an array substrate in one or more embodiments of the present application is shown.

[0030] Figure 5 A top view of a test unit in one embodiment of the present application is shown.

[0031] Figure 6 A top view of a test unit in one embodiment of the present application is shown. Figure 5 A schematic diagram of an offset amount of a pad-embedded probe in one embodiment of the present application is shown.

[0032] Figure 7 A schematic diagram of an offset amount of a pad-embedded probe in one embodiment of the present application is shown. Figure 5 A schematic diagram of a distribution of test units in one embodiment of the present application is shown.

[0033] Figure 8 A schematic diagram of a distribution of test units in one embodiment of the present application is shown. Figure 7 A schematic diagram of a process of a pad-embedded probe in one embodiment of the present application is shown.

[0034] Figure 9 A top view of a test unit in another embodiment of the present application is shown.

[0035] Figure 10 A top view of a test unit in another embodiment of the present application is shown. Figure 9 A schematic diagram of an offset amount of a pad-embedded probe in another embodiment of the present application is shown.

[0036] Figure 11 A schematic diagram of a distribution of test units in another embodiment of the present application is shown. Figure 9 A schematic diagram of a distribution of test units in another embodiment of the present application is shown.

[0037] Figure 12 A schematic diagram of a process of an electrical property test in one or more embodiments of the present application is shown.

[0038] BRIEF DESCRIPTION OF DRAWINGS 10': pad; 11': source pad; 12': drain pad; 13': gate pad; 20': TFT to be tested; 30': connection trace; 40': test equipment; 41': probe; 10: substrate; 11: display area; 12: non-display area; 120: test area; 20: test unit; 21: test element; 22: test pad; 23: trace. DETAILED DESCRIPTION

[0039] In order for those skilled in the art to which the present application pertains to more clearly understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0040] Figure 1For a top view schematic diagram of a TEG in the related art, please refer to Figure 1 , the TEG includes a plurality of test units, which are distributed in an array on a substrate. Each test unit includes a source pad 11', a drain pad 12', a gate pad 13', a TFT 20' to be tested, and a connection trace 30'. The source pad 11', the drain pad 12', the gate pad 13', and the TFT 20' to be tested are arranged in sequence along the row direction of the test unit array, and the source pad 11', the drain pad 12', and the gate pad 13' are connected to the TFT 20' to be tested through the connection trace 30' respectively. The connection trace 30' connected to the source pad 11' is located at a first side of the TFT 20' to be tested, the connection trace 30' connected to the drain pad 12' is located at a second side of the TFT 20' to be tested, and the connection trace 30' connected to the gate pad 13' is located at a side of the TFT 20' to be tested close to the gate pad 13'. The first side of the TFT 20' to be tested and the second side of the TFT 20' to be tested are opposite to each other and adjacent to the side of the TFT 20' to be tested close to the gate pad 13' respectively.

[0041] Figure 2 For Figure 1 , please refer to Figure 2 , the orthographic projection of the test unit on the substrate is a rectangle with a length X0=450μm and a width Y0=200μm, the orthographic projection of the source pad 11', the drain pad 12', and the gate pad 13' on the substrate is a square with a side length X1=100μm, the pad pitch X2=50μm, the width W of the placement space of the TFT 20' to be tested is 50μm, and the critical dimension CD of the connection trace 30' is 16μm. At this time, the area of the orthographic projection of the test unit on the substrate is X0*Y0=90000μm 2 , the area of the orthographic projection of the pad on the substrate is X1*X1=10000μm 2 , and the area ratio of the pad on the substrate relative to the orthographic projection of the test unit on the substrate is 3*X1*X1 / (X0*Y0)=33.33%. Figure 3 For Figure 2 , please refer to Figure 3 , the maximum offset X3 of the probe in the pad is X1 / 2=50μm, that is, the tolerance offset of the probe is 50μm.

[0042] Figure 4 For a top view schematic diagram of an array substrate in one or more embodiments of the present application, please refer to Figure 4In a first embodiment of the present application, an array substrate is provided, comprising a base substrate 10 and at least one test unit 20. The base substrate 10 has a display area 11 and a non-display area 12 located on one side of the display area 11. The test unit 20 is located in the non-display area 12.

[0043] Figure 5 This is a top view of a test unit in one embodiment of the present application. Figure 5 The test unit 20 includes a test element 21, a test pad 22, and a trace 23. Each port of the test element 21 corresponds to a test pad 22 and a trace 23, and is connected to the corresponding test pad 22 through the corresponding trace 23. The orthographic projection of the test pad 22 on the substrate 10 is a circle.

[0044] Figure 6 for Figure 5 See the diagram of the offset of the probe into the pad. Figure 6 For example, the orthographic projection of the test pad 22 on the base substrate 10 is a circle with a radius of R = 60 μm. At this time, the orthographic projection area of ​​the test pad 22 on the base substrate 10 is π*R*R = 11309.73 μm 2 , the maximum offset of the probe in the pad is X3 = 60μm, that is, the tolerance offset of the probe is 60μm. Figure 3 In comparison, the probe's tolerance offset increases from 50μm to 60μm. The probe's tolerance offset increases by (60μm-50μm) / 50μm=20%, while the pad area only increases by (11309.73μm 2 -10000μm 2 ) / 10000μm 2 =13.09%. It can be seen that, compared with a square pad of the same area, the circular test pad in the present application can improve the probe's tolerance to deviation, increase the difficulty of the probe deviating from the pad, and reduce the risk of the probe being directly scrapped due to deviation from the square pad.

[0045] In summary, the array substrate includes a substrate 10 and at least one test unit 20. The substrate 10 has a display area 11 and a non-display area 12 on one side of the display area 11, and the test unit 20 is located in the non-display area 12 and does not affect normal display. The test unit 20 includes a test element 21, a test pad 22 and a wire 23, each port of the test element 21 corresponds to the test pad 22 and the wire 23, and is connected to the corresponding test pad 22 through the corresponding wire 23. The probe is respectively inserted into each test pad 22 of the test unit 20, so that the test element 21 can be tested. The orthogonal projection of the test pad 22 on the substrate 10 is a circle. Compared with a square pad of the same area, the tolerance offset of the probe is improved, thereby increasing the difficulty of the probe offset from the pad, reducing the risk of the probe offset from the square pad and directly scrapped, prolonging the service life of the probe, and ensuring the test effect.

[0046] In some embodiments, referring to Figure 5 , the test element 21 can be a transistor with three ports, and the test unit 20 includes three test pads 22 and three wires 23, and the three test pads 22 and the three wires 23 correspond to the three ports of the test element 21 one by one.

[0047] Exemplarily, the three ports of the transistor can include a source, a drain and a gate, or can include a collector, an emitter and a base.

[0048] In a possible embodiment, referring to Figure 5 , the centers of the orthogonal projections of the three test pads 22 on the substrate 10 can not be collinear, and the line connecting the centers of the orthogonal projections of the three test pads 22 on the substrate 10 can form a triangle.

[0049] Exemplarily, referring to Figure 5 , the orthogonal projection of the two test pads 22 on the substrate 10 can be located on a first side of the orthogonal projection of the test element 21 on the substrate 10. The orthogonal projection of the other test pad 22 on the substrate 10 can be located on a second side of the orthogonal projection of the test element 21 on the substrate 10. The second side of the orthogonal projection of the test element 21 on the substrate 10 is opposite to the first side of the orthogonal projection of the test element 21 on the substrate 10. In this way, the test element 21 is arranged between the three test pads 22, so that the blank area between the three test pads 22 can be fully utilized, and the occupied space of the test unit 20 is saved.

[0050] For example, the three test pads 22 can be a first test pad, a second test pad and a third test pad respectively, and the second test pad is located between the first test pad and the third test pad. The central line of the first test pad and the third test pad on the substrate 10 is located on the first side of the central line of the test element 21 on the substrate 10. The central line of the second test pad on the substrate 10 is located on the second side of the central line of the test element 21 on the substrate 10.

[0051] For example, the triangle formed by the central line of the three test pads 22 on the substrate 10 can be an acute triangle.

[0052] For example, referring to Figure 5 , the three test pads 22 on the substrate 10 can be circular and have the same size. The distance between the centers of the three test pads 22 on the substrate 10 is equal. At this time, the central line of the three test pads 22 on the substrate 10 can form an equilateral triangle. In this way, the blank area between the three test pads 22 has a larger space, which is convenient for arranging the test element.

[0053] In some embodiments, referring to Figure 5 , the non-display area 12 includes a test area 120 corresponding to the test unit 20, and the test unit 20 is located in the corresponding test area 120. The test area 120 on the substrate 10 can be a triangle to match the arrangement of the test pads 22.

[0054] For example, the central line of the two test pads 22 located on the same side of the test element 21 can be parallel to one side of the test area 120 on the substrate 10. Still taking the example that the three test pads 22 are a first test pad, a second test pad and a third test pad respectively, and the second test pad is located between the first test pad and the third test pad, and the first test pad and the third test pad are located on the same side of the test element 21, the central line of the first test pad and the third test pad on the substrate 10 is parallel to one side of the test area 120 on the substrate 10.

[0055] For example, the test area 120 on the substrate 10 can be an equilateral triangle.

[0056] For example, referring to Figure 5, or taking the circle with the radius R = 60 μm of the orthographic projection of the test pad 22 on the substrate substrate 10 as an example, the orthographic projection of the test unit on the substrate (i.e. the test area 120) is an equilateral triangle with the side length L = 380 μm, the test pad 22 spacing D = 35 μm, the shortest distance S1 = 5 μm between the orthographic projection of the test pad 22 on the substrate substrate 10 and the edge of the test area 120, the distance S2 = (R / 2 + S1) / sin(30° / 2) = 130 μm between the center of the orthographic projection of the test pad 22 on the substrate substrate 10 and the vertex of the test area 120, the width W = (L / 2)*tan60°-(S2+2*2*R+S1) = 14 μm of the placement space of the test element 21, and the critical dimension CD = 10 μm of the wire 30. At this time, the area of the orthographic projection of the test unit on the substrate is L*(L / 2)*tan60° / 2 = 62527.03 μm 2 , and the area ratio of the test pad 22 relative to the orthographic projection of the test unit on the substrate is 3*π*R*R / (L*(L / 2)*tan60° / 2) = 54.26%. Compared with Figure 3 , the area of the orthographic projection of the test unit on the substrate is reduced from 90000 μm 2 to 62527.03 μm 2 , and the area ratio of the test pad relative to the test unit is increased from 33.33% to 54.26%. It can be seen that the arrangement mode of the test unit in the present application can improve the space utilization in the test unit and reduce the occupied area of the test unit, which is conducive to setting a larger number of test units and saving the effective area of the array substrate. In addition, the radius R of the orthographic projection of the test pad 22 on the substrate substrate 10, the critical dimension CD of the wire 30, etc. can be adjusted according to actual conditions.

[0057] Figure 7 For Figure 5 the distribution of the test unit in the present application, please refer to Figure 7 , for example, the array substrate can include a plurality of test units 20, and the plurality of test areas 120 are arranged in at least one row and multiple columns. The orthographic projection of the two adjacent test areas 120 in the same row on the substrate substrate 10 is a point-symmetrical figure. This is conducive to the neat arrangement of the test area 120 and saves the occupied space of the non-display area 12.

[0058] For example, please refer to Figure 7 , the plurality of test areas 120 are arranged in at least two rows. The orthographic projection of the two adjacent test areas 120 in the same column on the substrate substrate 10 is an axis-symmetrical figure, and the axis of symmetry is parallel to the row direction. This is conducive to the neat arrangement of the test area 120 and saves the occupied space of the non-display area 12.

[0059] For example, please refer to Figure 7The orthographic projection of two adjacent test regions 120 on the substrate 10 can coincide at one side. This facilitates the alignment of the test regions 120 and saves the space occupied by the non-display region 12.

[0060] Figure 8 For Figure 7 The process of inserting the probes into the middle pads is shown in FIG. 6. Twelve probes are used to press and connect the test elements 21 in the test region 120 in one arrangement. Then, the array substrate 10 is rotated by 180°, and the test elements 21 in the test region 120 in another arrangement are tested. Figure 8

[0061] Figure 9 For another embodiment of the test unit of the present application, please refer to FIG. 7. Figure 9 In another possible embodiment, the orthographic projection of the three test pads 22 on the substrate 10 can be arranged in the first direction. In this case, the orthographic projection of the three test pads 22 on the substrate 10 is in the same row.

[0062] For example, the three test pads 22 can be a first test pad, a second test pad and a third test pad. The second test pad is between the first test pad and the third test pad. The orthographic projection of the first test pad, the second test pad and the third test pad on the substrate 10 is in the same row.

[0063] For example, please refer to FIG. 8. Figure 9 The orthographic projection of the three test pads 22 on the substrate 10 can be on the same side of the orthographic projection of the test elements 21 on the substrate 10. The orthographic projection of the test pads 22 and the test elements 21 on the substrate 10 is arranged in the second direction, which intersects the first direction. In this way, the test elements 21 and the traces 30 are arranged on the same side of the three test pads 22, which facilitates the connection of the test elements 21 to the three test pads 22 through the traces 30 and saves the space occupied by the traces 30, thereby saving the space occupied by the test unit 20.

[0064] For example, the second direction can be perpendicular to the first direction, and the orthographic projection of one of the three test pads 22 and the test elements 21 on the substrate 10 is arranged in the second direction.

[0065] For example, please refer to FIG. 9. Figure 9 ​The three test pads 22 on the substrate 10 can be circular in shape. The centers of the three test pads 22 on the substrate 10 can be collinear. In this case, the centers of the three test pads 22 on the substrate 10 are collinear and have the same area, so that the area of each test pad 22 can be maximized and the space of the test unit can not be wasted.

[0066] In some embodiments, referring to Figure 9 The non-display area 12 includes a test area 120 corresponding to each test unit 20. The test area 120 on the substrate 10 can be rectangular to match the arrangement of the test pads 22.

[0067] For example, the test area 120 on the substrate 10 can be rectangular.

[0068] Referring to Figure 9 For example, the test area on the substrate is a rectangle with a length X0=450 μm and a width Y0=200 μm, the distance between the test pads 22 is D=(X0 / 3-R)=30 μm, the width of the placement space of the test element 21 is W=50 μm, and the critical dimension CD of the wire 30 is 10 μm. In this case, the area of the test area on the substrate is X0*Y0=90000 μm 2 The area ratio of the test pads 22 to the test area on the substrate is 3*π*R*R / (X0*Y0)=37.70%. Compared with Figure 3 The area of the test area on the substrate is unchanged, and the area ratio of the test pads to the test unit is increased from 33.33% to 37.70%.

[0069] The radius R of the test pads 22 on the substrate 10, the critical dimension CD of the wire 30, and the like can be adjusted according to actual conditions. For example, the test pads 22 on the substrate 10 are circular with a radius R=70 μm, the test area on the substrate is still a rectangle with a length X0=450 μm and a width Y0=200 μm, the distance between the test pads 22 is D=(X0 / 3-R)=10 μm, the width of the placement space of the test element 21 is W=50 μm, and the critical dimension CD of the wire 30 is 3 μm. In this case, the area of the test area on the substrate is X0*Y0=90000 μm 2 The area ratio of the test pads 22 to the test area on the substrate is 3*π*R*R / (X0*Y0)=51.31%. Compared withFigure 3 In comparison, the area of the orthographic projection of the test unit on the substrate does not change, and the area ratio of the test pad to the test unit increases from 33.33% to 51.31%. It can be seen that the arrangement of the test unit in the present application can improve the space utilization in the test unit without changing the area occupied by the test unit.

[0070] In addition, the tolerance offset of the probe is further increased. Figure 10 For Figure 9 The offset of the middle pad into the probe is shown in FIG. 6. When the orthographic projection of the test pad 22 on the substrate 10 is a circle with a radius R = 70 μm, the maximum offset X3 of the probe in the pad is 70 μm, i.e., the tolerance offset of the probe is 70 μm. Compared with the prior art shown in FIG. 5, the tolerance offset of the probe increases from 60 μm to 70 μm. Compared with the prior art shown in FIG. 4, the tolerance offset of the probe increases from 50 μm to 70 μm. Figure 10 Figure 6 Figure 3

[0071] Figure 11 For Figure 9 The distribution of the test unit is shown in FIG. 8. The array substrate can include a plurality of test units 20, and the plurality of test regions 120 are arranged in an array. This is advantageous for the neat arrangement of the test regions 120 and saves the occupied space of the non-display region 12. Figure 11 For example, the orthographic projection of the adjacent two test regions 120 on the substrate 10 can coincide at one side. This is advantageous for the neat arrangement of the test regions 120 and saves the occupied space of the non-display region 12.

[0072] Figure 11 In some embodiments, the array substrate can further include a pixel circuit, and the pixel circuit is located in the display region 11. The pixel circuit includes a plurality of thin film transistors, and the test element 21 is consistent with the material, thickness and width-length ratio of the thin film transistors.

[0073] The semiconductor lithography process forms a film layer consistent with the mask in the order of cleaning, deposition, exposure, development, etching and stripping, such as a source-drain (English: Source Drain, abbreviated: SD) layer, a gate (English: Gate) layer, a semiconductor layer and a gate insulator (English: Gate Insulator, abbreviated: GI) layer. The source-drain layer, the gate layer, the semiconductor layer and the gate insulator layer are combined to form a TFT. However, the characteristics of the TFT after the TFT is manufactured in the display region (English: Active Area, abbreviated: AA) cannot be directly obtained in the above process, and currently an EPM needs to be performed by setting a TFT TEG in the non-display region.

[0074] ​​​​​

[0075] The test unit 20 of the present application is a TFT TEG. The transistors as test elements 21 are fabricated at the same time as the TFTs in the AA using the same process, and the materials, film thicknesses, aspect ratios, etc. are consistent with the TFTs in the AA. Therefore, the test results of the transistors as test elements 21 can reflect the characteristics of the TFTs in the AA. The three ports of the transistors as test elements 21 are respectively connected to the test pads 22 through the traces 23. The probes of the test equipment are simultaneously inserted into the three test pads 22 connected to one transistor, so that the electrical characteristics of the transistors as test elements 21 can be tested. Thus, the electrical characteristics of the TFTs in the AA can be known through the test results of the transistors as test elements 21.

[0076] Figure 12 For the process schematic diagram of the EPM in one or more embodiments of the present application, please refer to Figure 12 The probes 41' of the test equipment 40' are respectively inserted into the three test pads 22 connected to the transistors as test elements 21 through the traces 23. The test signals preset are input into the test elements 21, and the feedback signals of the test elements 21 are received and processed to perform various detections, such as threshold voltage Vth, mobility, dynamic range DR Range, sub-threshold swing SS, on-state current Ion, off-state current Ioff, hysteresis Hys, contact resistance Rc, load resistance Rs, and capacitance Cap.

[0077] Exemplarily, the test equipment can include twelve probes. Each probe is inserted into one test pad 22, and the twelve probes can be simultaneously inserted into twelve test pads 22 (using single-sided crimping or double-sided crimping). Since each test element 21 is connected to three test pads 22, the twelve probes are simultaneously inserted into the pads connected to four test elements 21. The target of each probe is to be inserted into the center point of the corresponding test pad 22.

[0078] However, the probes will be plastically deformed during long-term use, causing some probes to deviate. The positions of some probes are not at the center points of the corresponding pads. Since the probes are precision devices and cannot be repaired, and the probes are expensive and have a long delivery cycle, once a probe deviates from a pad, it directly faces the risk of being scrapped.

[0079] The orthographic projection of the test pad 22 of the present application on the substrate 10 is circular. Compared with a square pad of the same area, the tolerance deviation of the probe is improved, thereby increasing the difficulty of the probe deviating from the pad, reducing the risk of the probe deviating from the square pad and being directly scrapped, prolonging the service life of the probe, and ensuring the test effect.

[0080] In the second aspect of the present application, a display device is provided, which comprises the array substrate provided in the first aspect of the present application.

[0081] In the present application, unless specifically defined and limited otherwise, the first feature is "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "over" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0082] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0083] In the present application, unless specifically defined and limited otherwise, the terms "connection", "fixing", and the like should be understood broadly, for example, "fixing" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate medium, or internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0084] In addition, in the present application, the description such as "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless specifically defined and limited otherwise.

[0085] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate (10) having a display area (11) and a non-display area (12) located on one side of the display area (11); at least one test unit (20) located in the non-display area (12); the test unit (20) comprises a test element (21), a test pad (22) and a trace (23); each port of the test element (21) corresponds to the test pad (22) and the trace (23), and is connected to the corresponding test pad (22) through the corresponding trace (23); the orthogonal projection of the test pad (22) on the substrate (10) is circular.

2. The array substrate of claim 1, wherein, The test element (21) is a transistor with three ports, and the test unit (20) comprises three test pads (22) and three traces (23), and the three test pads (22) and the three traces (23) correspond to the three ports of the test element (21) one by one.

3. The array substrate of claim 2, wherein, The centers of the orthogonal projections of the three test pads (22) on the substrate (10) are not collinear.

4. The array substrate of claim 3, wherein, The orthogonal projections of two test pads (22) on the substrate (10) are located on a first side of the orthogonal projection of the test element (21) on the substrate (10); the orthogonal projection of the other test pad (22) on the substrate (10) is located on a second side of the orthogonal projection of the test element (21) on the substrate (10), and the second side is opposite to the first side.

5. The array substrate of claim 4, wherein, The non-display area (12) comprises a test area (120) corresponding to the test unit (20), and the test unit (20) is located in the corresponding test area (120); the orthogonal projection of the test area (120) on the substrate (10) is a triangle.

6. The array substrate of claim 5, wherein, The center line of the two test pads (22) located on the same side of the test element (21) is parallel to one side of the triangle.

7. The array substrate of claim 5, wherein, The array substrate comprises a plurality of test units (20), and a plurality of test areas (120) are arranged in at least one row and multiple columns; the orthogonal projections of two adjacent test areas (120) in the same row on the substrate (10) are point-symmetric patterns.

8. The array substrate of claim 6, wherein, A plurality of test areas (120) are arranged in at least two rows; the orthogonal projections of two adjacent test areas (120) in the same column on the substrate (10) are axis-symmetric patterns, and the axis of symmetry is parallel to the row direction.

9. The array substrate according to any one of claims 3-8, wherein, The orthogonal projections of the three test pads (22) on the substrate (10) are circular and have equal sizes, and the distances between the centers of the orthogonal projections of the three test pads (22) on the substrate (10) are equal.

10. The array substrate of claim 2, wherein, The orthogonal projections of the three test pads (22) on the substrate (10) are arranged in a first direction.

11. The array substrate of claim 10, wherein, Projections of the three test pads (22) on the substrate (10) are on the same side of the projection of the test element (21) on the substrate (10); the projections of the test pads (22) and the test element (21) on the substrate (10) are arranged along a second direction, which intersects the first direction.

12. The array substrate of claim 11, wherein, The non-display area (12) includes a test area (120) corresponding to each test unit (20), and the test unit (20) is located in the corresponding test area (120); the projection of the test area (120) on the substrate (10) is rectangular.

13. The array substrate of claim 12, wherein, The array substrate includes a plurality of test units (20), and the plurality of test areas (120) are arranged in an array.

14. The array substrate according to any one of claims 10-13, wherein, The projections of the three test pads (22) on the substrate (10) are circular and have the same size, and the centers of the projections of the three test pads (22) on the substrate (10) are collinear.

15. The array substrate according to any one of claims 7, 8, 13, wherein, The projections of two adjacent test areas (120) on the substrate (10) coincide on one side.

16. The array substrate of any one of claims 2-8, 10-13, wherein, The array substrate further includes: A pixel circuit is located in the display area (11); the pixel circuit includes a plurality of thin film transistors, and the test element (21) has the same material, thickness, and width-length ratio as the thin film transistors.

17. A display device comprising: The display device includes the array substrate according to any one of claims 1-16.

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