Semiconductor package

Abstract

A semiconductor package is provided. A semiconductor package may include a substrate, a first package component bonded to the substrate, and a first cooling system over the first package component. The first package component may include a first semiconductor die. The first cooling system may include a first base at the first package component, wherein the first base may include a first recess, a first pin protruding from a bottom of the first recess, and a first raised portion surrounding the recess in a top view. The first cooling system may include a cover member over the first base, wherein the cover may be spaced apart from the first pin. The first cooling system may also include an encapsulant connecting the cover to the first raised portion of the first base.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor package with a cooling system and a method of manufacturing the same. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to the continual improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, the improvement in integration density has come from the continual reduction in the minimum feature size, which allows more components to be integrated into a given area. SUMMARY

[0003] Some embodiments of the present application provide a semiconductor package. The semiconductor package includes a substrate, a first package component, and a first cooling system. The first package component is bonded to the substrate, the first package component including a first semiconductor die. The first cooling system is positioned over the first package component, the first cooling system including a first base, a lid, and a sealant. The first base is positioned over the first package component, wherein the first base includes a first recess, a first pin, and a first raised portion, the first pin protruding from a bottom of the first recess, and the first raised portion encloses the first recess in a top view. The lid is positioned over the first base, wherein the lid is spaced apart from the first pin. The sealant connects the lid to the first raised portion of the first base.

[0004] According to some embodiments, the first package component further includes a second semiconductor die stacked on the first semiconductor die, wherein the first semiconductor die is a logic die and the second semiconductor die is a memory die.

[0005] According to some embodiments, further comprising a first dielectric bonding layer and a second dielectric bonding layer positioned between the first package component and the first base.

[0006] According to some embodiments, the first base further includes a second pin, a third pin, and a fourth pin protruding from the bottom of the first recess, wherein the first pin, the second pin, the third pin, and the fourth pin are the same size in the top view, and the first pin, the second pin, the third pin, and the fourth pin are arranged in a staggered array in the top view.

[0007] According to some embodiments, the first base further includes a second pin, a third pin, and a fourth pin protruding from the bottom of the first recess, wherein the first pin and the second pin are larger than the third pin and the fourth pin in the top view.

[0008] According to some embodiments, the first pin and the second pin are spaced apart by a first pitch, and the third pin and the fourth pin are spaced apart by a second pitch, wherein the first pitch is greater than the second pitch.

[0009] Some embodiments of the present application provide a semiconductor package. The semiconductor package includes a substrate, a first package component, and a first cooling system. The first package component is bonded to the substrate, and the first package component includes two or more semiconductor dies stacked vertically. The first cooling system is positioned over the first package component, and the first cooling system includes a first base and a lid. The first base is bonded to the first package component, wherein the first base includes a first recess, a first pin protruding from a bottom of the first recess, a second recess, a second pin protruding from a bottom of the second recess, and a first raised portion positioned between the first recess and the second recess. The lid is attached to the first base.

[0010] According to some embodiments, top surfaces of the first pin and the second pin of the first base are exposed, and a top surface of the first raised portion of the first base is in contact with a sealant on a bottom surface of the lid.

[0011] According to some embodiments, the lid includes a first coolant inlet and a first coolant outlet facing the first recess of the first base, and the lid further includes a second coolant inlet and a second coolant outlet facing the second recess of the first base.

[0012] According to some embodiments, the lid includes a first coolant inlet and a first coolant outlet facing the first recess of the first base, and the lid further includes a second coolant inlet and a second coolant outlet facing the second recess of the first base. BRIEF DESCRIPTION OF DRAWINGS

[0013] The concepts of the embodiments of the present application will be better understood from the following detailed description with reference to the drawings. It is noted that the various features of the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily expanded or reduced for the clarity of presentation.

[0014] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4A 、 Figure 4B 、 Figure 4C 、 Figure 4D 、 Figure 5 、 Figure 6A 、 Figure 6B 、 Figure 7 、 Figure 8A 、 Figure 8B and Figure 8C show cross-sectional and top views of intermediate stages in the formation of an integrated circuit package with a cooling system according to some embodiments.

[0015] REFERENCE NUMERALS

[0016] 50: integrated circuit die layer

[0017] 50': integrated circuit die component

[0018] 51: first bonding layer

[0019] 52: material layer

[0020] 53: second bonding layer

[0021] 54: isolation layer

[0022] 55: element layer

[0023] 56: logic die

[0024] 56A: substrate

[0025] 56B: bonding layer

[0026] 56C: interconnect structure

[0027] 56D: conductive via

[0028] 56E: conductive pad

[0029] 58: memory die

[0030] 58A: substrate

[0031] 58B: top bonding layer

[0032] 58C: interconnect structure

[0033] 58D: bottom bonding layer

[0034] 58E: conductive via

[0035] 58F: top conductive pad

[0036] 58G: bottom conductive pad

[0037] 60: cooling system base layer

[0038] 60': cooling system base component

[0039] 62: under bump metallization layer

[0040] 64: electrical connector

[0041] 66: adhesive

[0042] 68: carrier

[0043] 70: first integrated circuit package structure 72: pin 72A, 72B:

[0044] 74: raised portion

[0045] 75: recess

[0046] 76, 78: regions

[0047] 80: adhesive tape

[0048] 82: frame

[0049] 84: scribe line

[0050] 100: second integrated circuit package structure

[0051] 100': integrated circuit package component

[0052] 110: underfill

[0053] 120: encapsulant

[0054] 150: cooling system cover component

[0055] 152: body

[0056] 154: adapter

[0057] 156: opening

[0058] 156A: inlet

[0059] 156B: outlet

[0060] 158: coolant distribution network

[0061] 180: cooling system

[0062] 200: package substrate

[0063] 202: conductive pad

[0064] 204: pump system

[0065] 206: memory

[0066] 250: integrated circuit package

[0067] D1, D2: distance

[0068] D4: distance

[0069] H1: first height

[0070] H2: second height

[0071] L2, L3, L4: length

[0072] T1: total thickness

[0073] W1, W2, W3, W4: width

[0074] A-A': reference section DETAILED DESCRIPTION

[0075] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the embodiments of the present application. Specific examples of elements and configurations are described herein to facilitate discussion of the embodiments of the present application. It should be understood by those skilled in the art, however, that these specific examples and configurations are not intended to limit the scope of the embodiments of the present application. Rather, they are provided as examples for discussion of various embodiments of the present application. For example, reference is made below to a first feature being formed on or over a second feature, which should be interpreted as including embodiments where a first feature is formed directly on or over a second feature, as well as embodiments where additional features are formed between the first and second features such that the first and second features are not directly in contact. In addition, the present application can make reference to use of the same reference numerals in various examples. This reference by itself is not intended to be construed as a limitation on the scope of the application, but is simply used to facilitate describing the various embodiments of the present application.

[0076] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0077] An integrated circuit package having a cooling system and a method of forming the same are provided. According to some embodiments, the integrated circuit package includes one or more integrated circuit die components and a cooling system positioned over the one or more integrated circuit die components. A lower portion of the cooling system can be formed of a material having a high thermal conductivity and can include a plurality of enclosed compartments positioned over each of the one or more integrated circuit die components, with a plurality of pins protruding from a bottom of the enclosed compartments. An upper portion of the cooling system can be sealed to the lower portion of the cooling system and can include a coolant distribution network. Each of the one or more integrated circuit die components can include an integrated circuit die or a stack of integrated circuit dies. Heat generated by the integrated circuit die or the stack of integrated circuit dies can be effectively transferred to a liquid coolant flowing through the cooling system directed by the coolant distribution network. As a result, the one or more integrated circuit die components can be effectively cooled during operation of the integrated circuit package, thereby improving the performance and reliability of the integrated circuit package.

[0078] Figures 1 to 8CVarious intermediate stages of manufacturing an integrated circuit package having an embodiment cooling system are shown. Although Figures 1 to 8C A particular type of package is shown, but it should be understood that various embodiment cooling systems can also be attached to other types of semiconductor packages. In Figure 1 In the middle, the material layer 52 is bonded to the integrated circuit die layer 50 by the first bonding layer 51 and the second bonding layer 53. The integrated circuit die layer 50 can include an element layer 55 and an isolation layer 54. The isolation layer 54 can be on a first side of the element layer 55, and the second bonding layer 53 can be on a second side of the element layer 55 opposite the first side.

[0079] The element layer 55 can include a plurality of elements (not shown individually) and conductive features (not shown individually). By way of example, the element layer 55 can include one or more layers of active elements (e.g., transistors, etc.) formed on one or more semiconductor substrates. The conductive features in the interconnect structure can be used to electrically connect the active elements together to form functional circuitry. The integrated circuit die layer 50 can be singulated into a plurality of integrated circuit die parts, which can include integrated circuit dies or stacks of integrated circuit dies, in a subsequent singulation process, as described in more detail below. The material layer 52 can be subsequently patterned and singulated to form a cooling system over the integrated circuit die parts, as also described in more detail below. The material layer 52 can include a material having a high thermal conductivity, such as silicon, silicon carbide, chemical vapor deposition (CVD) diamond (e.g., synthetic diamond), etc., which can result in effective cooling of the subsequently formed integrated circuit die parts by the subsequently formed cooling system. In some embodiments, the isolation layer 54 includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), etc., and is formed by a suitable coating process, such as spin coating, lamination, etc. In some embodiments, the isolation layer 54 includes silicon dioxide, silicon nitride, etc., and is formed by a suitable deposition process, such as CVD, atomic layer deposition (ALD), etc.

[0080] Prior to the bonding process, a first bonding layer 51 can be formed on the material layer 52, and a second bonding layer 53 can be formed on the integrated circuit die layer 50. The first bonding layer 51 and the second bonding layer 53 can be formed by a suitable deposition process, such as CVD, ALD, etc. The first bonding layer 51 and the second bonding layer 53 can each include an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethylorthosilicate (TEOS)-based material, etc.; a nitride, such as silicon nitride, etc.; or other similar materials. The first bonding layer 51 and the second bonding layer 53 can include the same material or different materials. An activation process (e.g., a plasma process, a wet clean, a combination thereof, etc.) can be applied to one or more of the first bonding layer 51 or the second bonding layer 53. For example, a plasma process can form hydroxyl groups on the surface of the first bonding layer 51 and / or the second bonding layer 53 to prepare for a subsequent bonding process.

[0081] During the bonding process, a pick-and-place process or the like can be used to place the material layer 52 (with the first bonding layer 51) on the second bonding layer 53 over the integrated circuit die layer 50, where the first bonding layer 51 can be in contact with the second bonding layer 53. A small pressing force can then be applied to press the material layer 52 against the integrated circuit die layer 50 at room temperature. Direct bonds, such as dielectric-to-dielectric bonds, can be formed between the first bonding layer 51 and the second bonding layer 53. The bonding strength between the first bonding layer 51 and the second bonding layer 53 can then be improved in a subsequent higher-temperature annealing process. After the bonding process, the total thickness T1 of the first bonding layer 51 and the second bonding layer 53 can be less than about 100 nm, which can result in more efficient heat transfer from a subsequently formed integrated circuit die component (which can include an integrated circuit die or a stack of integrated circuit dies) to a subsequently formed cooling system, as described in more detail below.

[0082] In Figure 2In some embodiments, a plurality of under-bump metallizations (UBMs) 62 and electrical connectors 64 are formed. The under-bump metallizations 62 can have portions that extend along the surface of the isolation layer 54 and portions that extend through the isolation layer 54 to physically and electrically couple to conductive features (not shown separately) in the element layer 55. The electrical connectors 64 can be formed on the under-bump metallizations 62. Thus, the under-bump metallizations 62 and the electrical connectors 64 can be electrically coupled to elements (not shown separately) in the element layer 55. Figure 2 The structure shown in FIG. 1 can be referred to as a first integrated circuit package structure 70.

[0083] As an example of forming the under-bump metallizations 62, the isolation layer 54 can be patterned to form openings that expose underlying conductive features in the element layer 55. The patterning can be achieved by suitable photolithography and etching processes, such as forming a mask and then performing a non-isotropic etch. The mask can be removed after the patterning. A seed layer (not shown separately) can be formed on the isolation layer 54, in the openings through the isolation layer 54, and on the exposed conductive features in the element layer 55. The seed layer can be a metal layer, which can be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on the titanium layer. The seed layer can be formed using suitable deposition processes, such as physical vapor deposition (PVD), etc. A photoresist can then be formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The patterning can be through openings in the photoresist to expose portions of the seed layer. The openings can correspond to the under-bump metallizations 62.

[0084] A conductive material can be formed in the openings in the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroless plating, electroplating, etc. The conductive material can include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, etc., or combinations thereof. The photoresist and the portions of the seed layer on which the conductive material is not formed can then be removed. The photoresist can be removed by acceptable ashing or stripping processes, such as using oxygen plasma, etc. Once the photoresist is removed, the portions of the seed layer on which the conductive material is not formed can be removed by acceptable etching processes, such as by wet or dry etching. The remaining portions of the seed layer and the conductive material can be referred to as the under-bump metallizations 62.

[0085] An electrical connector 64 can then be formed on the under bump metallization layer 62. The electrical connector 64 can be a ball grid array (BGA) connector, a solder ball, a metal stud, a controlled collapse chip connection (C4) bump, a micro bump, an electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bump, or the like. In some embodiments, the electrical connector 64 includes an electrically conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like or a combination thereof. In such embodiments, the electrical connector 64 can be formed by first forming a layer of the electrically conductive material on the under bump metallization layer 62 by evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the layer of the electrically conductive material is formed on the under bump metallization layer 62, reflow can be performed to shape the layer of the electrically conductive material into the desired bump shape. In some embodiments, the electrical connector 64 includes a metal stud, such as a copper stud, formed by sputtering, printing, electroplating, electroless plating, PVD, CVD, or the like, which is solder free and has substantially vertical sidewalls. A metal cap layer can be formed on top of the metal stud. The metal cap layer can include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or the like or a combination thereof, and can be formed by plating.

[0086] In Figure 3 the first integrated circuit package structure 70 is attached to a carrier 68 by an adhesive 66. The carrier 68 can be a semiconductor carrier, a glass carrier, a ceramic carrier, or the like. The adhesive 66 can be located between the isolation layer 54 and the carrier 68, and can cover the surface of the under bump metallization layer 62 and the electrical connector 64. The adhesive 66 can separate the electrical connector 64 from the carrier 68. The first integrated circuit package structure 70 can be attached to the carrier 68 by applying the adhesive 66 on the carrier 68, placing the first integrated circuit package structure 70 on the carrier 68, and curing the adhesive 66.

[0087] In Figure 4AIn some embodiments, the material layer 52 is patterned to form a cooling system base layer 60. The cooling system base layer 60 can include a plurality of raised portions 74, a plurality of recessed portions 75 between the raised portions 74, and a plurality of pins 72 protruding from the bottom of the recessed portions 75. The pins 72 and the raised portions 74 can comprise the same material as the material layer 52. The patterning can be achieved by suitable photolithography and etching processes, such as forming a mask, performing anisotropic etching, and removing the mask. The anisotropic etching can be a dry etching, such as deep reactive-ion etching (DRIE), or the like. The etchant for the anisotropic etching can be fluorine or the like. The raised portions 74 can have a first height H1 in a range between about 50 pm to about 300 pm. The pins 72 can have a second height H2 in a range between about 50 pm to about 300 pm. In some embodiments, the first height H1 is equal to the second height H2.

[0088] Figure 4B The display Figure 4A A top view of the region 76 shown in Figure 4A The cross-sectional view shown in Figure 4B The reference section A-A’ in the top view shown in Figure 4B As shown, the raised portions 74 can divide the region 76 into one or more enclosed compartments, which correspond to the one or more recessed portions 75. Each recessed portion 75 and the pins 72 protruding from the bottom of the recessed portion 75 are enclosed by the raised portions 74. The raised portions 74 can confine the liquid coolant within each enclosed compartment, while heat can be transferred from the pins 72 and the raised portions 74 to the liquid coolant during operation of the cooling system formed subsequently, as described in more detail below. Figure 4B Four enclosed compartments in the region 76 are shown as an example, however the region 76 can have other numbers of enclosed compartments.

[0089] In Figure 4BIn the illustrated embodiment, the pins 72 within each enclosed compartment (e.g., recess 75) form a staggered array, wherein adjacent pins 72 have the same spacing D1, the top surfaces of the pins 72 have the same shape and the same size, and the enclosed compartments have the same shape and the same size. The spacing D1 can be in the range of about 100 μm and about 500 μm. The top surface of the pins 72 can have a circular shape, and its width W1 (e.g., diameter) can be in the range of about 100 μm and about 500 μm. The enclosed compartments can have a rectangular shape, and its length L2 can be in the range of about 5 mm and about 15 mm, and its width W2 can be in the range of about 5 mm and about 15 mm. In other embodiments, the pins 72 can form a different pattern, the top surface of the pins 72 can have other shapes and sizes, and the enclosed compartments can have other shapes and sizes.

[0090] Figure 4C Displaying a display similar to some embodiments Figure 4B A top view of region 76 is shown, where like symbols represent like features formed by the same process. Within some enclosed compartments of region 76 (e.g., recess 75), pins 72 may be spaced at different pitches, and the top surfaces of pins 72 may have different sizes. Pins 72A in an area (e.g., region 78) that may be above a hotspot of a subsequently formed integrated circuit die component may be spaced at a smaller pitch and have a top surface of a smaller width than pins 72B in the same enclosed compartment, which may result in more efficient cooling of the subsequently formed integrated circuit die component. As described in more detail below. Figure 4C In the illustrated embodiment, pins 72A in region 78 near a corner of an enclosed compartment are spaced apart at a spacing D2 and have a top surface having a width W2, while pins 72B in the same enclosed compartment are spaced apart at a spacing D1 that is greater than spacing D2 and have a top surface having a width W1 that is greater than width W2.

[0091] Figure 4D Displaying a display similar to some embodiments Figure 4B A top view of region 76 is shown, wherein like symbols represent like features formed by like processes. Figure 4DIn the illustrated embodiment, the pins 72 within each enclosed compartment (e.g., recess 75) form a staggered array with the same spacing Dl between adjacent pins 72, and the top surfaces of the pins 72 have the same shape and the same dimensions. The top surfaces of the pins 72 have a pear (or teardrop) shape. The pear shape has a narrow end and a wide end. The length L3 from the narrow end to the wide end can be in a range between about 100 pm and about 500 pm. The width W3 of the wide end can be in a range between about 100 pm and about 500 pm. When the top surfaces of the pins 72 have the pear shape, the fluid dynamics (e.g., velocity) of the liquid coolant can be improved when the liquid coolant flows in a direction from the wide end to the narrow end, which can result in turbulent flow of the liquid coolant. As a result, more effective cooling of subsequently formed integrated circuit die components can be achieved, as described in more detail below.

[0092] In Figure 5 , the carrier 68 and the adhesive 66 (shown in Figure 4A ) are removed. The adhesive 66 can be removed by dissolving the adhesive 66 with a suitable solvent. After the adhesive 66 is removed, the carrier 68 can be removed and the electrical connectors 64 can be exposed. Figure 5 The structure shown in

[0093] In Figure 6A , the second integrated circuit package structure 100 is singulated to form a plurality of individual integrated circuit package components 100’. The second integrated circuit package structure 100 can be placed on the tape 80 supported by the frame 82. The second integrated circuit package structure 100 can then be singulated along the scribe lines 84 so that the second integrated circuit package structure 100 can be divided into a plurality of individual integrated circuit package components 100’. At the same time, the integrated circuit die layer 50 can be divided into a plurality of individual integrated circuit die components 50’, and the cooling system base layer 60 can be divided into a plurality of individual cooling system base components 60’. Each integrated circuit package component 100’ can include a cooling system base component 60’ positioned above an integrated circuit die component 50’. A top view of each integrated circuit package component 100’ can be the same as or similar to the top views shown in Figure 4B , 4C and 4D. The singulation process can include a sawing process, a laser cutting process, or the like. A cleaning process or a rinsing process can be performed after the singulation process.

[0094] Each integrated circuit die component 50’ can include an integrated circuit die or a stack of integrated circuit dies (not shown separately). The integrated circuit die can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc.

[0095] The integrated circuit die can include a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate can include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates can also be used, such as a multilayer or graded substrate. The integrated circuit die can include elements located on an active surface of the semiconductor substrate. The elements can be active elements (e.g., transistors, diodes, etc.), capacitors, resistors, etc.

[0096] The integrated circuit die can also include an interconnect structure on the active surface of the semiconductor substrate. The interconnect structure can interconnect the elements to form the integrated circuit. The interconnect structure can include metallization patterns in dielectric layers. The dielectric layers can be low- k dielectric layers. The metallization patterns can include metal lines and vias that can be formed in the dielectric layers by a damascene process (e.g., a single damascene process, a dual damascene process, etc.). The metallization patterns can be formed of suitable conductive materials, such as copper, tungsten, aluminum, silver, gold, combinations thereof, etc. The metallization patterns can be electrically coupled to the elements. Conductive vias can be disposed in the semiconductor substrate. The conductive vias can be electrically coupled to the metallization patterns of the interconnect structure.

[0097] Figure 6B An example of the composition of the integrated circuit die component 50’ is shown, where the integrated circuit die component 50’ includes a stack of integrated circuit dies that includes a logic die 56 (e.g., CPU, GPU, SoC, AP, microcontroller) in an element layer 55 and a stack of multiple memory dies 58 (e.g., DRAM, SRAM). The stack of multiple memory dies 58 can be referred to as a high bandwidth memory (HBM) stack. The logic die 56 can be at the bottom of the element layer 55. The logic die 56 can include a substrate 56A, a bond layer 56B on a first side of the substrate 56A, and an interconnect structure 56C on a second side of the substrate 56A. The interconnect structure 56C can be in contact with the isolation layer 54. Conductive vias 56D can extend through the substrate 56A and be electrically coupled to a metallization pattern (not shown) of the interconnect structure 56C and a conductive pad 56E in the bond layer 56B. The metallization pattern of the interconnect structure 56C can be electrically coupled to the under bump metallization layer 62.

[0098] The stack of memory dies 58 is on the bond layer 56B of the logic die 56. Some of the stack of memory dies 58 can include a substrate 58A, a top bond layer 58B on a first side of the substrate 58A, an interconnect structure 58C on a second side of the substrate 58A, and a bottom bond layer 58D on the interconnect structure 58C. Conductive vias 58E can extend through the substrate 58A and be electrically coupled to a metallization pattern (not shown) of the interconnect structure 58C and a top conductive pad 58F in the top bond layer 58B. The metallization pattern of the interconnect structure 58C can be electrically coupled to a bottom conductive pad 58G in the bottom bond layer 58D. The memory die 58 at the top of the stack of memory dies 58 can include a substrate 58A, an interconnect structure 58C on a second side of the substrate 58A, and a bottom bond layer 58D on the interconnect structure 58C. A metallization pattern (not shown) of the interconnect structure 58C can be electrically coupled to a bottom conductive pad 58G in the bottom bond layer 58D. The first side of the substrate 58A can be in contact with the second bond layer 53.

[0099] The bonding layer 56B, the top bonding layer 58B, and the bottom bonding layer 58D can include a dielectric material, such as silicon oxide, silicon nitride, or the like. The conductive pad 56E, the top conductive pad 58F, and the bottom conductive pad 58G can include a metal, such as copper, aluminum, or the like. The logic die 56 and the memory dies 58 at the bottom of the stack of memory dies 58 can be bonded together by dielectric-to-dielectric bonding and metal-to-metal bonding, where the bonding layer 56B can be bonded to the bottom bonding layer 58D by dielectric-to-dielectric bonding, and the conductive pad 56E can be bonded to the bottom conductive pad 58G by metal-to-metal bonding. Adjacent memory dies 58 can be bonded together by dielectric-to-dielectric bonding and metal-to-metal bonding, where the top bonding layer 58B can be bonded to the adjacent bottom bonding layer 58D by dielectric-to-dielectric bonding, and the top conductive pad 58F can be bonded to the adjacent bottom conductive pad 58G by metal-to-metal bonding. Thus, each of the stack of logic die 56 and memory dies 58 can be electrically coupled to one another.

[0100] In Figure 7 the integrated circuit package component 100’ is bonded to a package substrate 200, and a bottom fill 110 is formed between the integrated circuit package component 100’ and the package substrate 200. The package substrate 200 can include a conductive pad 202. In some embodiments, the package substrate 200 includes a material such as fiberglass reinforced resin, bismaleimide-triazine (BT) resin, other printed circuit board (PCB) materials, or the like. In some embodiments, the package substrate 200 includes a material such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, arsenic gallium phosphide, gallium indium phosphide, or the like.

[0101] The package substrate 200 can include active and / or passive elements (not shown separately), such as transistors, capacitors, resistors, combinations thereof, or the like. These active and / or passive elements can be formed using any suitable method. The package substrate 200 can include a metallization layer (not shown separately) that is physically and electrically coupled to the conductive pad 202. The metallization layer can be formed over the active and / or passive elements and can connect the active and / or passive elements to form functional circuitry. The metallization layer can be alternating layers of a dielectric material (e.g., a low dielectric constant dielectric material) and a conductive material (e.g., copper), and have conductive vias that interconnect the layers of conductive material. In some embodiments, the package substrate 200 is devoid of active and passive elements.

[0102] During the bonding process, the electrical connectors 64 can be reflowed to bond the integrated circuit package components 100’ to the conductive pads 202. The electrical connectors 64 can physically and electrically couple the package substrate 200 to the integrated circuit package components 100’. In some embodiments, a solder resist (not shown separately) is formed on the package substrate 200. The electrical connectors 64 can be disposed in openings in the solder resist to physically and electrically couple to the conductive pads 202. The solder resist can be used to protect areas of the package substrate 200 from external damage.

[0103] The underfill 110 can surround the electrical connectors 64 and protect the joints created due to the reflow of the electrical connectors 64. In a top view, the underfill 110 can surround the integrated circuit package components 100’. The underfill 110 can be formed by a capillary flow process after the integrated circuit package components 100’ are attached, or by a suitable deposition method before the integrated circuit package components 100’ are attached. The underfill 110 can be subsequently cured. Figure 7 The layout of the integrated circuit package components 100’ on the package substrate 200 shown in FIGS. 1-3 is merely an example, and other layouts can be contemplated. Figure 7 It is shown as an example that the integrated circuit package components 100’ on the package substrate 200 have the same height, however the integrated circuit package components 100’ on the package substrate 200 can have different heights.

[0104] Figures 1 to 7 An integrated circuit die component 50’ is shown according to some embodiments as an integrated circuit die or a stack of integrated circuit dies. In other embodiments, the integrated circuit die component 50’ can be an integrated circuit package including an integrated circuit die or a stack of integrated circuit dies. The integrated circuit package can be a system on integrated chips (SoIC) package, an integrated fan-out on substrate (InFO) package, a chip on wafer on substrate (CoWoS) package, etc.

[0105] In Figure 8A , Figure 8B and Figure 8C The cooling system lid component 150 is attached to the cooling system base component 60’ by the sealant 120 in Figure 8A The cross-sectional view shown in FIG. 3 can be taken along the reference section A-A’ in the top view shown in Figure 8B and 8C where like symbols refer to like features formed by the same process. FIG. B shows a cross-sectional view taken along the reference section A-A’ in the top view shown in Figure 8Aa top view of region 76 shown in FIG. 1 1 1. For illustrative purposes, the cooling system base component 60' is shown in FIG. 1 1 1 without the cooling system lid component 150 and the sealant 120. Figure 8C The cooling system lid component 150, the sealant 120, and the cooling system base component 60' can be collectively referred to as a cooling system 180. Figure 8A and Figure 8C The structure shown in FIG. 1 1 1 can be referred to as an integrated circuit package 250. During operation of the integrated circuit package 250, the cooling system 180 can utilize a liquid coolant to cool the underlying integrated circuit die component 50'.

[0106] The sealant 120 can be applied to the top surface of the raised portion 74 of the cooling system base component 60' prior to placing the cooling system lid component 150 on the cooling system base component 60', where the sealant 120 can contact the bottom surface of the cooling system lid component 150. In some embodiments, the sealant 120 comprises a polymeric material and is subsequently cured. In some embodiments, the sealant 120 comprises a metallic material, such as a thermal interface material (TIM). The pins 72 can be spaced apart from the cooling system lid component 150, and the top surface of the pins 72 can be exposed. Figure 8A The sealant 120 on the cooling system base component 60' is shown as having the same height as an example, however the sealant 120 on the cooling system base component 60' can have different heights when the cooling system base component 60' has different heights, such that one cooling system lid component 150 can be used to form a cooling system 180 with cooling system base components 60' having different heights.

[0107] The cooling system lid component 150 can comprise a main body 152 and a plurality of adapters 154. The main body 152 can comprise a coolant distribution network 158 and a plurality of openings 156. Figure 8A An example of a flow path of the liquid coolant is shown with dashed lines with arrows to illustrate an embodiment of the coolant distribution network 158. For illustrative purposes, the openings 156 are shown in FIG. 1 1 1 without the cooling system base component 60'. Figure 8A and 8CThe plurality of adapters 154 can be connected to the external inlet and the external outlet, respectively, for flowing the liquid coolant into and out of the cooling system 180. The pump system 204 can be connected to the cooling system 180 through the adapters 154. The pump system 204 can move the liquid coolant from the reservoir 206 into the cooling system 180, and from the cooling system 180 into the reservoir 206. The plurality of openings 156 can face the recesses 75 and the pins 72 of the cooling system base component 60', and the plurality of openings 156 can include a plurality of inlets 156A and outlets 156B for flowing the liquid coolant into and out of the plurality of enclosed compartments (e.g., recesses 75) of the cooling system base component 60', respectively. The coolant distribution network 158 can be connected to the adapters 154 and the openings 156, and can direct the delivery of the liquid coolant in the cooling system 180.

[0108] The sealant 120 can extend between the top surface of the raised portion 74 of the cooling system base component 60' and the bottom surface of the cooling system cover component 150. The sealant 120 can seal a portion of the cooling system cover component 150 to the underlying corresponding enclosed compartment of the cooling system base component 60', which can confine the liquid coolant within the enclosed compartment. One or more sealed enclosed compartments can be located in each cooling system base component 60' above the corresponding integrated circuit die component 50'. When a plurality of sealed enclosed compartments are provided above the corresponding integrated circuit die component 50', the integrated circuit die component 50' can be more effectively cooled during operation of the integrated circuit package 250.

[0109] The cooling system cover component 150 can be formed of copper, stainless steel, polymer, etc. In the illustrated embodiment, the cooling system cover component 150 is formed of copper. Figure 8C In the illustrated embodiment, the plurality of openings 156 have the same shape and the same size. The openings 156 can have a rectangular shape with a length L4 in a range between about 5 mm and about 15 mm, and a width W4 in a range between about 1 mm and about 2 mm. Two openings 156 (which can be a pair of an inlet and an outlet) are provided on opposite sides of each enclosed compartment (e.g., recess 75). The two openings 156 can be spaced apart by a distance D4 in a range between about 3 mm and about 11 mm. Figure 8C The layout of the openings 156 in the illustrated cooling system cover component 150 is merely exemplary, and other layouts can be contemplated. The sealant 120 can be formed of epoxy, silicone, etc. The liquid coolant can be deionized water, glycol-based coolant, etc.

[0110] As an example of the working principle of cooling system 180 during operation of integrated circuit package 250, liquid coolant can flow into cooling system 180 via one adapter 154 (e.g., an inlet) and be distributed by coolant distribution network 158 to inlet 156A above each enclosed compartment. Liquid coolant can enter and flow through the enclosed compartment while contacting corresponding pin 72 and corresponding raised portion 74 of corresponding cooling system base component 60'. At the same time, heat generated in integrated circuit die component 50' under cooling system base component 60' can be transferred to cooling system base component 60' through first bonding layer 51 and second bonding layer 53. When liquid coolant contacts pin 72 and raised portion 74, heat can be further transferred to liquid coolant. Liquid coolant can then exit each enclosed compartment through outlet 156B disposed above the enclosed compartment and be directed by coolant distribution network 158 to another adapter 154 (e.g., an outlet) to flow out of cooling system 180. Thus, integrated circuit die component 50' can be effectively cooled during operation of integrated circuit package 250.

[0111] The described embodiments can have some advantageous features. By forming cooling system 180 over integrated circuit die component 50', heat generated by integrated circuit die component 50' can be effectively transferred to liquid coolant flowing through cooling system 180. Thus, integrated circuit die component 50' can be effectively cooled during operation of integrated circuit package 250, thereby improving the performance and reliability of integrated circuit package 250.

[0112] In some embodiments, a semiconductor package includes a substrate, a first package component, and a first cooling system. The first package component is bonded to the substrate, the first package component including a first semiconductor die. The first cooling system is located over the first package component, the first cooling system including a first base, a lid, and a sealant. The first base is located over the first package component, wherein the first base includes a first recess, a first pin, and a first raised portion, the first pin protruding from a bottom of the first recess, and the first raised portion encloses the first recess in a top view. The lid is located over the first base, wherein the lid is spaced apart from the first pin. The sealant connects the lid to the first raised portion of the first base. In some embodiments, the first raised portion and the first pin of the first base include a same first material. In some embodiments, the first material is silicon. In some embodiments, the first package component further includes a second semiconductor die stacked on the first semiconductor die, wherein the first semiconductor die is a logic die and the second semiconductor die is a memory die. In some embodiments, the semiconductor package further includes a first dielectric bonding layer and a second dielectric bonding layer located between the first package component and the first base. In some embodiments, the first base further includes a second pin, a third pin, and a fourth pin protruding from the bottom of the first recess, wherein the first pin, the second pin, the third pin, and the fourth pin are the same size in a top view, and the first pin, the second pin, the third pin, and the fourth pin are arranged in a staggered array in a top view. In some embodiments, the first base further includes a second pin, a third pin, and a fourth pin protruding from the bottom of the first recess, wherein the first pin and the second pin are larger than the third pin and the fourth pin in a top view. In some embodiments, the first pin is spaced apart from the second pin by a first pitch, and the third pin is spaced apart from the fourth pin by a second pitch, wherein the first pitch is larger than the second pitch.

[0113] In some embodiments, a semiconductor package includes a substrate, a first package component, and a first cooling system. The first package component is bonded to the substrate, the first package component including two or more semiconductor dies stacked vertically. The first cooling system is positioned over the first package component, the first cooling system including a first base and a cover. The first base is bonded to the first package component, wherein the first base includes a first recess, a first pin protruding from a bottom of the first recess, a second recess, a second pin protruding from a bottom of the second recess, and a first raised portion between the first recess and the second recess. The cover is attached to the first base. In some embodiments, top surfaces of the first pin and the second pin of the first base are exposed, and a top surface of the first raised portion of the first base is in contact with a sealant on a bottom surface of the cover. In some embodiments, the first base includes a semiconductor material. In some embodiments, the semiconductor package further includes an underfill between the first package component and the substrate, wherein the underfill surrounds the first package component in a top view. In some embodiments, the cover includes a coolant distribution network. In some embodiments, the cover includes a first coolant inlet and a first coolant outlet facing the first recess of the first base, and the cover further includes a second coolant inlet and a second coolant outlet facing the second recess of the first base.

[0114] In some embodiments, a method of manufacturing a semiconductor package. The method includes bonding a material layer to a package component layer. The method includes removing a portion of the material layer to form a base layer, wherein the base layer includes a first recess, a plurality of first pins protruding from a bottom of the first recess, and a first raised portion surrounding the first recess in a top view. The method includes singulating the base layer and the package component layer to form a first base and a first package component, wherein the first base remains bonded to the first package component, and wherein the first base includes the first recess, the plurality of first pins, and the first raised portion. The method includes bonding the first package component to a substrate. The method also includes attaching a cover to the first raised portion of the first base with a sealant, wherein the cover includes a plurality of first openings facing the first base. In some embodiments, the material layer includes a semiconductor material. In some embodiments, top surfaces of the plurality of first pins of the first base are spaced apart from the cover. In some embodiments, the first package component includes a stack of a plurality of memory dies on a logic die. In some embodiments, bonding the material layer to the package component layer further includes bonding a first bonding layer on the material layer to a second bonding layer on the package component layer with a through-die bonding. In some embodiments, the method further includes singulating the base layer and the package component layer to form a second base and a second package component, wherein the second base remains bonded to the second package component, and wherein the second base includes a second recess, a plurality of second pins protruding from a bottom of the second recess, and a second raised portion surrounding the second recess in a top view. The method further includes bonding the second package component to the substrate next to the first package component. The method further includes attaching the cover to the second raised portion of the second base with the sealant, wherein the cover includes a plurality of second openings facing the second base.

[0115] The above summarizes the features of many embodiments, so that those skilled in the art to which the present application belongs can more easily understand the embodiments of the present application. Those skilled in the art to which the present application belongs should understand that other processes and structures can be easily designed or changed based on the embodiments of the present application to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art to which the present application belongs should also understand that these equivalent structures do not deviate from the concept and scope of the present application. Various changes, substitutions and variations can be made to the embodiments of the present application without departing from the concept and scope of the appended claims.

Claims

1. A semiconductor package, characterized by, Comprising: a substrate; a first package component bonded to the substrate, the first package component comprising a first semiconductor die; and a first cooling system located over the first package component, the first cooling system comprising: a first pedestal located over the first package component, wherein the first pedestal comprises a first recess, a first pin protruding from a bottom of the first recess, and a first raised portion that surrounds the first recess in a top view; a lid located over the first pedestal, wherein the lid is spaced apart from the first pin; and a sealant connecting the lid to the first raised portion of the first pedestal.

2. The semiconductor package of claim 1, wherein, The first package component further comprises a second semiconductor die stacked on the first semiconductor die, wherein the first semiconductor die is a logic die and the second semiconductor die is a memory die.

3. The semiconductor package of claim 1, wherein, Further comprising a first dielectric bonding layer and a second dielectric bonding layer located between the first package component and the first pedestal.

4. The semiconductor package of claim 1, wherein, The first pedestal further comprises a second pin, a third pin, and a fourth pin protruding from the bottom of the first recess, wherein the first pin, the second pin, the third pin, and the fourth pin are the same size in the top view, and the first pin, the second pin, the third pin, and the fourth pin are arranged in a staggered array in the top view.

5. The semiconductor package of claim 1, wherein, The first pedestal further comprises a second pin, a third pin, and a fourth pin protruding from the bottom of the first recess, wherein the first pin and the second pin are larger than the third pin and the fourth pin in the top view.

6. The semiconductor package of claim 5, wherein, The first pin and the second pin are spaced apart by a first pitch, and the third pin and the fourth pin are spaced apart by a second pitch, wherein the first pitch is greater than the second pitch.

7. A semiconductor package, characterized by, Comprising: a substrate; a first package component bonded to the substrate, the first package component comprising two or more semiconductor dies stacked vertically; and a first cooling system located over the first package component, the first cooling system comprising: a first pedestal bonded to the first package component, wherein the first pedestal comprises a first recess, a first pin protruding from a bottom of the first recess, a second recess, a second pin protruding from a bottom of the second recess, and a first raised portion located between the first recess and the second recess; and a lid attached to the first pedestal.

8. The semiconductor package of claim 7, wherein the semiconductor package is a flip chip semiconductor package. Top surfaces of the first pin and the second pin of the first pedestal are exposed, and a top surface of the first raised portion of the first pedestal is in contact with a sealant on a bottom surface of the lid.

9. The semiconductor package of claim 7, wherein the semiconductor package is a flip chip semiconductor package. The lid comprises a coolant distribution network.

10. The semiconductor package of claim 7, wherein the semiconductor package is a flip chip semiconductor package. The lid comprises a first coolant inlet and a first coolant outlet facing the first recess of the first pedestal, and the lid further comprises a second coolant inlet and a second coolant outlet facing the second recess of the first pedestal.

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