Control system of inverter

Abstract

The utility model discloses a control system of an inverter. The system comprises a system controller and a plurality of redundant level selection circuits. The system controller is used for obtaining a voltage phase vector sequence, and the voltage phase vector sequence is composed of a plurality of vector levels; the redundant level selection circuit is used for receiving the voltage phase vector sequence corresponding to the redundant level selection circuit, and determining whether various redundant level states exist in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence; and when the phase voltage output circuit has multiple redundant level states within the vector action time, the current output state of each parallel bridge arm in the phase voltage output circuit is controlled, so that the output state of the phase voltage output circuit is a target state in the multiple redundant level states. According to the technical scheme of the utility model, the efficiency of selecting the redundant level state of the interleaved multi-level inverter can be improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to inverter control technical field especially is related to a control system of inverter. BACKGROUND

[0002] With the gradual maturity of the interleaved parallel multi-level inverter, the interleaved parallel multi-level inverter is more and more applied to the power system, and each phase of the interleaved parallel multi-level inverter is formed by a plurality of parallel bridge arms in parallel, and the output ends of the parallel bridge arms are combined into a total output end through a plurality of filter inductors as the total output of the phase of the inverter. Among them, each parallel bridge arm in the interleaved parallel multi-level inverter is in a two-level working state, that is, outputting "1" level when the upper bridge arm of the parallel bridge arm is turned on, and outputting "0" level when the lower bridge arm of the parallel bridge arm is turned on.

[0003] Currently, the selection optimization of the redundant level state is a problem that needs to be solved and a difficult problem in the space vector control technology of the interleaved parallel three-level and multi-level. For example, the three-level inverter has 19 effective voltage vectors, and the circuit topology of the interleaved parallel three-level inverter adopts two-level output because of the six parallel bridge arms, and can be in 64 output states, while the three-level inverter circuit can only have 19 effective voltage vectors, and the inverter can output an effective voltage vector through multiple output states. Here, the multiple output states are redundant level states.

[0004] Therefore, when the inverter can output an effective voltage vector through multiple redundant level states, a specific target state needs to be selected from the multiple redundant level states to make the inverter output the voltage vector through the target state. Currently, the existing redundant level state selection method is through the space vector pulse width modulation (SVPWM) control technology. The SVPWM control technology first determines the voltage target vector corresponding to the voltage to be output by the inverter, and calculates the voltage phase vector sequence corresponding to each phase voltage output circuit in the inverter based on the voltage target vector, and selects the redundant level state of the inverter based on each voltage phase vector sequence.

[0005] However, the traditional SVPWM control technology is mainly applicable to the neutral point clamped (NPC) inverter, and the traditional SVPWM control technology cannot be directly adapted to the interleaved parallel multi-level inverter, and needs to be combined with the carrier interleaving parallel technology to realize it. With the increase of the number of interleaved parallel branches, the selection of the redundant level state will be very complex, therefore, the efficiency of the existing interleaved parallel multi-level inverter for selecting the redundant level state is low. UTILITY MODEL CONTENTS

[0006] Therefore, the utility model provides a control system of inverter, main purpose lies in solving the technical problem of low efficiency when redundancy level state selection of staggered parallel multilevel inverter.

[0007] To achieve the above object, the utility model provides a control system of inverter first, be applied to the staggered parallel multilevel inverter with multiple phase voltage output circuit, each phase voltage output circuit is used to output a phase voltage, the system includes system controller and multiple redundancy level selection circuit, redundancy level selection circuit with phase voltage output circuit one to one corresponds;

[0008] System controller is used to obtain the voltage phase vector sequence corresponding to each phase voltage output circuit, wherein the voltage phase vector sequence is composed of multiple sequentially arranged vector levels;

[0009] Redundancy level selection circuit is used to receive the voltage phase vector sequence corresponding to redundancy level selection circuit from system controller, and based on the level type of vector level in voltage phase vector sequence, determine whether the output state of phase voltage output circuit in the vector action time corresponding to vector level exists multiple redundancy level states;

[0010] Redundancy level selection circuit is also used to control the current output state of each parallel bridge arm in phase voltage output circuit when multiple redundancy level states exist in phase voltage output circuit in vector action time, so that the output state of phase voltage output circuit is in the target state in multiple redundancy level states.

[0011] In an embodiment of the utility model, the redundancy level selection circuit includes switching quantity circuit and a plurality of bridge arm control circuits, wherein each bridge arm control circuit is used for controlling the current output state of one parallel bridge arm, the switching quantity circuit is used for receiving the voltage phase vector sequence, and based on the level type of the vector level in the voltage phase vector sequence, it is determined that the output state of phase voltage output circuit in the vector action time corresponding to the vector level whether there are multiple redundancy level states, when the phase voltage output circuit has multiple redundancy level states in the vector action time, the switching quantity circuit is also used for receiving the bridge arm current output by each parallel bridge arm in the phase voltage output circuit, and based on the bridge arm current, the overcurrent parallel bridge arm and the undercurrent parallel bridge arm are determined in all parallel bridge arms, the switching quantity circuit is also used for sending low level output signal to the bridge arm control circuit corresponding to the overcurrent parallel bridge arm, so that the bridge arm control circuit sends low level signal to the base of the switch tube in the upper bridge arm of the overcurrent parallel bridge arm, and sends high level signal to the base of the switch tube in the lower bridge arm of the overcurrent parallel bridge arm, the switching quantity circuit is also used for sending high level output signal to the bridge arm control circuit corresponding to the undercurrent parallel bridge arm, so that the bridge arm control circuit sends high level signal to the base of the switch tube in the upper bridge arm of the undercurrent parallel bridge arm, and sends low level signal to the base of the switch tube in the lower bridge arm of the undercurrent parallel bridge arm.

[0012] In an embodiment of the utility model, each level type corresponds to a preset level identifier, the switching quantity circuit includes current comparison circuit and redundancy determination circuit, the redundancy determination circuit is used for receiving the voltage phase vector sequence, and based on the level identifier of the level type of the vector level in the voltage phase vector sequence, it is determined that the output state of phase voltage output circuit in the vector action time corresponding to the vector level whether there are multiple redundancy level states, the current comparison circuit is used for receiving the bridge arm current output by each parallel bridge arm in the phase voltage output circuit, and based on the bridge arm current, the indication signal for indicating the overcurrent parallel bridge arm in the parallel bridge arm is generated, when the phase voltage output circuit has multiple redundancy level states in the vector action time, the redundancy determination circuit is also used for receiving the indication signal, and based on the indication signal, the overcurrent parallel bridge arm and the undercurrent parallel bridge arm are determined in all parallel bridge arms, and low level output signal is sent to the controlled end of the bridge arm control circuit corresponding to the overcurrent parallel bridge arm, and high level output signal is sent to the controlled end of the bridge arm control circuit corresponding to the undercurrent parallel bridge arm.

[0013] In one embodiment of the utility model, multiple parallel bridge arms in phase voltage output circuit include first parallel bridge arm and second parallel bridge arm, the level mark includes first mark signal and second mark signal, the first parallel bridge arm corresponding bridge arm control circuit is first bridge arm control circuit, the second parallel bridge arm corresponding bridge arm control circuit is second bridge arm control circuit, the first bridge arm control circuit includes first diode, second diode, first resistance, second resistance, first circuit non gate, second circuit non gate and third circuit non gate, the input end of third circuit non gate is as the controlled end of first bridge arm control circuit, the anode end of first diode and the first end of first resistance parallel after the connection of end and the output end of third circuit non gate are connected, the cathode end of first diode and the second end of first resistance parallel after the connection of end and the input end of first circuit non gate are connected, the output end of first circuit non gate and the base of switch tube in the upper bridge arm of first parallel bridge arm are connected, the anode end of second diode and the first end of second resistance parallel after the connection of end and the input end of third circuit non gate are connected, the cathode end of second diode and the second end of second resistance parallel after the connection of end and the input end of second circuit non gate are connected, the output end of second circuit non gate and the base of switch tube in the lower bridge arm of first parallel bridge arm are connected.

[0014] In one embodiment of the utility model, the second bridge arm control circuit includes third diode, fourth diode, third resistance, fourth resistance, fourth circuit non gate, fifth circuit non gate and sixth circuit non gate, the input end of sixth circuit non gate is as the controlled end of second bridge arm control circuit, the anode end of third diode and the first end of third resistance parallel after the connection of end and the output end of sixth circuit non gate are connected, the cathode end of third diode and the second end of third resistance parallel after the connection of end and the input end of fourth circuit non gate are connected, the output end of fourth circuit non gate and the base of switch tube in the upper bridge arm of second parallel bridge arm are connected, the anode end of fourth diode and the first end of fourth resistance parallel after the connection of end and the input end of sixth circuit non gate are connected, the cathode end of fourth diode and the second end of fourth resistance parallel after the connection of end and the input end of fifth circuit non gate are connected, the output end of fifth circuit non gate and the base of switch tube in the lower bridge arm of second parallel bridge arm are connected.

[0015] In one embodiment of the utility model, the first bridge arm control circuit further includes first capacitor and second capacitor, the first end of first capacitor is connected with the input end of first circuit non gate, the second end of first capacitor is grounded, the first end of second capacitor is connected with the input end of second circuit non gate, the second end of second capacitor is grounded, the second bridge arm control circuit further includes third capacitor and fourth capacitor, the first end of third capacitor is connected with the input end of fourth circuit non gate, the second end of third capacitor is grounded, the first end of fourth capacitor is connected with the input end of fifth circuit non gate, the second end of fourth capacitor is grounded.

[0016] In one embodiment of the utility model, the current comparison circuit includes first voltage comparator, fifth resistance, sixth resistance, seventh resistance, eighth resistance and first D flip-flop, the first end of fifth resistance is connected with the output end of first parallel bridge arm, for receiving the first bridge arm current that first parallel bridge arm outputs, the two ends of fifth resistance are connected with the noninverting input end of first voltage comparator, the first end of sixth resistance is connected with the output end of second parallel bridge arm, for receiving the second bridge arm current that second parallel bridge arm outputs, the two ends of sixth resistance are connected with the noninverting input end of first voltage comparator, the power input end of first voltage comparator is connected with external power supply, and the ground terminal of first voltage comparator is grounded, the power input end of first voltage comparator is also connected with the first end of eighth resistance, the second end of eighth resistance is connected to the output end of first voltage comparator and the first end of seventh resistance respectively, and the second end of seventh resistance is connected with the second end of sixth resistance, the clock input end of first D flip-flop is used to receive preset frequency trigger pulse, the data input end of first D flip-flop is connected with the output end of first voltage comparator, and the output end of first D flip-flop is used to output the indication signal to the redundancy determination circuit.

[0017] In one embodiment of the utility model, the control system of inverter further includes pulse trigger, the pulse output end of pulse trigger is connected with the clock input end of first D flip-flop, for outputing the trigger pulse to the clock input end of first D flip-flop.

[0018] In an embodiment of the utility model, the redundancy determination circuit includes first exclusive OR gate, first tri-state same direction buffer, second tri-state same direction buffer, third tri-state same direction buffer, fourth tri-state same direction buffer, first NOT gate, second NOT gate and third NOT gate, first input of first exclusive OR gate is used for receiving first identification signal corresponding to each vector level in voltage phase vector sequence, second input of first exclusive OR gate is used for receiving second identification signal of each vector level in voltage phase vector sequence, the output of first exclusive OR gate is connected to the control end of first tri-state same direction buffer, the control end of third tri-state same direction buffer, the input of first NOT gate and the input of third NOT gate respectively, the output of first NOT gate is connected with the control end of second tri-state same direction buffer, the output end of third NOT gate is connected with the control end of fourth tri-state same direction buffer, the first input of first exclusive OR gate is connected with the input of first tri-state same direction buffer, and the second input of first exclusive OR gate is connected with the input of third tri-state same direction buffer, the input of second NOT gate and the input of second tri-state same direction buffer are used for receiving the indication signal, the output of second NOT gate is connected with the input of fourth tri-state same direction buffer, and the output of first tri-state same direction buffer and the output of second tri-state same direction buffer are connected with the controlled end of first bridge arm control circuit after parallel connection, and the output of third tri-state same direction buffer and the output of fourth tri-state same direction buffer are connected with the controlled end of second bridge arm control circuit after parallel connection.

[0019] In an embodiment of the utility model, the redundancy determination circuit further includes ninth resistance and tenth resistance, the first end of ninth resistance is connected to external power supply, and the second end of ninth resistance is connected between the output of first tri-state same direction buffer and the output of second tri-state same direction buffer, the first end of tenth resistance is connected to external power supply, and the second end of tenth resistance is connected between the output of third tri-state same direction buffer and the output of fourth tri-state same direction buffer.

[0020] The control system of the inverter provided by the utility model, the system controller can acquire the voltage phase vector sequence corresponding to each phase voltage output circuit in the interleaved parallel multi-level inverter, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels. Further, each redundancy level selection circuit can acquire the voltage phase vector sequence corresponding to the redundancy level selection circuit from the system controller; further, each redundancy level selection circuit can determine whether the output state of the phase voltage output circuit corresponding to the redundancy level selection circuit in the vector action time corresponding to the vector level in the voltage phase vector sequence received by the redundancy level selection circuit has a plurality of redundancy level states, and control the current output state of each parallel bridge arm in the phase voltage output circuit when the phase voltage output circuit has a plurality of redundancy level states in the vector action time, so that the output state of the phase voltage output circuit is in a target state among the plurality of redundancy level states, so as to select the target state among the plurality of redundancy level states according to the principle that the currents output by each parallel bridge arm in the same phase voltage output circuit tend to be the same, so as to realize the selection of the redundancy level state. The technical scheme of the application can significantly improve the efficiency of selecting the redundancy level state of the interleaved parallel multi-level inverter.

[0021] The above description is only a summary of the technical scheme of the utility model, in order to more clearly understand the technical means of the utility model, the specific embodiments of the utility model can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the utility model more obvious and easy to understand, the specific embodiments of the utility model are described below. BRIEF DESCRIPTION OF DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the utility model, and constitute a part of the utility model, the schematic embodiments of the utility model and the description thereof are used to explain the utility model, and do not constitute an improper limitation on the utility model. In the drawings:

[0023] Figure 1 A structure schematic view of a parallel bridge arm provided by the utility model embodiment is shown;

[0024] Figure 2 A structure schematic view of a phase voltage output circuit as an example provided by the utility model embodiment is shown;

[0025] Figure 3 A schematic view of a space voltage vector diagram provided by the utility model embodiment is shown;

[0026] Figure 4 A structure schematic view of a control system of an inverter provided by the utility model embodiment is shown;

[0027] Figure 5The second structural diagram of a control system of an inverter provided by an embodiment of the present utility model is shown;

[0028] Figure 6 The third structural diagram of a control system of an inverter provided by an embodiment of the present utility model is shown. DETAILED DESCRIPTION

[0029] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other.

[0030] To further illustrate the technical means and effects employed by the present invention to achieve its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention is provided in conjunction with the accompanying drawings and preferred embodiments. In the following description, different references to "one embodiment" or "embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.

[0031] Currently, the optimization of the selection of redundant level states is a key issue that needs to be addressed in interleaved parallel three-level and multi-level space vector control technologies. Here, the existing interleaved parallel multi-level inverter has multiple phase voltage output circuits, each of which is used to output one phase voltage. If the interleaved parallel multi-level inverter is a three-phase inverter, the interleaved parallel multi-level inverter includes three phase voltage output circuits, each of which is used to output one phase voltage. Furthermore, according to the number of levels that the interleaved parallel multi-level inverter can output, each phase voltage output circuit includes multiple parallel bridge arms, such as Figure 1 As shown, each parallel bridge arm includes an upper bridge arm and a lower bridge arm, each of which has a switching tube serving as a power switch. The output end of the parallel bridge arm is connected to an inductor, through which the filtered voltage and bridge arm current are output to the outside. Here, if the interleaved parallel multilevel inverter is a three-level inverter, then each phase voltage output circuit in the interleaved parallel multilevel inverter includes two parallel bridge arms. If the interleaved parallel multilevel inverter is a four-level inverter, then each phase voltage output circuit in the interleaved parallel multilevel inverter includes three parallel bridge arms. Furthermore, the output end of each parallel bridge arm is respectively connected to the first end of an inductor. The output end of each parallel bridge arm corresponds to an inductor, and the second end of each inductor is combined into an output end, forming the total output of the phase, which outputs current to the motor or grid side.

[0032] In the embodiment of the present application, an inverter with interleaved parallel multi-level inverter as three-phase output inverter is taken as an example for illustration (three phases include U phase, V phase and W phase), the inverter includes three phase voltage output circuits, each of which is formed by n parallel bridge arms in parallel, the output ends of the n parallel bridge arms are combined into a total output end through n inductors, as the total output of the phase of the inverter. Other phase number of interleaved parallel multi-level inverter is also applicable to the embodiment.

[0033] Further, each parallel bridge arm in the interleaved parallel multi-level inverter is in a two-level working state, i.e. outputting "1" level (the switch in the upper bridge arm of the parallel bridge arm is turned on, so that the upper bridge arm is turned on) or "0" level (the switch in the lower bridge arm of the parallel bridge arm is turned on, so that the lower bridge arm is turned on). Further, when the switch in the upper bridge arm of the parallel bridge arm is turned on, the bridge arm current output by the parallel bridge arm increases, and when the switch in the lower bridge arm of the parallel bridge arm is turned on, the bridge arm current output by the parallel bridge arm decreases. The switches in the upper bridge arm and the lower bridge arm cannot be turned on at the same time.

[0034] Further, the total output of the three phases of the interleaved parallel multi-level inverter can synthesize output of multiple levels, i.e. "1" level, "0" level and (n-1) intermediate levels, i.e. (n-1) / n, (n-2) / n, …, 1 / n, wherein "1" level is high level and "0" is low level. Here, when the upper bridge arms of all parallel bridge arms of the phase voltage output circuit are turned on, the phase voltage output circuit outputs "1" level, and when the lower bridge arms of all parallel bridge arms of the phase voltage output circuit are turned on, the phase voltage output circuit outputs "0" level. The output state of the phase voltage output circuit is that a specific parallel bridge arm in the phase voltage output circuit outputs "1" level and other parallel bridge arms output "0" level.

[0035] Further, the generation of n-1 intermediate levels of the phase voltage output circuit is combined by the partial parallel bridge arm circuit outputting "1" level and the partial parallel bridge arm circuit outputting "0" level for the phase voltage output circuit. For example, the phase voltage output circuit has n parallel bridge arms, and the (n-5) / n level is combined by (n-5) parallel bridge arms outputting "1" level and 5 parallel bridge arms outputting "0" level. Further, when the phase voltage output circuit outputs an intermediate level, the phase voltage output circuit can be in multiple output states to output the intermediate level, and the number of output states in which the phase voltage output circuit can be when outputting the intermediate level is the number of redundant levels when the phase voltage output circuit outputs the intermediate level. Therefore, the above-mentioned (n-1) intermediate levels will become an important optimization element of the interleaved parallel multi-level inverter control, and how to design the selection control circuit in the space vector control is more complex than the traditional multi-level inverter.

[0036] Further, taking the three-level interleaved parallel multi-level inverter as an example, as shown in Figure 2 the phase voltage output circuit of the three-level interleaved parallel multi-level inverter includes two parallel bridge arms, wherein the first parallel bridge arm is composed of the first switch tube T1 in the upper bridge arm and the second switch tube T2 in the lower bridge arm, and further, the output end of the parallel bridge arm can be led out between the emitter of the switch tube in the upper bridge arm and the collector of the switch tube in the lower bridge arm of the parallel bridge arm, and the output end can output the bridge arm current. Further, the output end of the first parallel bridge arm is connected with the first end of the first inductor L1; further, the second parallel bridge arm is composed of the third switch tube T3 in the upper bridge arm and the fourth switch tube T4 in the lower bridge arm, and the output end of the second parallel bridge arm is connected with the first end of the second inductor L2; further, the second end of the first inductor L1 is connected with the second end of the second inductor L2, and the total output of the phase voltage output circuit is constructed for outputting a phase voltage.

[0037] Further, when the first switch tube T1 and the third switch tube T3 are turned on, and other switch tubes are turned off, the level state of the phase voltage output circuit output is high level, and the high level state is U here; when the first switch tube T1 and the fourth switch tube T4 are turned on, and other switch tubes are turned off, the level state of the phase voltage output circuit output is intermediate level, and the intermediate level state is U / 2 here; when the second switch tube T2 and the third switch tube T3 are turned on, and other switch tubes are turned off, the level state of the phase voltage output circuit output is also intermediate level, and the intermediate level state is U / 2 here; when the second switch tube T2 and the fourth switch tube T4 are turned on, and other switch tubes are turned off, the level state of the phase voltage output circuit output is low level, and the low level state is "0" here. The interleaved parallel multi-level inverter can realize three-level output, and in addition, the interleaved parallel inverter can generate more level outputs by only increasing the parallel bridge arm in the phase voltage output circuit.

[0038] Here, when the level state of the phase voltage output circuit output is intermediate level, the phase voltage output circuit output state includes output state 1 and output state 2, wherein the output state 1 is that the first switch tube T1 and the fourth switch tube T4 are turned on, and other switch tubes are turned off, and the output state 2 is that the second switch tube T2 and the third switch tube T3 are turned on, and other switch tubes are turned off. It can be seen that the phase voltage output circuit outputs the intermediate level, and the output state can be in the output state 1 or the output state 2, and here, the output state 1 and the output state 2 are the redundant level states of the phase voltage output circuit. When the phase voltage output circuit outputs the intermediate level, a target state needs to be selected from the redundant level states, and this process is the selection process of the redundant level state.

[0039] Further, taking the interleaved parallel three-level inverter as an example. The existing interleaved parallel three-level inverter has low efficiency in redundant level state selection, and it is necessary to use the mature control mode of the NPC three-level inverter to optimize the efficiency of the redundant level state selection of the interleaved parallel three-level inverter.

[0040] Here, the NPC three-level inverter is also called a neutral point clamped (NPC) inverter, which is a relatively mature multi-level topology structure, and there is also a redundant level state selection problem, but because there are only 27 combinations of level states in the NPC three-level inverter, the number of redundant level states is much smaller than that of the interleaved parallel three-level inverter. At present, the control mode of the NPC three-level inverter is very mature, and the commonly selected mode is the space vector pulse width modulation (SVPWM) control technology, but the traditional SVPWM control technology for the NPC three-level inverter cannot be directly adapted to the interleaved parallel three-level inverter because of the different number of redundant level states.

[0041] However, through reasonable control strategy optimization, the mature control strategy of the NPC three-level inverter can be used in combination with the selection principle of the redundant level states of the interleaved parallel inverter to form a selection method and circuit of the redundant level states of the interleaved parallel three-level inverter.

[0042] Further, Figure 3 The space voltage vector diagram of the NPC three-level inverter is given, in which 19 effective voltage vectors are indicated by 19 arrows, and these vector arrows form several triangular sectors.

[0043] Further, because the NPC three-level inverter has 27 output combinations of level states, which are called NPC vertex vectors, they are assigned to Figure 3 19 voltage vectors.

[0044] Further, taking the vertex vector opn pointing upwards as an example, it contains the meaning that the U-phase output of the three-level inverter is the middle level o, the V-phase output is the high level p, and the W-phase output is the low level n. Further, the three output level vectors are called vertex sub-vectors corresponding to the U, V, and W phases of the vertex vector.

[0045] Further, according to the above control strategy, the triangular sector in which the voltage target vector is located in the space voltage vector diagram of the NPC three-level inverter can be determined, and the NPC vertex vector of the triangular sector can be determined, and each NPC vertex sub-vector output by the phase voltage output circuit can be determined, and the action time of the NPC vertex vector and the vertex sub-vector can be calculated. Further, the vector levels corresponding to each NPC vertex sub-vector of the phase voltage output circuit are arranged to obtain the voltage phase vector sequence corresponding to the phase voltage output circuit.

[0046] Further, according to the voltage phase vector sequence, there is a NPC vertex sub-vector of the intermediate level "o", that is, there are multiple redundant level state vector action time vectors. Because the circuit topology of the interleaved parallel three-level inverter has 6 half-bridge circuits and adopts two-level output, a total of 64 output level states can be generated, however, only 19 effective voltage vectors can be obtained for the three-level inverter circuit, and the corresponding redundant level state of each effective voltage vector is more than that of the NPC three-level inverter. Specifically, the intermediate level "o" of the NPC three-level inverter can correspond to 2 redundant levels of the interleaved parallel inverter.

[0047] Further, Figure 3 In the space voltage vector diagram of the NPC three-level inverter shown, the vertices of each triangle are assigned 27 NPC vertex vectors. If each NPC vertex vector contains an intermediate level "o", it can correspond to 2 redundant levels of the interleaved parallel three-level inverter. According to this relationship principle, Table 1 lists the corresponding number of redundant levels of the two types of three-level inverters.

[0048]

[0049] Table 1

[0050] On the basis of the principle of the above-mentioned prior art, the following describes the control system of the inverter according to some embodiments of the present application. Figures 1 to 6 The control system of the inverter according to some embodiments of the present application is described.

[0051] As Figure 1 As shown in the control system of the inverter according to an embodiment of the present application, the control system is applied to an interleaved parallel multi-level inverter (not shown in the figure) with multiple phase voltage output circuits, each phase voltage output circuit (not shown in the figure) is used to output a phase voltage; further, the control system of the inverter includes a system controller 110 and multiple redundant level selection circuits 120, the redundant level selection circuits 120 correspond one-to-one to the phase voltage output circuits, and each redundant level selection circuit 120 is used to control the current output state of each parallel bridge arm in a phase voltage output circuit.

[0052] Further, the system controller 110 is used to obtain the voltage phase vector sequence corresponding to each phase voltage output circuit, wherein the voltage phase vector sequence is composed of multiple sequentially arranged vector levels; here, the system controller 110 can be connected with a host computer, and relevant personnel can send the voltage phase vector sequence of each phase voltage output circuit in the interleaved parallel multi-level inverter to the system controller 110 based on the host computer.

[0053] Further, the redundancy level selection circuit 120 is configured to receive the voltage phase vector sequence corresponding to the redundancy level selection circuit 120 from the system controller 110, and determine whether there are multiple redundancy level states of the output state of the phase voltage output circuit in the vector action time corresponding to the vector level of the voltage phase vector sequence based on the level type of the vector level in the voltage phase vector sequence. Specifically, each redundancy level selection circuit 120 is connected with the system controller 110, and the system controller 110 can send the voltage phase vector sequence corresponding to the phase voltage output circuit to the redundancy level selection circuit 120 corresponding to the phase voltage output circuit.

[0054] Further, after receiving the voltage phase vector sequence, the redundancy level selection circuit 120 determines whether the level type of the vector level in the voltage phase vector sequence is the intermediate level, and if the level type of a certain vector level is the intermediate level, it is determined that there are multiple redundancy level states of the output state of the phase voltage output circuit in the vector action time corresponding to the vector level of the intermediate level; on the contrary, if the level type of a certain vector level is not the intermediate level, it is determined that there are no multiple redundancy level states of the output state of the phase voltage output circuit in the vector action time corresponding to the vector level of the intermediate level.

[0055] Further, the redundancy level selection circuit 120 is further configured to control the current output state of each parallel bridge arm in the phase voltage output circuit when there are multiple redundancy level states of the output state of the phase voltage output circuit in the vector action time, so that the output state of the phase voltage output circuit is in a target state in the multiple redundancy level states.

[0056] In the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit is reduced in the vector action time. Specifically, the strategy of selecting the redundancy level state is to select the redundancy level state according to the principle that the currents output by the parallel bridge arms of the same phase tend to be the same. In the vector action time of the complementary half-bridge output state, the output current of the originally larger parallel bridge arm is reduced, and the output current of the originally smaller parallel bridge arm is increased, so that the difference between the output currents of each parallel bridge arm in the phase voltage output circuit is reduced in the vector action time, and then the redundancy level state in which the currents output by the parallel bridge arms tend to be the same is selected as the target state. Further, for each phase voltage output circuit, when there are multiple redundancy level states in the vector action time of a vector level in the voltage phase vector sequence, the target state can be selected from the multiple redundancy level states by the above-mentioned method.

[0057] The application provides a control system of an inverter. A system controller can obtain a voltage phase vector sequence corresponding to each phase voltage output circuit in the interleaved parallel multi-level inverter, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels. Further, each redundancy level selection circuit can obtain the voltage phase vector sequence corresponding to the redundancy level selection circuit from the system controller. Further, each redundancy level selection circuit can determine whether the output state of the phase voltage output circuit corresponding to the redundancy level selection circuit has multiple redundancy level states in the vector action time corresponding to the vector level according to the level type of the vector level in the voltage phase vector sequence received by the redundancy level selection circuit. When the phase voltage output circuit has multiple redundancy level states in the vector action time, the redundancy level selection circuit controls the current output state of each parallel bridge arm in the phase voltage output circuit so that the output state of the phase voltage output circuit is in a target state among the multiple redundancy level states, so as to select the target state among the multiple redundancy level states according to the principle that the currents output by each parallel bridge arm in the same phase voltage output circuit tend to be the same, thereby realizing the selection of the redundancy level state. The technical scheme of the application can significantly improve the efficiency of selecting the redundancy level state of the interleaved parallel multi-level inverter.

[0058] In an optional embodiment, as shown in Figure 5 The redundancy level selection circuit 120 includes a switching circuit 121 and a plurality of bridge arm control circuits 122. Each bridge arm control circuit 122 is configured to control the current output state of a parallel bridge arm (not shown in the figure).

[0059] Specifically, the switching circuit 121 is configured to receive the voltage phase vector sequence and determine whether the output state of the phase voltage output circuit has multiple redundancy level states in the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence. Here, the switching circuit 121 can determine whether the level type of the vector level in the voltage phase vector sequence is an intermediate level after receiving the voltage phase vector sequence. If the level type of a certain vector level is an intermediate level, it is determined that the output state of the phase voltage output circuit has multiple redundancy level states in the vector action time corresponding to the intermediate vector level.

[0060] Further, when there are multiple redundant level states of the phase voltage output circuit in the vector acting time, the switching circuit 121 is further configured to receive bridge arm currents output by each parallel bridge arm in the phase voltage output circuit, and determine an overcurrent parallel bridge arm and an undercurrent parallel bridge arm among all the parallel bridge arms based on the bridge arm currents. The switching circuit 121 can be connected to the output end of each parallel bridge arm in the phase voltage output circuit to obtain the bridge arm current of each parallel bridge arm. Here, the switching circuit 121 can determine the parallel bridge arm outputting a larger bridge arm current as the overcurrent parallel bridge arm, and determine the parallel bridge arm outputting a smaller bridge arm current as the undercurrent parallel bridge arm.

[0061] Further, the switching circuit 121 is further configured to send a low-level output signal to the bridge arm control circuit 122 corresponding to the overcurrent parallel bridge arm, so that the bridge arm control circuit 122 sends a low-level signal to the gate of the switch tube in the upper bridge arm of the overcurrent parallel bridge arm, and sends a high-level signal to the gate of the switch tube in the lower bridge arm of the overcurrent parallel bridge arm.

[0062] Further, the switching circuit 121 is further configured to send a high-level output signal to the bridge arm control circuit 122 corresponding to the undercurrent parallel bridge arm, so that the bridge arm control circuit 122 sends a high-level signal to the gate of the switch tube in the upper bridge arm of the undercurrent parallel bridge arm, and sends a low-level signal to the gate of the switch tube in the lower bridge arm of the undercurrent parallel bridge arm.

[0063] The embodiments provided in the present application can quickly determine the overcurrent parallel bridge arm and the undercurrent parallel bridge arm among the parallel bridge arms of the phase voltage output circuit through the bridge arm currents of the parallel bridge arms, thereby improving the selection efficiency of the redundant level state of the inverter.

[0064] In an optional embodiment, in the voltage phase vector sequence, each vector level has a preset level type corresponding to a level identifier, so as to distinguish the level types of the vector levels. At present, in a three-level inverter, the level types include two identification signals, i.e., a first identification signal and a second identification signal. The first identification signal and the second identification signal of the intermediate level are “0” and “1” or “1” and “0”, respectively. The first identification signal and the second identification signal of the high level are “1” and “1”, respectively. The first identification signal and the second identification signal of the low level are “0” and “0”, respectively. Further, if the voltage phase vector sequence includes multiple vector levels, the switching circuit can receive the first identification signal and the second identification signal of each vector level in the voltage phase vector sequence, and determine whether the vector level is an intermediate level based on the first identification signal and the second identification signal of the vector level.

[0065] Further, the switch quantity circuit comprises a current comparison circuit and a redundancy determination circuit; the redundancy determination circuit is configured to receive the voltage phase vector sequence, and determine whether the output state of the phase voltage output circuit in the vector action time corresponding to the vector level exists multiple redundancy level states based on the level type of the vector level.

[0066] Specifically, the redundancy determination circuit can receive the voltage phase vector sequence from the system controller, analyze the level identification of each vector level in the voltage phase vector sequence one by one, and determine whether the first identification signal and the second identification signal of a certain vector level are "0", "1" or "1", "0", respectively. When the first identification signal and the second identification signal of a certain vector level are "0", "1" or "1", "0", respectively, it is determined that the output state of the phase voltage output circuit in the vector action time exists multiple redundancy level states.

[0067] Further, the current comparison circuit is configured to receive the bridge arm currents output by each parallel bridge arm in the phase voltage output circuit, and generate an indication signal for indicating the overcurrent parallel bridge arm in the parallel bridge arms based on the bridge arm currents. Specifically, the current comparison circuit can determine the larger bridge arm current from the two bridge arm currents, and regard the parallel bridge arm outputting the larger bridge arm current as the overcurrent parallel bridge arm.

[0068] Further, when the phase voltage output circuit exists multiple redundancy level states in the vector action time, the redundancy determination circuit is further configured to receive the indication signal, determine the overcurrent parallel bridge arm and the undercurrent parallel bridge arm in all the parallel bridge arms based on the indication signal, send a low-level output signal to the controlled end of the bridge arm control circuit corresponding to the overcurrent parallel bridge arm, and send a high-level output signal to the controlled end of the bridge arm control circuit corresponding to the undercurrent parallel bridge arm.

[0069] The embodiments provided in the present application can determine whether the phase voltage output circuit exists multiple redundancy level states in the vector action time of the vector level of the voltage phase vector sequence based on the level type of each vector level in the voltage phase vector sequence, and improve the selection efficiency of the redundancy level state of the inverter.

[0070] In an optional embodiment, each phase voltage output circuit in the interleaved parallel multi-level inverter is as follows Figure 2As shown, each phase voltage output circuit contains two parallel bridge arms, including a first parallel bridge arm and a second parallel bridge arm, the first parallel bridge arm is composed of a first switch tube T1 and a second switch tube T2, and the second parallel bridge arm is composed of a third switch tube T3 and a fourth switch tube T4. Here, the bridge arm control circuit corresponding to the first parallel bridge arm is the first bridge arm control circuit, and the bridge arm control circuit corresponding to the second parallel bridge arm is the second bridge arm control circuit. Further, the first bridge arm control circuit is used to control the parallel bridge arm in which the first switch tube T1 and the second switch tube T2 are located, and the parallel bridge arm in which the first switch tube T1 and the second switch tube T2 are located outputs a first bridge arm current I1; at the same time, the second bridge arm control circuit is used to control the parallel bridge arm in which the third switch tube T3 and the fourth switch tube T4 are located, and the parallel bridge arm in which the third switch tube T3 and the fourth switch tube T4 are located outputs a second bridge arm current I2. Figure 2 Figure 2

[0071] Further, as shown in Figure 6 , the first bridge arm control circuit includes a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a first circuit NOT gate U11, a second circuit NOT gate U12, and a third circuit NOT gate U15, and the first circuit NOT gate U11, the second circuit NOT gate U12, and the third circuit NOT gate U15 can be NOT gates.

[0072] Specifically, the input end of the third circuit NOT gate U15 serves as the controlled end of the first bridge arm control circuit and is connected with the redundancy judgment circuit.

[0073] Further, the anode end of the first diode D1 and the first end of the first resistor R1 are connected in parallel, and the connection end after the parallel connection is connected with the output end of the third circuit NOT gate U15; the cathode end of the first diode D1 and the second end of the first resistor R1 are connected in parallel, and the connection end after the parallel connection is connected with the input end of the first circuit NOT gate U11; and the output end of the first circuit NOT gate U11 is connected with the base of the switch tube in the upper bridge arm of the first parallel bridge arm.

[0074] Further, the anode end of the second diode D2 and the first end of the second resistor R2 are connected in parallel, and the connection end after the parallel connection is connected with the input end of the third circuit NOT gate U15; the cathode end of the second diode D2 and the second end of the second resistor R2 are connected in parallel, and the connection end after the parallel connection is connected with the input end of the second circuit NOT gate U12; and the output end of the second circuit NOT gate U12 is connected with the base of the switch tube in the lower bridge arm of the first parallel bridge arm.

[0075] In the actual working process, when the controlled end of the first bridge arm control circuit receives a high level from the first control end of the redundancy judgment circuit, the parallel bridge arm in which the first switch tube T1 and the second switch tube T2 are located is controlled Figure 2 ​​The first switch tube T1 in the first bridge arm control circuit is turned on, and the second switch tube T2 is controlled to be turned off. When the first bridge arm control circuit receives a low level from the first control end of the redundancy determination circuit, the first switch tube T1 is controlled to be turned off, and the second switch tube T2 is controlled to be turned on. The embodiments provided in the application can send a high level signal or a low level signal to the controlled end of the first bridge arm control circuit to control the current output state of the first parallel bridge arm, thereby improving the selection efficiency of the redundancy level state of the inverter.

[0076] Further, as shown in Figure 6 The second bridge arm control circuit includes a third diode D3, a fourth diode D4, a third resistor R3, a fourth resistor R4, a fourth circuit NOT gate U13, a fifth circuit NOT gate U14, and a sixth circuit NOT gate U16. The fourth circuit NOT gate U13, the fifth circuit NOT gate U14, and the sixth circuit NOT gate U16 can be NOT gates.

[0077] Here, the input end of the sixth circuit NOT gate U16 is connected to the redundancy determination circuit as the controlled end of the second bridge arm control circuit.

[0078] Specifically, the anode end of the third diode D3 is connected to the output end of the sixth circuit NOT gate U16 in parallel with the first end of the third resistor R3, the cathode end of the third diode D3 is connected to the input end of the fourth circuit NOT gate U13 in parallel with the second end of the third resistor R3, and the output end of the fourth circuit NOT gate U13 is connected to the base of the switch tube in the upper bridge arm of the second parallel bridge arm.

[0079] Further, the anode end of the fourth diode D4 and the first end of the fourth resistor R4 are connected to the input end of the sixth circuit NOT gate U16 in parallel, the cathode end of the fourth diode D4 and the second end of the fourth resistor R4 are connected to the input end of the fifth circuit NOT gate U14 in parallel, and the output end of the fifth circuit NOT gate U14 is connected to the base of the switch tube in the lower bridge arm of the second parallel bridge arm.

[0080] In actual working process, when the second bridge arm control circuit receives a high level from the second control end of the redundancy determination circuit, the third switch tube T3 is turned on and the fourth switch tube T4 is controlled to be turned off. When the second bridge arm control circuit receives a low level from the second control end of the redundancy determination circuit, the third switch tube T3 is controlled to be turned off, and the fourth switch tube T4 is controlled to be turned on. The embodiments provided in the application can send a high level signal or a low level signal to the controlled end of the second bridge arm control circuit to control the current output state of the first parallel bridge arm, thereby improving the selection efficiency of the redundancy level state of the inverter.

[0081] In an optional embodiment, asFigure 6 As shown, the first bridge arm control circuit further comprises a first capacitor C1 and a second capacitor C2; specifically, a first end of the first capacitor C1 is connected with an input end of the first circuit NOT gate U11, a second end of the first capacitor C1 is grounded, a first end of the second capacitor C2 is connected with an input end of the second circuit NOT gate U12, and a second end of the second capacitor C2 is grounded.

[0082] Further, the second bridge arm control circuit further comprises a third capacitor C3 and a fourth capacitor C4; specifically, a first end of the third capacitor C3 is connected with an input end of the fourth circuit NOT gate U13, a second end of the third capacitor C3 is grounded, a first end of the fourth capacitor C4 is connected with an input end of the fifth circuit NOT gate U14, and a second end of the fourth capacitor C4 is grounded.

[0083] In the embodiments provided in the present application, the first capacitor and the second capacitor are arranged in the first bridge arm control circuit, and the third capacitor and the fourth capacitor are arranged in the second bridge arm control circuit, so that the electrical signals sent by the first bridge arm control circuit to the first parallel bridge arm and the electrical signals sent by the second bridge arm control circuit to the second parallel bridge arm can be respectively filtered and processed, and the control accuracy of the first parallel bridge arm and the second parallel bridge arm is improved.

[0084] In an optional embodiment, as shown in Figure 6 As shown, the current comparison circuit comprises a first voltage comparator U9, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8 and a first D flip-flop U10.

[0085] Specifically, a first end of the fifth resistor R5 is connected with an output end of the first parallel bridge arm, for receiving a first bridge arm current I1 output by the first parallel bridge arm, two ends of the fifth resistor R5 are connected with an inverting input end of the first voltage comparator U9, a first end of the sixth resistor R6 is connected with an output end of the second parallel bridge arm, for receiving a second bridge arm current I2 output by the second parallel bridge arm, two ends of the sixth resistor R6 are connected with a non-inverting input end of the first voltage comparator U9, a power supply input end of the first voltage comparator U9 is connected with an external power supply VCC, and a ground end of the first voltage comparator U9 is grounded.

[0086] Further, the power input end of the first voltage comparator U9 is also connected with the first end of the eighth resistor R8, the second end of the eighth resistor R8 is connected with the output end of the first voltage comparator U9 and the first end of the seventh resistor R7 respectively, and the second end of the seventh resistor R7 is connected with the second end of the sixth resistor R6; further, the clock input end of the first D flip-flop U10 is used for receiving the trigger pulse CP with a preset frequency, the data input end of the first D flip-flop U10 is connected with the output end of the first voltage comparator U9, and the output end of the first D flip-flop U10 is used for outputting the indication signal to the redundancy judgment circuit.

[0087] Further, the control system of the inverter further comprises a pulse trigger (not shown in the figure); the pulse output end of the pulse trigger is connected with the clock input end of the first D flip-flop U10, and is used for outputting the trigger pulse CP to the clock input end of the first D flip-flop.

[0088] In the actual working process, the first bridge arm current I1 generates a voltage at the fifth resistor R5, the second bridge arm current I2 generates a voltage at the sixth resistor R6, and the first voltage comparator U9 compares the voltage at the fifth resistor R5 and the voltage at the sixth resistor R6 in real time. Here, when the first bridge arm current I1 is greater than the second bridge arm current I2, the output end of the first voltage comparator U9 outputs a low-level signal as an indication signal, which is used for indicating that the first parallel bridge arm is an overcurrent parallel bridge arm and the second parallel bridge arm is an undercurrent parallel bridge arm; on the contrary, when the first bridge arm current I1 is less than the second bridge arm current I2, the output end of the first voltage comparator U9 outputs a high-level signal as an indication signal, which is used for indicating that the second parallel bridge arm is an overcurrent parallel bridge arm and the first parallel bridge arm is an undercurrent parallel bridge arm.

[0089] The trigger pulse CP is a frequency-adjustable PWM wave, which can realize the modulation of the redundant level output when the vector level is the middle level. When the interleaved parallel multi-level inverter outputs the middle level state, in order to improve the current ripple, multiple switching needs to be performed between several different selectable redundant level states, the switching frequency is determined by the trigger pulse CP, and the selection of the redundant level state follows the principle of "comparing the convergence" of the output current values of each parallel bridge arm. Further, the frequency value of the trigger pulse CP needs to balance the working frequency of the switch tube, the size of the inductance, and the indicators of the current ripple requirements. At the same time, the frequency of the trigger pulse CP can be greater than the calculation frequency of the voltage target vector calculated by the system controller, and the time length of the period of the trigger pulse CP is less than the time length of the vector action time, so as to improve the current ripple. Further, the first D flip-flop U10 can collect the output level of the first voltage comparator U9 at each rising edge of the trigger pulse CP, and latch it in the subsequent trigger pulse CP cycle, thereby forming an output pulse to change the output level at the same frequency as the trigger pulse CP, and each time the level is changed from the output of the voltage comparator.

[0090] In the actual working process, the first bridge arm current I1 generates a voltage at the fifth resistor R5, the second bridge arm current I2 generates a voltage at the sixth resistor R6, and the first voltage comparator U9 compares the voltage at the fifth resistor R5 with the voltage at the sixth resistor R6 in real time. Here, when the first bridge arm current I1 is greater than the second bridge arm current I2, the output end of the first voltage comparator U9 outputs a low-level signal as an indication signal, and sends the low-level signal to the first D flip-flop U10. The low-level signal received by the first D flip-flop U10 is a continuous analog signal. In order to convert the continuous analog signal into a digital signal composed of high and low levels, the trigger pulse CP is sent to the clock input end of the first D flip-flop U10. At each rising edge of the trigger pulse CP, the output end of the first D flip-flop U10 outputs the indication signal received from the output end of the first voltage comparator U9 at the last trigger pulse CP cycle. Similarly, when the first bridge arm current I1 is less than the second bridge arm current I2, the output end of the first voltage comparator U9 outputs a high-level signal as an indication signal, and sends the high-level signal to the first D flip-flop U10. The high-level signal received by the first D flip-flop U10 is a continuous analog signal. By sending the trigger pulse CP to the clock input end of the first D flip-flop U10, at each rising edge of the trigger pulse CP, the output end of the first D flip-flop U10 outputs the indication signal received from the output end of the first voltage comparator U9 at the last trigger pulse CP cycle. From then on, the signal output by the output end of the first D flip-flop U10 is the indication signal in the form of a digital signal.

[0091] The embodiment provided in the application can determine the over-current parallel bridge arm and the under-current parallel bridge arm in the first parallel bridge arm and the second parallel bridge arm based on the first bridge arm current and the second bridge arm current, and improve the selection efficiency of the redundant level state of the inverter.

[0092] In an optional embodiment, as shown in Figure 6 The redundancy determination circuit includes a first exclusive OR gate U1, a first tri-state inverter U2, a second tri-state inverter U3, a third tri-state inverter U4, a fourth tri-state inverter U5, a first NOT gate U6, a second NOT gate U7, and a third NOT gate U8.

[0093] Specifically, the first input end of the first exclusive OR gate U1 is configured to receive a first identification signal corresponding to each of the vector levels, and the second input end of the first exclusive OR gate U1 is configured to receive a second identification signal of each of the vector levels.

[0094] Further, the output end of the first exclusive OR gate U1 is connected to the control end of the first tri-state inverter U2, the control end of the third tri-state inverter U4, the input end of the first NOT gate U6, and the input end of the third NOT gate U8, respectively; the output end of the first NOT gate U6 is connected to the control end of the second tri-state inverter U3; and the output end of the third NOT gate U8 is connected to the control end of the fourth tri-state inverter U5.

[0095] Further, the first input end of the first exclusive OR gate U1 is connected to the input end of the first tri-state inverter U2, and the second input end of the first exclusive OR gate U1 is connected to the input end of the third tri-state inverter U4.

[0096] Further, the input end of the second NOT gate U7 and the input end of the second tri-state inverter U3 are connected to the output end of the first D flip-flop U10, configured to receive the indication signal.

[0097] Further, the output end of the second NOT gate U7 is connected to the input end of the fourth tri-state inverter U5, the output end of the first tri-state inverter U2 and the output end of the second tri-state inverter U3 are connected in parallel, and the connected end is connected to the controlled end of the first bridge arm control circuit as the first control end of the redundancy determination circuit; the output end of the third tri-state inverter U4 and the output end of the fourth tri-state inverter U5 are connected in parallel, and the connected end is connected to the controlled end of the second bridge arm control circuit as the second control end of the redundancy determination circuit.

[0098] Further, as shown in Figure 6As shown, the redundancy determination circuit further comprises a ninth resistor R9 and a tenth resistor R10; specifically, a first end of the ninth resistor R9 is connected to an external power supply VCC, a second end of the ninth resistor R9 is connected between an output end of the first tri-state in-phase buffer U2 and an output end of the second tri-state in-phase buffer U3; a first end of the tenth resistor R10 is connected to the external power supply VCC, a second end of the tenth resistor R10 is connected between an output end of the third tri-state in-phase buffer U4 and an output end of the fourth tri-state in-phase buffer U5.

[0099] The working flow of the actual use of the control system of the inverter is described below. Specifically, the first input end and the second input end of the first XOR gate U1 in the redundancy level selection circuit receive identification signals of vector levels in a voltage phase vector sequence. Here, the first input end of the first XOR gate U1 is used to receive a first identification signal of the level identification of each vector level in the voltage phase vector sequence, and the second input end of the first XOR gate U1 is used to receive a second identification signal of the level identification of each vector level in the voltage phase vector sequence. When the system controller sends the voltage phase vector sequence to the redundancy determination circuit in the switching quantity circuit, the first identification signal of each vector level is sequentially input to the first input end of the first XOR gate U1 of the redundancy determination circuit, and the second identification signal of each vector level is input to the second input end of the first XOR gate U1 of the redundancy determination circuit.

[0100] Further, when the level type of the vector level is the intermediate level, the first identification signal and the second identification signal input to the first XOR gate U1 are different, which makes the first XOR gate U1 output a high level. When the level type of the vector level is not the intermediate level, the two level signals input to the first XOR gate U1 make the first XOR gate U1 output a low level.

[0101] Further, when the control end of each of the first tri-state in-phase buffer U2, the second tri-state in-phase buffer U3, the third tri-state in-phase buffer U4, and the fourth tri-state in-phase buffer U5 receives a “0” level, the tri-state in-phase buffer receiving the “0” level is turned on; when the control end of each of the first tri-state in-phase buffer U2, the second tri-state in-phase buffer U3, the third tri-state in-phase buffer U4, and the fourth tri-state in-phase buffer U5 receives a “1” level, the tri-state in-phase buffer receiving the “1” level is turned off and presents a high resistance state output.

[0102] Further, when the first and second input terminals of the first XOR gate U1 receive the same level of the first and second identification signals, the output level of the first XOR gate U1 is "0", at this time, the first and third tri-state in-phase buffers U2 and U4 are opened, and the second and fourth tri-state in-phase buffers U3 and U5 are closed; on the contrary, when the output level of the first XOR gate U1 is "1", the second and fourth tri-state in-phase buffers U3 and U5 are opened, and the first and third tri-state in-phase buffers U2 and U4 are closed.

[0103] Specifically, when the output level of the first XOR gate U1 is "0", the output signals of the redundancy judgment circuit to the controlled terminals of the first and second bridge arm control circuits are determined by the levels of the signals received by the first and second input terminals of the first XOR gate U1, the level of the signal output by the redundancy judgment circuit to the controlled terminal of the first bridge arm control circuit is the same as the level of the signal received by the first input terminal of the first XOR gate U1, and the level of the signal output by the redundancy judgment circuit to the controlled terminal of the second bridge arm control circuit is opposite to the level of the signal received by the second input terminal of the first XOR gate U1.

[0104] On the contrary, when the output level of the first XOR gate U1 is "1", the output signals of the redundancy judgment circuit to the controlled terminals of the first and second bridge arm control circuits are determined by the level of the indication signal, the level of the signal output by the redundancy judgment circuit to the controlled terminal of the first bridge arm control circuit is the same as the level of the indication signal, and the level of the signal output by the redundancy judgment circuit to the controlled terminal of the second bridge arm control circuit is opposite to the level of the indication signal.

[0105] Further, if the first bridge arm current I1 is greater than the second bridge arm current I2, the first voltage comparator U9 outputs "0" level, the indication signal is "0" level, Figure 2 The lower bridge arm of the parallel bridge arm in which the first and second switch tubes T1 and T2 are located is turned on, and the first bridge arm current I1 decreases. At the same time, the upper bridge arm of the parallel bridge arm in which the third and fourth switch tubes T3 and T4 are located is turned on, and the second bridge arm current I2 increases. After the period of the trigger pulse CP, the difference between the first bridge arm current I1 and the second bridge arm current I2 decreases.

[0106] On the contrary, if the first bridge arm current I1 is less than the second bridge arm current I2, the first voltage comparator U9 outputs "1" level, the indication signal is "1" level, Figure 2The upper bridge arm of the parallel bridge arm in which the first switch tube T1 and the second switch tube T2 are located is turned on, and the first bridge arm current I1 increases. Meanwhile, the lower bridge arm of the parallel bridge arm in which the third switch tube T3 and the fourth switch tube T4 are located is turned on, and the second bridge arm current I2 decreases. After the period of the trigger pulse CP, the difference between the first bridge arm current I1 and the second bridge arm current I2 decreases, so that the output state of the phase voltage output circuit is in the target state among the multiple redundant level states.

[0107] Here, the process of selecting the redundant level state of the other phase voltage output circuit of the interleaved parallel multi-level inverter can refer to the process described above, and here, the description is not repeated,

[0108] The embodiments provided in the application can control the current output state of each parallel bridge arm in the phase voltage output circuit when the output state of the phase voltage output circuit corresponding to the redundant level selection circuit exists multiple redundant level states during the vector action time corresponding to the vector level according to the level type of the vector level in the voltage phase vector sequence and the bridge arm current of the two parallel bridge arms, so that the output state of the phase voltage output circuit is in the target state among the multiple redundant level states, so as to select the target state among the multiple redundant level states according to the principle that the currents output by each parallel bridge arm in the same phase voltage output circuit tend to be the same, so as to realize the selection of the redundant level state. The technical scheme of the application can significantly improve the efficiency of selecting the redundant level state of the interleaved parallel multi-level inverter.

[0109] It should be noted that the selection and internal circuit connection mode of the system controller, the bridge arm control circuit, the current comparison circuit and the redundant determination circuit can be determined according to the actual situation, and the embodiments are not limited specifically. In addition, the connection mode of each device can be determined according to the specific selection of the device, and the embodiments are not limited specifically. The circuit function of the control system of the inverter provided in the embodiments is mainly realized through the circuit connection relationship between each circuit module, and does not depend on the program module in a certain circuit module. In addition, each circuit module in the control system of the inverter can be realized through an analog circuit or a digital circuit, and for the system controller which can implant a program module, the realization of the module function can be realized through the program module provided by the prior art.

[0110] The above-described embodiments only express several embodiments of the application, and the description is more specific and detailed, but it cannot be understood as a limitation on the scope of the application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the application, a number of modifications and improvements can be made, which belong to the protection scope of the application. Therefore, the protection scope of the application patent should be subject to the appended claims.

Claims

1. A control system of an inverter applied to a multi-level inverter with a plurality of phase voltage output circuits each for outputting a phase voltage, characterized by, The system comprises a system controller and a plurality of redundancy level selection circuits corresponding to the phase voltage output circuits; The system controller is configured to obtain a voltage phase vector sequence corresponding to each phase voltage output circuit, wherein the voltage phase vector sequence comprises a plurality of sequentially arranged vector levels; The redundancy level selection circuit is configured to receive the voltage phase vector sequence corresponding to the redundancy level selection circuit from the system controller, and determine whether there are multiple redundancy level states of the output state of the phase voltage output circuit within the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence; The redundancy level selection circuit is further configured to control the current output state of each parallel bridge arm in the phase voltage output circuit to make the output state of the phase voltage output circuit in a target state among the multiple redundancy level states when the phase voltage output circuit has multiple redundancy level states within the vector action time.

2. The control system of an inverter according to claim 1, characterized by, The redundancy level selection circuit comprises a switching circuit and a plurality of bridge arm control circuits, wherein each bridge arm control circuit is configured to control the current output state of one parallel bridge arm; The switching circuit is configured to receive the voltage phase vector sequence, and determine whether there are multiple redundancy level states of the output state of the phase voltage output circuit within the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence; When the phase voltage output circuit has multiple redundancy level states within the vector action time, the switching circuit is further configured to receive the bridge arm currents output by each parallel bridge arm in the phase voltage output circuit, and determine the overcurrent parallel bridge arm and the undercurrent parallel bridge arm among all the parallel bridge arms based on the bridge arm currents; The switching circuit is further configured to send a low-level output signal to the bridge arm control circuit corresponding to the overcurrent parallel bridge arm, so as to make the bridge arm control circuit send a low-level signal to the base of the switch tube in the upper bridge arm of the overcurrent parallel bridge arm and send a high-level signal to the base of the switch tube in the lower bridge arm of the overcurrent parallel bridge arm; The switching circuit is further configured to send a high-level output signal to the bridge arm control circuit corresponding to the undercurrent parallel bridge arm, so as to make the bridge arm control circuit send a high-level signal to the base of the switch tube in the upper bridge arm of the undercurrent parallel bridge arm and send a low-level signal to the base of the switch tube in the lower bridge arm of the undercurrent parallel bridge arm.

3. The control system of the inverter according to claim 2, wherein each of the level types corresponds to a preset level identifier. The switching circuit comprises a current comparison circuit and a redundancy determination circuit; The redundancy determination circuit is configured to receive the voltage phase vector sequence, and determine whether there are multiple redundancy level states of the output state of the phase voltage output circuit within the vector action time corresponding to the vector level based on the level identification of the level type of the vector level in the voltage phase vector sequence; The current comparison circuit is configured to receive the bridge arm currents output by each parallel bridge arm in the phase voltage output circuit, and generate an indication signal for indicating the overcurrent parallel bridge arm among the parallel bridge arms based on the bridge arm currents. The redundancy determination circuit is further configured to receive the indication signal when there are multiple redundancy level states of the phase voltage output circuit within the vector acting time, and determine the over-current parallel bridge arm and the under-current parallel bridge arm among all the parallel bridge arms based on the indication signal, and send a low-level output signal to a controlled end of a bridge arm control circuit corresponding to the over-current parallel bridge arm, and send a high-level output signal to a controlled end of a bridge arm control circuit corresponding to the under-current parallel bridge arm.

4. The control system of an inverter according to claim 3, wherein the plurality of the parallel bridge arms in the phase voltage output circuit includes a first parallel bridge arm and a second parallel bridge arm, and the level identifier includes a first identification signal and a second identification signal, characterized in that, The bridge arm control circuit corresponding to the first parallel bridge arm is a first bridge arm control circuit, and the bridge arm control circuit corresponding to the second parallel bridge arm is a second bridge arm control circuit; the first bridge arm control circuit comprises a first diode, a second diode, a first resistor, a second resistor, a first circuit NOT gate, a second circuit NOT gate, and a third circuit NOT gate; an input end of the third circuit NOT gate is a controlled end of the first bridge arm control circuit; a connection end of the anode end of the first diode and the first end of the first resistor in parallel is connected with an output end of the third circuit NOT gate, a connection end of the cathode end of the first diode and the second end of the first resistor in parallel is connected with an input end of the first circuit NOT gate, and an output end of the first circuit NOT gate is connected with a base of a switch tube in an upper bridge arm of the first parallel bridge arm; a connection end of the anode end of the second diode and the first end of the second resistor in parallel is connected with an input end of the third circuit NOT gate, a connection end of the cathode end of the second diode and the second end of the second resistor in parallel is connected with an input end of the second circuit NOT gate, and an output end of the second circuit NOT gate is connected with a base of a switch tube in a lower bridge arm of the first parallel bridge arm.

5. The control system of the inverter according to claim 4, characterized by, The second bridge arm control circuit comprises a third diode, a fourth diode, a third resistor, a fourth resistor, a fourth circuit NOT gate, a fifth circuit NOT gate, and a sixth circuit NOT gate; an input end of the sixth circuit NOT gate is a controlled end of the second bridge arm control circuit; a connection end of the anode end of the third diode and the first end of the third resistor in parallel is connected with an output end of the sixth circuit NOT gate, a connection end of the cathode end of the third diode and the second end of the third resistor in parallel is connected with an input end of the fourth circuit NOT gate, and an output end of the fourth circuit NOT gate is connected with a base of a switch tube in an upper bridge arm of the second parallel bridge arm; a connection end of the anode end of the fourth diode and the first end of the fourth resistor in parallel is connected with an input end of the sixth circuit NOT gate, a connection end of the cathode end of the fourth diode and the second end of the fourth resistor in parallel is connected with an input end of the fifth circuit NOT gate, and an output end of the fifth circuit NOT gate is connected with a base of a switch tube in a lower bridge arm of the second parallel bridge arm.

6. The control system of the inverter according to claim 5, characterized by, The first bridge arm control circuit further comprises a first capacitor and a second capacitor; a first end of the first capacitor is connected with an input end of the first circuit NOT gate, a second end of the first capacitor is grounded, a first end of the second capacitor is connected with an input end of the second circuit NOT gate, and a second end of the second capacitor is grounded. The second bridge arm control circuit further comprises a third capacitor and a fourth capacitor; The first end of the third capacitor is connected with the input end of the fourth non-inverter, the second end of the third capacitor is grounded, the first end of the fourth capacitor is connected with the input end of the fifth non-inverter, and the second end of the fourth capacitor is grounded.

7. The control system of the inverter according to claim 5, characterized by, The current comparison circuit comprises a first voltage comparator, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a first D flip-flop; The first end of the fifth resistor is connected with the output end of the first parallel bridge arm for receiving the first bridge arm current output by the first parallel bridge arm, the two ends of the fifth resistor are connected with the opposite-phase input end of the first voltage comparator, the first end of the sixth resistor is connected with the output end of the second parallel bridge arm for receiving the second bridge arm current output by the second parallel bridge arm, the two ends of the sixth resistor are connected with the same-phase input end of the first voltage comparator, the power input end of the first voltage comparator is connected with an external power supply, and the ground end of the first voltage comparator is grounded; The power input end of the first voltage comparator is further connected with the first end of the eighth resistor, the second end of the eighth resistor is connected with the output end of the first voltage comparator and the first end of the seventh resistor respectively, and the second end of the seventh resistor is connected with the second end of the sixth resistor. The clock input end of the first D flip-flop is used for receiving a trigger pulse with a preset frequency, the data input end of the first D flip-flop is connected with the output end of the first voltage comparator, and the output end of the first D flip-flop is used for outputting the indication signal to the redundancy determination circuit.

8. The control system of the inverter according to claim 7, characterized by, The control system of the inverter further comprises a pulse trigger; The pulse output end of the pulse trigger is connected with the clock input end of the first D flip-flop, and the pulse trigger is used for outputting the trigger pulse to the clock input end of the first D flip-flop.

9. The control system of the inverter according to claim 7, characterized by, The redundancy determination circuit comprises a first exclusive OR gate, a first tri-state same-direction buffer, a second tri-state same-direction buffer, a third tri-state same-direction buffer, a fourth tri-state same-direction buffer, a first non-inverter, a second non-inverter and a third non-inverter. The first input end of the first exclusive OR gate is used for receiving a first identification signal corresponding to each vector level in a voltage phase vector sequence, and the second input end of the first exclusive OR gate is used for receiving a second identification signal of each vector level in the voltage phase vector sequence. The output end of the first exclusive OR gate is connected with the control end of the first tri-state same-direction buffer, the control end of the third tri-state same-direction buffer, the input end of the first non-inverter and the input end of the third non-inverter respectively, the output end of the first non-inverter is connected with the control end of the second tri-state same-direction buffer, and the output end of the third non-inverter is connected with the control end of the fourth tri-state same-direction buffer. The first input end of the first exclusive OR gate is connected with the input end of the first tri-state same-direction buffer, and the second input end of the first exclusive OR gate is connected with the input end of the third tri-state same-direction buffer. The input end of the second non-inverter and the input end of the second tri-state same-direction buffer are used for receiving the indication signal. An output end of the second NOT gate is connected with an input end of the fourth tri-state same-direction buffer, and a connecting end of the output end of the first tri-state same-direction buffer and the output end of the second tri-state same-direction buffer in parallel is connected with a controlled end of the first bridge arm control circuit, and a connecting end of the output end of the third tri-state same-direction buffer and the output end of the fourth tri-state same-direction buffer in parallel is connected with a controlled end of the second bridge arm control circuit.

10. The control system of the inverter according to claim 9, characterized by, The redundancy determination circuit further comprises a ninth resistor and a tenth resistor; A first end of the ninth resistor is connected to an external power supply, and a second end of the ninth resistor is connected between the output end of the first tri-state same-direction buffer and the output end of the second tri-state same-direction buffer; A first end of the tenth resistor is connected to an external power supply, and a second end of the tenth resistor is connected between the output end of the third tri-state same-direction buffer and the output end of the fourth tri-state same-direction buffer.

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