DPU switch

Abstract

The utility model relates to a DPU switch. The DPU switch comprises a plurality of optical modules and a plurality of first cross matrix chips; the first cross matrix chips are electrically connected with the plurality of optical modules, and each first cross matrix chip is electrically connected with other first cross matrix chips; the optical module is used for converting a received optical signal into an electric signal and sending the electric signal to the first cross matrix chip electrically connected with the optical module, and the first cross matrix chip transmits the electric signal to the optical module which is electrically connected with the first cross matrix chip and does not send the electric signal. Or the first cross matrix chip transmits the electric signal to at least one first cross matrix chip electrically connected with the first cross matrix chip. Through the technical scheme disclosed by the invention, the problems of high cost and narrow application range of an analog cross matrix chip of which the number of channels can meet the number of ports in related technologies are solved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of communication technology, and in particular to a DPU switch. BACKGROUND

[0002] Network latency is a core indicator of an ultra-fast trading system, and low latency is a common pursuit of the global financial industry. Latency means economic value, and the pursuit of latency in the current financial industry has gone from milliseconds to microseconds.

[0003] In the related art, the number of channels applied in a low-latency switch can meet the cost of a simulation cross-matrix chip with a number of ports, but the application is not widespread, which limits the use of the switch. CONTENT OF THE UTILITY MODEL

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a DPU switch, which avoids the problem of high cost of a simulation cross-matrix chip with a number of channels that can meet the number of ports and the problem of not being widely applied in the related art.

[0005] In a first aspect, the present disclosure provides a DPU switch, comprising:

[0006] a plurality of optical modules and a plurality of first cross-matrix chips;

[0007] The first cross-matrix chip is electrically connected to a plurality of optical modules, and each first cross-matrix chip is electrically connected to other first cross-matrix chips;

[0008] The optical module is configured to convert a received optical signal into an electrical signal and transmit the electrical signal to the first cross-matrix chip electrically connected thereto, and the first cross-matrix chip transmits the electrical signal to the optical module electrically connected thereto which has not transmitted the electrical signal, or the first cross-matrix chip transmits the electrical signal to at least one first cross-matrix chip electrically connected thereto.

[0009] Optionally, the number of optical modules is M, the number of first cross-matrix chips is N, and one first cross-matrix chip is electrically connected to X optical modules.

[0010] Wherein, M, N and X are positive integers greater than or equal to 1, and X = M / N.

[0011] Optionally, the DPU switch further comprises:

[0012] The FPGA chip and a plurality of second cross-matrix chips are electrically connected with the first cross-matrix chip through the second cross-matrix chips, and part of the optical modules are electrically connected with the first cross-matrix chip through the second cross-matrix chips.

[0013] The second cross-matrix chip receives the electrical signal emitted by the optical module and sends the electrical signal to the first cross-matrix chip, or the second cross-matrix chip receives the electrical signal emitted by the optical module and sends the electrical signal to the FPGA chip, the FPGA chip processes the electrical signal and sends it to the second cross-matrix chip, and the second cross-matrix chip sends it to the first cross-matrix chip.

[0014] Optionally, the second cross-matrix chip includes a second matrix subunit, a first input end of the second matrix subunit is electrically connected with one of the optical modules, a second input end of the second matrix subunit is electrically connected with the FPGA chip, a first output end of the second matrix subunit is electrically connected with the first cross-matrix chip, and a second output end of the second matrix subunit is electrically connected with the FPGA chip.

[0015] Optionally, the FPGA chip includes a first data processing subunit and a second data processing subunit, and the second cross-matrix chip includes a third matrix subunit and a fourth matrix subunit.

[0016] The first input end of the third matrix subunit is electrically connected with the first data processing subunit, the second input end of the third matrix subunit is electrically connected with the second data processing subunit, the output end of the third matrix subunit is electrically connected with the first cross-matrix chip, the first input end of the fourth matrix subunit is electrically connected with the first cross-matrix chip, the first output end of the fourth matrix subunit is electrically connected with the first data processing subunit, and the second output end of the fourth matrix subunit is electrically connected with the second data processing subunit.

[0017] Optionally, the DPU switch further includes:

[0018] An ARM chip, the ARM chip is electrically connected with the FPGA chip, and the FPGA chip sends the processed electrical signal to the ARM chip.

[0019] Optionally, the DPU switch further includes:

[0020] An analog switch and a firmware upgrade chip, the firmware upgrade chip, the FPGA chip and the ARM chip are electrically connected with the analog switch respectively.

[0021] The ARM chip is configured to switch the on channel of the analog switch when the FPGA chip needs to be upgraded, so that the firmware upgrade chip is connected with the FPGA chip.

[0022] Optionally, the DPU switch further comprises:

[0023] a debugging module, the debugging module being connected with the external interface and the FPGA chip respectively, and an external device being electrically connected with the debugging module through the external interface, and the external device upgrading the FPGA chip through the debugging module.

[0024] Optionally, the DPU switch further comprises:

[0025] an optical module control unit, the optical module control unit being electrically connected with the FPGA chip and the optical module respectively;

[0026] The FPGA chip performs state monitoring and information reading and writing on the optical module through the optical module control unit.

[0027] Optionally, the first cross-matrix chip comprises a 16X16 cross-matrix chip MAXP37161B with a bandwidth of 28GBPS.

[0028] The present disclosure provides a DPU switch comprising: a plurality of optical modules and a plurality of first cross-matrix chips; the first cross-matrix chip is electrically connected with the plurality of optical modules, and each first cross-matrix chip is electrically connected with other first cross-matrix chips; the optical module is configured to convert the received optical signal into an electrical signal and send the electrical signal to the first cross-matrix chip electrically connected therewith, and the first cross-matrix chip transmits the electrical signal to the optical module which does not send the electrical signal electrically connected therewith, or the first cross-matrix chip transmits the electrical signal to at least one first cross-matrix chip electrically connected therewith. Thus, the present disclosure sets a plurality of optical modules and a plurality of first cross-matrix chips, the first cross-matrix chip is electrically connected with the plurality of optical modules, and each first cross-matrix chip is electrically connected with other first cross-matrix chips, and the plurality of first cross-matrix chips are used to realize the electrical connection with the plurality of optical modules to realize the matching with the number of ports, which replaces the connection mode in the prior art that only one cross-matrix chip is electrically connected with a plurality of optical modules in the DPU switch, and avoids the problem that the cost of the analog cross-matrix chip in the related art is high and the application is not extensive. BRIEF DESCRIPTION OF DRAWINGS

[0029] The drawings incorporated into the specification and constituting a part of the specification, show embodiments consistent with the present disclosure, and together with the specification, serve to explain the principles of the present disclosure.

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0031] Figure 1 A structural schematic diagram of a DPU switch provided by an embodiment of the present disclosure is shown in the figure.

[0032] Figure 2 A structural schematic diagram of another DPU switch provided by an embodiment of the present disclosure is shown in the figure.

[0033] Figure 3 A connection relationship schematic diagram of a first cross-matrix chip provided by an embodiment of the present disclosure is shown in the figure.

[0034] Figure 4 A connection relationship schematic diagram of another first cross-matrix chip provided by an embodiment of the present disclosure is shown in the figure.

[0035] Figure 5 A connection relationship schematic diagram of another first cross-matrix chip provided by an embodiment of the present disclosure is shown in the figure.

[0036] Figure 6 A connection relationship schematic diagram of another first cross-matrix chip provided by an embodiment of the present disclosure is shown in the figure.

[0037] Figure 7 A partial structural schematic diagram of a DPU switch provided by an embodiment of the present disclosure is shown in the figure.

[0038] Figure 8 A partial structural schematic diagram of a DPU switch provided by an embodiment of the present disclosure is shown in the figure. Figure 7 A partial structural schematic diagram of a DPU switch provided by an embodiment of the present disclosure is shown in the figure.

[0039] Figure 9 A connection relationship schematic diagram of a debugging module provided by an embodiment of the present disclosure is shown in the figure.

[0040] Figure 10 A connection relationship schematic diagram of an optical module control unit and an FPGA chip provided by an embodiment of the present disclosure is shown in the figure.

[0041] Figure 11 A connection relationship schematic diagram of another optical module control unit and an FPGA chip provided by an embodiment of the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0043] Many specific details are set forth in the following description in order to provide a thorough understanding of the present disclosure. However, the present disclosure can be practiced according to other embodiments that are not described in detail herein; obviously, the description is only a part of the embodiments of the present disclosure, not all the embodiments.

[0044] Figure 1 A structural schematic diagram of a DPU switch provided by an embodiment of the present disclosure is shown in FIG. 1. Figure 1 As shown in FIG. 1, the DPU switch includes a plurality of optical modules and a plurality of first cross-matrix chips. The first cross-matrix chips are electrically connected with the plurality of optical modules, and each first cross-matrix chip is electrically connected with other first cross-matrix chips. The optical module is configured to convert a received optical signal into an electrical signal and transmit the electrical signal to the first cross-matrix chip electrically connected therewith. The first cross-matrix chip transmits the electrical signal to an optical module electrically connected therewith and not transmitting the electrical signal, or transmits the electrical signal to at least one first cross-matrix chip electrically connected therewith.

[0045] The DPU switch provided by the embodiment of the present disclosure is a switch dedicated to DPU. DPU (Data Processing Unit) is a new generation of processor for data-centric computing, which can integrate complete data center functions into a single chip. The performance of DPU has been greatly improved compared with the existing CPU. The data processing capability of DPU is stronger, so the embodiment of the present disclosure improves the switch dedicated to DPU.

[0046] Specifically, the optical module is an optoelectronic device that performs photoelectric and electro-optical conversion. The transmitting end of the optical module converts an electrical signal into an optical signal, and the receiving end of the optical module converts an optical signal into an electrical signal. Optical modules are classified according to packaging forms, and common ones include SFP, SFP+, SFF, GBIC (Gigabit Interface Converter), etc.

[0047] The cross-matrix chip (Crossbar Array) is an integrated circuit chip used to build a crossbar switch network. It is based on crossbar switch technology and can realize cross-connection between multiple inputs and multiple outputs. The cross-matrix chip is usually composed of a large number of crossbar switch units, which can route input signals to corresponding output ports as needed. Each crossbar switch unit is usually composed of a switch and related control circuit. The cross-matrix chip has wide applications in electronic communication, computer network and data transmission, etc. It can be used to build high-speed data switching and routing systems to realize fast forwarding and processing of data. The cross-matrix chip has the characteristics of low delay, high bandwidth and flexible connection capability, which can meet the needs of large-scale data transmission and processing.

[0048] The DPU switch provided by the embodiment of the present disclosure includes a plurality of optical modules and a plurality of first cross-matrix chips, Figure 1 Four first cross-matrix chips and 48 optical modules are exemplarily shown in the figure, the 48 optical modules are connected with 48 physical ports, the first cross-matrix chips are electrically connected with the plurality of optical modules, that is, the first first cross-matrix chip (HSW0) is electrically connected with the optical module 0 to the optical module 11, the second first cross-matrix chip (HSW1) is electrically connected with the optical module 12 to the optical module 23, the third first cross-matrix chip (HSW2) is electrically connected with the optical module 24 to the optical module 35, and the fourth first cross-matrix chip (HSW3) is electrically connected with the optical module 36 to the optical module 47. Each first cross-matrix chip is electrically connected with other first cross-matrix chips, that is, the first cross-matrix chip (HSW0) is electrically connected with the second cross-matrix chip (HSW1), the third cross-matrix chip (HSW2) and the fourth cross-matrix chip (HSW3), the second cross-matrix chip (HSW1) is electrically connected with the first cross-matrix chip (HSW0), the third cross-matrix chip (HSW2) and the fourth cross-matrix chip (HSW3), the third cross-matrix chip (HSW2) is electrically connected with the first cross-matrix chip (HSW0), the second cross-matrix chip (HSW1) and the fourth cross-matrix chip (HSW3), and the fourth cross-matrix chip (HSW3) is electrically connected with the first cross-matrix chip (HSW0), the second cross-matrix chip (HSW1) and the third cross-matrix chip (HSW2).

[0049] In some embodiments, referring to Figure 1 The optical module 0 converts the received optical signal into an electrical signal and sends the electrical signal to the first cross-matrix chip (HSW0) electrically connected thereto. According to the signal transmission requirement, the first cross-matrix chip (HSW0) can transmit the electrical signal to one optical module or a plurality of optical modules, for example, to the optical module 1 or to the optical module 1, the optical module 2 and the optical module 3, etc., which are not listed one by one. In addition, the first cross-matrix chip (HSW0) can also transmit the received electrical signal to one first cross-matrix chip electrically connected thereto or to a plurality of first cross-matrix chips electrically connected thereto, for example, the first first cross-matrix chip (HSW0) transmits the received electrical signal to the second first cross-matrix chip (HSW1), or to the second first cross-matrix chip (HSW1), the third first cross-matrix chip (HSW2) and the fourth first cross-matrix chip (HSW3), etc.

[0050] Therefore, the embodiment of the present disclosure sets multiple optical modules and multiple first cross-matrix chips, the first cross-matrix chips are electrically connected with the multiple optical modules, each first cross-matrix chip is electrically connected with other first cross-matrix chips, and the multiple first cross-matrix chips are used to realize the electrical connection with the multiple optical modules to realize the matching with the number of ports, which replaces the connection mode that only one cross-matrix chip is electrically connected with multiple optical modules in the DPU switch in the prior art, and avoids the problem that the cost of the analog cross-matrix chip with the number of channels capable of meeting the number of ports is high and the application is not extensive in the related art.

[0051] Optionally, as shown in Figure 1 , the number of optical modules is M, the number of first cross-matrix chips is N, and one first cross-matrix chip is electrically connected with X optical modules; wherein M, N and X are positive integers greater than or equal to 1, and X=M / N.

[0052] Exemplarily, as shown in Figure 1 , 48 optical modules and 4 first cross-matrix chips can be set, the first cross-matrix chip includes 16 input ports and 16 output ports, that is, each first cross-matrix chip is electrically connected with 12 optical modules. Therefore, the design of the port connection of the first cross-matrix chip is simplified, and the port waste of the first cross-matrix chip is avoided.

[0053] Figure 2 Another structure schematic diagram of a DPU switch provided by the embodiment of the present disclosure is provided, Figure 3 a connection relationship schematic diagram of a first cross-matrix chip provided by the embodiment of the present disclosure is provided, Figure 4 a connection relationship schematic diagram of another first cross-matrix chip provided by the embodiment of the present disclosure is provided, Figure 5 a connection relationship schematic diagram of another first cross-matrix chip provided by the embodiment of the present disclosure is provided, Figure 6 a connection relationship schematic diagram of another first cross-matrix chip provided by the embodiment of the present disclosure is provided, wherein, Figures 3 to 6 the arrow in represents the direction of electrical signal data flow. Optionally, in combination with Figures 2 to 6The DPU switch also includes: an FPGA (Field Programmable Gate Array) chip and multiple second cross-matrix chips. The FPGA chip is electrically connected to the first cross-matrix chip through the second cross-matrix chip, and some optical modules are electrically connected to the first cross-matrix chip through the second cross-matrix chip. The second cross-matrix chip receives the electrical signal emitted by the optical module and sends the electrical signal to the first cross-matrix chip; or the second cross-matrix chip receives the electrical signal emitted by the optical module and sends the electrical signal to the FPGA chip. The FPGA chip processes the electrical signal and sends it to the second cross-matrix chip, and the second cross-matrix chip sends it to the first cross-matrix chip.

[0054] Figure 3 for Figure 2 The data flow of the first cross matrix chip (HSW0) in the Figure 4 for Figure 2 The data flow of the second first cross matrix chip (HSW1) is as follows: Figure 5 for Figure 2 The data flow of the third first cross matrix chip (HSW2) is as follows: Figure 6 for Figure 2 The data flow of the fourth first cross matrix chip (HSW3) in the second cross matrix chip can be, for example, a 2×2 matrix DS280MB810 matrix chip. Each second cross matrix chip includes four 2×2 matrices. The four 2×2 matrices in the first second cross matrix chip are distinguished by DSW0-A, DSW0-B, DSW0-C and DSW0-D in the figure. The other second cross matrix chips can be understood by reference and will not be described one by one. Figures 3 to 6 It can be seen that the embodiment of the present disclosure uses a total of 13 second cross-matrix chips.

[0055] Below is Figure 3 The data flow in Figure 1 is briefly described as follows. Optical module 0 receives the electrical signal from the first cross-connect matrix chip (HSW0) through TX0 and transmits the electrical signal to the first cross-connect matrix chip (HSW0) through RX0. When the electrical signal does not pass through the FPGA chip, the DPU switch can function as a single-layer DPU switch.

[0056] The optical modules 1 to 11 are electrically connected with the first cross-matrix chip through the second cross-matrix chip, and the FPGA chip is electrically connected with the first cross-matrix chip through the second cross-matrix chip. The second cross-matrix chip can send the electrical signals sent by the optical modules to the FPGA chip. The FPGA chip processes the electrical signals and sends them to the second cross-matrix chip, which then sends them to the first cross-matrix chip. The first cross-matrix chip can transmit the electrical signals to the optical modules electrically connected thereto through the TX, or send the electrical signals to at least one first cross-matrix chip electrically connected thereto through the TX. After the data traffic is processed by the FPGA, the DPU switch is used as a 1.5-layer DPU switch.

[0057] Optionally, in combination with Figures 3 to 6 , the second cross-matrix chip comprises a second matrix subunit. A first input end of the second matrix subunit is electrically connected with an optical module, a second input end of the second matrix subunit is electrically connected with the FPGA chip, a first output end of the second matrix subunit is electrically connected with the first cross-matrix chip, and a second output end of the second matrix subunit is electrically connected with the FPGA chip.

[0058] In the following, the 2X2 matrix DS280MB810 DSW0-B part in Figure 3 will be explained as a second matrix subunit. The first input end of the 2X2 matrix DS280MB810 DSW0-B part is electrically connected with the optical module 1, the second input end of the 2X2 matrix DS280MB810 DSW0-B part is electrically connected with the VU13P in the FPGA chip, the first output end of the 2X2 matrix DS280MB810 DSW0-B part is electrically connected with the first cross-matrix chip, and the second output end of the 2X2 matrix DS280MB810 DSW0-B part is electrically connected with the VU13P in the FPGA chip. The optical module 1 converts the received optical signals into electrical signals and transmits the electrical signals to the 2X2 matrix DS280MB810 DSW0-B part. The 2X2 matrix DS280MB810 DSW0-B part selects to transmit the electrical signals sent by the optical module 1 directly to the first cross-matrix chip (HSW0), or to transmit the electrical signals sent by the optical module 1 to the VU13P in the FPGA chip. After the VU13P in the FPGA chip processes the electrical signals, it sends them to the 2X2 matrix DS280MB810 DSW0-B part, which then sends them to the first cross-matrix chip (HSW0).

[0059] The second matrix subunit, for example, also comprises Figure 32x2 matrix DS280MB810 DSW0-B part, 2x2 matrix DS280MB810 DSW2-D part, Figure 4 2x2 matrix DS280MB810 DSW3-B part, 2x2 matrix DS280MB810 DSW3-C part, 2x2 matrix DS280MB810 DSW5-D part, Figure 5 2x2 matrix DS280MB810 DSW6-B part, 2x2 matrix DS280MB810 DSW6-C part, and 2x2 matrix DS280MB810 DSW8-D part, Figure 6 2x2 matrix DS280MB810 DSW9-B part, 2x2 matrix DS280MB810 DSW9-C part, and 2x2 matrix DS280MB810 DSW11-D part. Other similar parts can be understood with reference to the above embodiments and will not be described here one by one.

[0060] Optionally, in combination with Figures 3 to 6 , the FPGA chip comprises a first data processing subunit and a second data processing subunit, and the second cross matrix chip comprises a third matrix subunit and a fourth matrix subunit; the first input end of the third matrix subunit is electrically connected with the first data processing subunit, the second input end of the third matrix subunit is electrically connected with the second data processing subunit, the output end of the third matrix subunit is electrically connected with the first cross matrix chip, the first input end of the fourth matrix subunit is electrically connected with the first cross matrix chip, the first output end of the fourth matrix subunit is electrically connected with the first data processing subunit, and the second output end of the fourth matrix subunit is electrically connected with the second data processing subunit.

[0061] Specifically, in combination with Figures 3 to 6 , the first data processing subunit is, for example, VU13P in the FPGA chip, and the second data processing subunit is, for example, KU5P in the FPGA chip. The VU13P and KU5P in the drawings of the present application can be understood in this way and will not be described here. Figure 3 2x2 matrix DS280MB810 DSW0-A part is the third matrix subunit, and 2x2 matrix DS280MB810 DSW12-A part is the fourth matrix subunit, Figure 4 2x2 matrix DS280MB810 DSW3-A part is the third matrix subunit, and 2x2 matrix DS280MB810 DSW12-B part is the fourth matrix subunit, Figure 5 2x2 matrix DS280MB810 DSW6-A part is the third matrix subunit, and 2x2 matrix DS280MB810 DSW12-C part is the fourth matrix subunit,Figure 6 The 2X2 matrix DS280MB810 DSW9-A part is a third matrix subunit, and the 2X2 matrix DS280MB810 DSW12-D part is a fourth matrix subunit.

[0062] The first data processing subunit and the second data processing subunit may, for example, have different analysis rules for the received electrical signal data, for example, the VU13P performs more complex analysis on the received electrical signal data, and the KU5P performs more complex analysis on the received electrical signal data.

[0063] The following is an example of a DPU switch provided by the embodiment of the present disclosure. Figure 3 The working principles of the first data processing subunit and the second data processing subunit are explained as follows. The first cross matrix chip (HSW0) transmits the electrical signal data that has not been analyzed to the 2X2 matrix DS280MB810 DSW12-A part through TX1, and the 2X2 matrix DS280MB810 DSW12-A part selects and transmits the electrical signal data to the VU13P or the KU5P for electrical signal data analysis. The first input end of the 2X2 matrix DS280MB810 DSW0-A part is electrically connected to the VU13P, the second input end of the 2X2 matrix DS280MB810 DSW0-A part is electrically connected to the KU5P, the 2X2 matrix DS280MB810 DSW0-A part selects the electrical signal data transmitted by the VU13P or the KU5P, and transmits the electrical signal data to the first cross matrix chip (HSW0) through RX1, and transmits the electrical signal data to the outside by the first cross matrix chip (HSW0). Figures 4 to 6 The related signal transmission mode in the above can be understood by reference, and will not be described again here.

[0064] Figure 7 A partial structure schematic diagram of a DPU switch provided by the embodiment of the present disclosure is provided. Optionally, in combination with Figure 2 and Figure 7 The DPU switch further includes an ARM chip, the ARM chip is electrically connected to the FPGA chip, and the FPGA chip transmits the processed electrical signal to the ARM chip.

[0065] Specifically, Figure 7 A partial structure schematic diagram of a DPU switch provided by the embodiment of the present disclosure is provided. The ARM chip is, for example, an X86 core board, the ARM chip transmits signals to the KU5P in the FPGA through PCIE3.0 X 4, and the ARM chip transmits signals to the VU13P in the FPGA through PCIE3.0 X8. The FPGA chip transmits the processed electrical signal to the ARM chip, the ARM chip further processes the electrical signal, and then transmits the electrical signal to the first cross matrix chip, and transmits the electrical signal to the outside by the first cross matrix chip.

[0066] In addition, the debugging serial port To the front panel U conversion serial chip, the COME core board and the RTC-PCF85063 are all electrically connected with the ARM chip through relevant channels, which can be connected in the manner shown in the above embodiment, or in other manners, and the embodiments of the present disclosure do not repeat the same. Figure 7

[0067] Figure 8 For Figure 7 the connection relationship between the FPGA chip and the ARM chip, a partial enlarged schematic view is shown in FIG. 6. Optionally, in combination with Figure 7 and Figure 8 , the DPU switch further includes an analog switch and a firmware upgrade chip, the firmware upgrade chip, the FPGA chip and the ARM chip are electrically connected with the analog switch, and the ARM chip is configured to switch the conduction channel of the analog switch when the FPGA chip needs to be upgraded, so that the firmware upgrade chip is in conduction with the FPGA chip.

[0068] Specifically, in combination with Figure 7 and Figure 8 , the firmware upgrade chip is, for example, Flash 256Mbit and Flash 1Gb in Figure 7 and Figure 8 , the firmware upgrade chip is electrically connected with the FPGA chip through the analog switch, the ARM chip is electrically connected with the analog switch, and is configured to control the switching of the conduction channel of the analog switch. The SPI interface of the external flash of the analog switch can be connected to the configuration SPI interface of the FPGA chip, or can be connected to the SPI channel of the ARM chip. When the FPGA chip is working normally, the ARM chip controls the switching of the conduction channel of the analog switch, and is connected to the configuration SPI interface of the FPGA chip. When the FPGA chip needs to be upgraded, the conduction channel of the analog switch is switched, so that the firmware upgrade chip, for example, Flash 256Mbit or Flash 1Gb, is in conduction with the FPGA chip, and the FPGA chip is upgraded.

[0069] Figure 9 For the connection relationship of the debugging module provided by the embodiments of the present disclosure, a schematic view is shown in FIG. 7. Optionally, as shown in Figure 9 , the DPU switch further includes a debugging module, the debugging module is electrically connected with the external interface and the FPGA chip respectively, and the external device is electrically connected with the debugging module through the external interface, and the external device upgrades the FPGA chip through the debugging module.

[0070] Specifically, as shown in Figure 9 , one end of the debugging module is electrically connected with the external interface, for example, a USB interface, and the other end of the debugging module is electrically connected with the FPGA chip.

[0071] ​Exemplarily, when the FPGA chip system is paralyzed, the user can electrically connect an external device such as a computer with the debugging module through the external interface, and run the program of the FPGA chip manufacturer on the computer to restore the system of the FPGA chip. Thus, the upgrading of the FPGA chip can be realized only through a USB line of a Type C interface, avoiding the problem that in the prior art, the debugging module needs to be placed in the DPU switch, and the front cover of the DPU switch needs to be opened, resulting in complicated debugging. The steps required for upgrading the FPGA chip are simplified.

[0072] The debugging module is, for example, an MCU STM32F103C8T6TR and an FT4232H, and the front panel Mini USB TYPE_B is connected with the MCU and the FT4232H through a USB2.0 HUB 1To 4USB2514 (an industrial-grade USB2.0 hub with 1 USB upstream port and 4 USB downstream ports) as an external interface. The MCU is electrically connected with the CPLD through a JTAG (Joint Test Action Group), and the CPLD is a related chip in the DPU switch. The MCU is used for debugging the CPLD. The FT4232H is used for debugging the COME core board, the ARM chip, the CPU, the KU5P and the VU13P.

[0073] Figure 10 A connection relationship diagram of an optical module control unit and an FPGA chip provided by an embodiment of the present disclosure is shown in Figure 11 A connection relationship diagram of an optical module control unit and an FPGA chip provided by another embodiment of the present disclosure is shown in Figure 7 、 Figure 10 and Figure 11 The DPU switch further includes an optical module control unit, which is electrically connected with the FPGA chip and the optical module respectively; and the FPGA chip performs state monitoring and information reading and writing on the optical module through the optical module control unit.

[0074] Specifically, in combination with Figure 7 、 Figure 10 and Figure 11 The optical module control unit includes, for example, an I2C To GPIO chip and an 8-way expansion TCA9548 chip of I2C. Figure 10 Exemplarily, 48 optical modules are monitored by 24 I2C To GPIO chips in Figure 11 Exemplarily, 48 optical modules are read by 6 I2C To GPIO chips and 8-way expansion TCA9548 chips of I2C, a total of 4 I2C channels are completed, namely I2C0, I2C5, I2C6 and I2C7.

[0075] Referring toFigure 7 The 13 second cross-matrix chips (illustrated as DS280 in the figure) can be set with different I2C addresses, and are controlled and monitored by 4 I2C channels, namely I2C1, I2C2, I2C3 and I2C4. The 4 first cross-matrix chips (illustrated as MAXP37161B in the figure) can be set with different I2C addresses, and are controlled and monitored by 1 I2C channel, namely I2C8. Figure 7 Figure 7 In addition, The encryption chip, voltage detection AD, temperature measurement chip, FRAM and EEPROM are also illustrated in the figure as being controlled and monitored by the I2C9 channel. The first CRPS power supply, the second CRPS power supply, the MP5023, the 12284C and the fan temperature control ADT7470 are controlled and monitored by the I2C10 channel. The ZL30633 (DPLL) is controlled and monitored by the I2C12 channel, and the CPLD (Complex Programmable Logic Device) is controlled and monitored by the I2C11 channel.

[0076] Figure 7 Therefore, the embodiments of the present disclosure realize the dynamic management and monitoring of the devices of the DPU switch through the perfect interface control.

[0077] Therefore, the embodiments of the present disclosure realize the dynamic management and monitoring of the devices of the DPU switch through the perfect interface control.

[0078] Optionally, the first cross-matrix chip includes a 16X16 cross-matrix chip MAXP37161B with a bandwidth of 28GBPS.

[0079] With the development of computer technology and financial technology, high-frequency trading is increasingly widely used in financial markets, and has gradually become the main profit mode of many trading institutions. In the European and American markets, high-frequency trading accounts for more than 60% of the total trading volume, and in the Asian market, this proportion will also reach more than 20%. With the relaxation of domestic financial regulatory policies, high-frequency trading is developing rapidly in China, and a batch of successful investment institutions have emerged in the market. In the future, high-frequency trading will be further developed with the gradual relaxation of the regulatory environment. High-frequency trading has a very strong requirement for low latency of data, and most of the low latency DPU switches on the market are 10G rate interfaces, which cannot support connection for higher bandwidth 25G rate interfaces.

[0080] ​The existing low latency DPU switch system, the current interface bandwidth is mostly 48 physical ports, each physical port has, for example, 10G rate SFP+ (Small Form-factor Pluggables, small form-factor pluggable optical module) interface, and the low latency DPU switch usually uses a cross matrix of chip M21605, which is a 160X160 12.5Gbps bandwidth analog cross matrix chip. But at present, in order to reduce the latency, it is necessary to use a matrix switch chip supporting higher bandwidth. For 48X48 or more analog cross matrix chips with a bandwidth of 25Gbps or more, due to cost problems, their use is not widespread.

[0081] To solve this problem, the embodiments of the present disclosure use 4 pieces of 28G bandwidth 16X16 cross matrix chip MAXP37161B which is widely used and low cost, to realize a 48-port 25G interface low latency DPU switch, which can be provided for financial futures industry applications, so that the single port bandwidth of the original low latency 48-port DPU switch is increased from 10Gbps to 25Gbps, and the data transmission rate is faster. The application scenario is a low latency 48-port DPU switch in futures and exchanges, and the non-existent is a snap mirror of more than 16 25Gbps rate ports.

[0082] The embodiments of the present disclosure realize the electrical connection with the plurality of optical modules by setting a plurality of optical modules and a plurality of first cross matrix chips, the first cross matrix chips are electrically connected with the plurality of optical modules, each first cross matrix chip is electrically connected with other first cross matrix chips, and the electrical connection with the plurality of optical modules is realized by using the plurality of first cross matrix chips to realize the matching with the number of ports, which replaces the connection mode that only one cross matrix chip in the DPU switch in the prior art is electrically connected with a plurality of optical modules, and avoids the problem that the cost of the cross matrix chip with a channel number capable of meeting the number of ports is high and the application is not widespread in the related art.

[0083] It should be noted that, in this document, relational terms such as "first" and "second", and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0084] The foregoing is merely illustrative of the various implementations of the present disclosure and the general principles thereof. Numerous modifications can be made to these illustrations, and equivalents can be substituted therefor, without departing from the scope of the present disclosure. The specific embodiments commensurate with the specific application are intended to be illustrative only and not limiting of the scope of the application as set forth in the following claims.

Claims

1. A DPU switch, characterized by, Comprise: a plurality of optical modules and a plurality of first cross-matrix chips; each of the first cross-matrix chips is electrically connected with the plurality of optical modules, and each of the first cross-matrix chips is electrically connected with other first cross-matrix chips; the optical module is used for converting the received optical signal into an electrical signal, and transmitting the electrical signal to the first cross-matrix chip electrically connected therewith, and the first cross-matrix chip transmits the electrical signal to the optical module electrically connected therewith which does not transmit the electrical signal, or the first cross-matrix chip transmits the electrical signal to at least one first cross-matrix chip electrically connected therewith.

2. The DPU switch of claim 1, wherein, The number of optical modules is M, the number of first cross-matrix chips is N, and one first cross-matrix chip is electrically connected with X optical modules; wherein M, N and X are positive integers greater than or equal to 1, and X = M / N.

3. The DPU switch of claim 1, wherein, Further comprising: a FPGA chip and a plurality of second cross-matrix chips, the FPGA chip is electrically connected with the first cross-matrix chip through the second cross-matrix chip, and part of the optical modules are electrically connected with the first cross-matrix chip through the second cross-matrix chip; the second cross-matrix chip receives the electrical signal emitted by the optical module, and transmits the electrical signal to the first cross-matrix chip; or the second cross-matrix chip receives the electrical signal emitted by the optical module, and transmits the electrical signal to the FPGA chip, the FPGA chip processes the electrical signal and transmits it to the second cross-matrix chip, and the second cross-matrix chip transmits it to the first cross-matrix chip.

4. The DPU switch of claim 3, wherein, The second cross-matrix chip comprises a second matrix subunit, a first input end of the second matrix subunit is electrically connected with one optical module, a second input end of the second matrix subunit is electrically connected with the FPGA chip, a first output end of the second matrix subunit is electrically connected with the first cross-matrix chip, and a second output end of the second matrix subunit is electrically connected with the FPGA chip.

5. The DPU switch of claim 3, wherein, The FPGA chip comprises a first data processing subunit and a second data processing subunit, and the second cross-matrix chip comprises a third matrix subunit and a fourth matrix subunit; a first input end of the third matrix subunit is electrically connected with the first data processing subunit, a second input end of the third matrix subunit is electrically connected with the second data processing subunit, an output end of the third matrix subunit is electrically connected with the first cross-matrix chip, a first input end of the fourth matrix subunit is electrically connected with the first cross-matrix chip, a first output end of the fourth matrix subunit is electrically connected with the first data processing subunit, and a second output end of the fourth matrix subunit is electrically connected with the second data processing subunit.

6. The DPU switch of claim 3, wherein, Further comprising: an ARM chip, the ARM chip is electrically connected with the FPGA chip, and the FPGA chip transmits the processed electrical signal to the ARM chip.

7. The DPU switch of claim 6, wherein, Further comprising: An analog switch and a firmware upgrade chip, the firmware upgrade chip, the FPGA chip and the ARM chip are electrically connected with the analog switch respectively; The ARM chip is used for switching on the channel of the analog switch when the FPGA chip needs to be upgraded, so that the firmware upgrade chip is connected with the FPGA chip.

8. The DPU switch of claim 3, wherein, Further comprising: A debugging module, the debugging module is electrically connected with the external interface and the FPGA chip respectively, and an external device is electrically connected with the debugging module through the external interface, and the external device upgrades the FPGA chip through the debugging module.

9. The DPU switch of claim 3, wherein, Further comprising: An optical module control unit, the optical module control unit is electrically connected with the FPGA chip and the optical module respectively; The FPGA chip carries out state monitoring and information reading and writing on the optical module through the optical module control unit.

10. The DPU switch of claim 1, wherein, The first cross matrix chip includes a 16X16 cross matrix chip MAXP37161B with a bandwidth of 28GBPS.

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