Planar gate VDMOS with low reverse recovery interference

Abstract

The utility model provides a planar gate VDMOS with low reverse recovery interference. The planar gate VDMOS is characterized in that a plurality of buffer regions are arranged in a silicon carbide substrate; the lower side surface of the drift layer is connected to the upper side surface of the silicon carbide substrate, a variable doping region is arranged in the drift layer, and a lug boss is arranged on the drift layer; the lower side surface of the P-type well region is connected to the upper side surface of the drift layer; the inner side surface of the P-type well region is connected to the outer side surface of the lug boss; a P-type source region and an N-type source region are arranged in the P-type well region, and the P-type source region is connected with the N-type source region; the P-type well region is positioned right above the variably doped region; the lower side surface of the gate dielectric layer is respectively connected with the lug boss and the P-type well region; the gate metal layer is connected to the gate dielectric layer; the drain metal layer is respectively connected with the P-type well region, the P-type source region and the N-type source region; the drain metal layer is connected to the lower side surface of the silicon carbide substrate and each buffer region, and the buffer regions are constructed in the device, so that the rising edge of reverse recovery overshoot of the device can be effectively reduced, and the external interference of the device is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of low reverse recovery interference planar gate VDMOS. BACKGROUND

[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the performance requirements of device are different in different fields, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), lower body diode conduction loss. Due to the fast reverse recovery speed of silicon carbide device, the drain voltage overshoot caused by reverse recovery can easily cause interference to other circuits of the system, affecting the stability of the system. SUMMARY

[0003] The technical problem to be solved by the utility model is to provide a low reverse recovery interference planar gate VDMOS, which has a buffer zone inside the device, which can effectively reduce the rising edge of the reverse recovery overshoot of the device and reduce the external interference of the device.

[0004] In a first aspect, the utility model provides a low reverse recovery interference planar gate VDMOS, comprising:

[0005] A silicon carbide substrate, a plurality of buffer zones are provided in the silicon carbide substrate;

[0006] A drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, a variable doping region is provided in the drift layer, and a protruding portion is provided on the drift layer;

[0007] A P-type well region, the lower side of the P-type well region is connected to the upper side of the drift layer, and the inner side of the P-type well region is connected to the outer side of the protruding portion; a P-type source region and an N-type source region are provided in the P-type well region, the P-type source region is connected to the N-type source region, and the P-type well region is located directly above the variable doping region;

[0008] A gate dielectric layer, the lower side of the gate dielectric layer is connected to the protruding portion and the P-type well region respectively;

[0009] A gate metal layer, the gate metal layer is connected to the gate dielectric layer;

[0010] A drain metal layer, the drain metal layer is connected to the P-type well region, the P-type source region and the N-type source region respectively;

[0011] And a drain metal layer, the drain metal layer is connected to the lower side of the silicon carbide substrate and each buffer zone.

[0012] The utility model discloses a low reverse recovery interference planar gate VDMOS.

[0013] I, the utility model constructs the buffer zone in the silicon carbide substrate of device, and this buffer zone can inhibit the interference introduced by the drain voltage sharp rising edge sharp of parasitic body diode reverse recovery current of device after device switches from conduction to cut-off, reduces the noise of device, improves robustness.

[0014] II, the utility model constructs the variable doped area inside the drift layer, and this area can drain the current of device JFET area to the area below device P type trap area, thereby realizes increasing device conduction area, reduces device on resistance and avoids the effect of heat concentration caused by current concentration in device interior.

[0015] III, the variable doped area and P type trap area are separated by the drift layer, and this area can reduce the influence of variable doped area on device switch structure, thereby realizes only improving device performance without affecting the characteristics of original parameters of device. BRIEF DESCRIPTION OF DRAWINGS

[0016] The utility model will be further explained in connection with the embodiments with reference to the drawings.

[0017] Figure 1 It is the principle diagram of the utility model of a kind of low reverse recovery interference planar gate VDMOS.

[0018] Figure 2 It is the process section of the utility model of a kind of low reverse recovery interference planar gate VDMOS Figure One .

[0019] Figure 3 It is the process section of the utility model of a kind of low reverse recovery interference planar gate VDMOS Figure Two .

[0020] Figure 4 It is the process section of the utility model of a kind of low reverse recovery interference planar gate VDMOS Figure Three .

[0021] Figure 5 It is the process section of the utility model of a kind of low reverse recovery interference planar gate VDMOS Figure Four .

[0022] Figure 6 It is the process section of the utility model of a kind of low reverse recovery interference planar gate VDMOS Figure Five .

[0023] Figure 7 It is the process section of the utility model of a kind of low reverse recovery interference planar gate VDMOS Figure Six .

[0024] Figure 8 The utility model discloses a kind of low reverse recovery interference planar gate VDMOS's process section view Figure Seven

[0025] Figure 9 The utility model discloses a kind of low reverse recovery interference planar gate VDMOS's process section view Figure Eight

[0026] Figure 10 The utility model discloses a kind of low reverse recovery interference planar gate VDMOS's process section view Figure Nine DETAILED DESCRIPTION

[0027] For the convenience of understanding the present application, the present application will be described more fully below with reference to the accompanying drawings. The drawings illustrate embodiments of the present application. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0029] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0030] ​​​Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0031] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0032] As shown in the drawings: Figure 1 The embodiment of the present application provides a low reverse recovery interference planar gate VDMOS, which comprises:

[0033] A silicon carbide substrate 1, wherein a plurality of buffer zones 11 are arranged in the silicon carbide substrate 1;

[0034] A drift layer 2, wherein a lower side of the drift layer 2 is connected to an upper side of the silicon carbide substrate 1, a variable doping zone 21 is arranged in the drift layer 2, and a protruding part 22 is arranged on the drift layer 2;

[0035] A P-type well zone 3, wherein a lower side of the P-type well zone 3 is connected to an upper side of the drift layer 2, and an inner side of the P-type well zone 3 is connected to an outer side of the protruding part 22; a P-type source zone 31 and an N-type source zone 32 are arranged in the P-type well zone 3, the P-type source zone 31 is connected to the N-type source zone 32, and the P-type well zone 3 is located directly above the variable doping zone 21;

[0036] A gate dielectric layer 4, wherein a lower side of the gate dielectric layer 4 is connected to the protruding part 22 and the P-type well zone 3 respectively;

[0037] A gate metal layer 5, wherein the gate metal layer 5 is connected to the gate dielectric layer 4;

[0038] a drain metal layer 6, which is connected to the P-type well region 3, the P-type source region 31 and the N-type source region 32 respectively;

[0039] a drain metal layer 7, which is connected to the lower side of the silicon carbide substrate 1 and each buffer region 11.

[0040] In this embodiment, preferably, the distance between the upper side of the variable doping region 21 and the lower side of the P-type well region 3 is 3-5 μm.

[0041] In this embodiment, preferably, the thickness of the buffer region 11 is 300-500 nm.

[0042] In this embodiment, preferably, the width of the variable doping region 21 is equal to the width of the P-type well region 3.

[0043] As shown in Figures 1 to 10 the preparation method of the VDMOS includes the following steps:

[0044] Step 1, forming a barrier layer 8 above the silicon carbide substrate 1 provided with the drain metal layer 7, etching the barrier layer 8 to form a through hole, and performing ion implantation on the silicon carbide substrate 1 to form a plurality of buffer regions 11;

[0045] Step 2, removing the barrier layer 8 and epitaxially growing a drift layer 2 on the silicon carbide substrate 1;

[0046] Step 3, forming a barrier layer 8 above the drift layer 2, etching the barrier layer 8 to form a through hole, performing ion implantation on the drift layer 2 to form a second N-type doping region 212, removing the original barrier layer 8, re-forming a barrier layer 8, and performing ion implantation on the drift layer 2 to form a first N-type doping region 211, wherein the variable doping region 21 includes the first N-type doping region 211 and the second N-type doping region 212, the concentration of the first N-type doping region 211 is less than that of the second N-type doping region 212, and the inner side of the first N-type doping region 211 is connected to the inner side of the second N-type doping region 212;

[0047] Step 4, removing the original barrier layer 8, re-forming a barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation on the drift layer 2 to form a P-type well region 3;

[0048] Step 5, removing the original barrier layer 8, re-forming a barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation on the P-type well region 3 to form a P-type source region 31;

[0049] Step 6, removing the original barrier layer 8, re-forming a barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation on the P-type well region 3 to form an N-type source region 32;

[0050] Step 7, remove the original barrier layer 8, re-form barrier layer 8, etch barrier layer 8 to form a via, deposit to form gate dielectric layer 4;

[0051] Step 8, remove the original barrier layer 8, re-form barrier layer 8, etch barrier layer 8 to form a via, deposit metal to form gate metal layer 5;

[0052] Step 9, remove the original barrier layer 8, re-form barrier layer 8, etch barrier layer 8 to form a via, deposit metal to form source metal layer 6, remove barrier layer 8, complete preparation.

[0053] In another embodiment of the utility model, silicon carbide substrate 1, drift layer 2 and variable doped region 21 are all N type; buffer region 11 is P type; the doping concentration of silicon carbide substrate 1 is 2-8e18cm -3 ; the doping concentration of buffer region 11 is 1-4e18cm -3 , the doping concentration of drift layer 2 is 1-5e17cm -3 , the doping concentration of first N type doped region 211 is 0.8-1.2e18cm -3 , the doping concentration of second N type doped region 212 is 1.2-2e18cm -3 , the doping concentration of P type well region 3 is 5-8e17cm -3 , gate dielectric layer 4 is silicon dioxide, the doping concentration of N type source region 32 is 2-8e18cm -3 , the doping concentration of P type source region 31 is 1-5e19cm -3 ; the doping concentration of N type silicon carbide substrate 1 is to ensure that low resistance ohmic contact is formed with drain metal layer 7, P type buffer region 11 provides holes when the device is reverse recovery, the doping concentration of N type drift layer 2 is the compromise of device reverse voltage and on-resistance, N type variable doped region 21 is to redistribute the current in the device, reduce the on-resistance of the device, avoid current heat concentration, P type well region 3 is to form the longitudinal voltage structure of the device and the gate control structure of the device, N type source region 32 and P type source region 31 are to form low resistance ohmic contact with source metal layer 6;

[0054] The thickness of the silicon carbide substrate 1 of the device is 1 μm, the thickness of the P-type buffer zone 11 is 300-500 nm, the thickness of the N-type drift layer 2 is 10-30 μm, which is adjusted within the above range according to the requirement of the voltage withstand characteristic of the device, the thickness of the N-type variable-doping zone 21 is 1-3 μm, the distance between the upper side of the N-type variable-doping zone 21 and the lower side of the P-type well zone 3 is 3-5 μm, which is to realize the redistribution of the current on the basis of ensuring that the switching and voltage withstand characteristics of the device are not affected, the thickness of the P-type well zone 3 is 500 nm, which is to ensure the voltage withstand capability and gate control capability of the device, the thickness of the N-type source zone 32 and the P-type source zone 31 is 200 nm, which is a compromise of the ion implantation process control capability and the gate control depth of the device, the thickness of the source metal layer 6 is 200 nm, and the thickness of the gate metal layer 5 is 150 nm;

[0055] The P-type buffer layer 11 constructed in the silicon carbide substrate 1 makes the substrate hole injection process slow down due to the existence of the initial holes in the substrate hole injection process when the device is switched from on to off, thereby reducing the rising edge speed when the device is switched from on to off, and further reducing the high-frequency interference of the device caused by reverse recovery;

[0056] When the electrons of the device flow downward after flowing laterally from the N-type source zone 32 through the P-type well zone 3, the lateral electron flow area of the device increases with the increase of the downward flow depth, and the N-type drift layer 2 cannot be used for electron freewheeling in the region close to the P-type well zone 3 of the device, which leads to the increase of the on-resistance of the device, the current distribution is concentrated, and the N-type variable-doping zone 21 reduces the resistance on the left and right sides of the device, so that the electrons begin to flow laterally close to the P-type well zone 3, thereby reducing the overall on-resistance of the device and avoiding the current concentration of the device.

[0057] The device reduces the peak value of the reverse recovery current of the device by increasing the P-type buffer zone 11 in the N-type silicon carbide substrate 1, reduces the rising edge speed of the reverse recovery voltage overshoot of the device, realizes the reverse recovery interference of the device, and improves the robustness of the device.

[0058] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. A low reverse recovery interference planar gate VDMOS, characterized in that: The application relates to a silicon carbide substrate, which comprises: a silicon carbide substrate, which is internally provided with a plurality of buffer zones; a drift layer, which is connected to the upper side of the silicon carbide substrate, and is internally provided with a variable doping zone, and is externally provided with a convex part; a P-type well zone, which is connected to the upper side of the drift layer, and is internally connected to the outer side of the convex part; the P-type well zone is internally provided with a P-type source zone and an N-type source zone, and the P-type source zone is connected to the N-type source zone; the P-type well zone is located directly above the variable doping zone; a gate dielectric layer, which is connected to the lower side of the convex part and the P-type well zone; a gate metal layer, which is connected to the gate dielectric layer; a drain metal layer, which is connected to the P-type well zone, the P-type source zone and the N-type source zone; and a drain metal layer, which is connected to the lower side of the silicon carbide substrate and each buffer zone.

2. A low reverse recovery planar gate VDMOS as claimed in claim 1, wherein: The variable doping zone comprises a first N-type doping zone and a second N-type doping zone, the concentration of the first N-type doping zone is smaller than that of the second N-type doping zone, and the inner side of the first N-type doping zone is connected to the inner side of the second N-type doping zone.

3. The low reverse recovery planar gate VDMOS of claim 1, wherein: The distance between the upper side of the variable doping zone and the lower side of the P-type well zone is 3-5 mu m.

4. The low reverse recovery planar gate VDMOS of claim 1, wherein: The thickness of the buffer zone is 300-500 nm.

5. The low reverse recovery planar gate VDMOS of claim 1, wherein: The width of the variable doping zone is equal to that of the P-type well zone.

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