Display panel and display device
By setting a shielding layer on the base substrate of the display panel, the overlapping area between the thin film transistor layer and the shielding layer is avoided, especially the overlap between the second pole of the target transistor and the shielding layer, which solves the problems of abnormal display and increased power consumption caused by static electricity, and achieves the stability of the display panel and the reduction of power consumption.
Patent Information
- Application Number
- CN202422655237.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-10-21
- Estimated Expiration
- 2034-10-31
AI Technical Summary
When existing display panels use GOA instead of Gate IC for display scanning drive, static electricity may cause abnormal display problems and increased power consumption.
A shielding layer is provided on the base substrate of the display panel to avoid overlapping areas between the thin film transistor layer and the shielding layer in the GOA, especially overlapping between the second electrode of the target transistor and the shielding layer, thereby reducing the capacitance caused by signal overlap and thus reducing the power consumption of the GOA.
It effectively reduces the power consumption of GOA, improves the abnormal display problem caused by static electricity, and improves the stability of the display panel.
Smart Images
Figure CN223463262U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of display, and particularly relates to a display panel and a display device. BACKGROUND
[0002] At present, GOA (English: Gate On Array, Chinese: Gate on Array substrate) is mostly used to replace Gate IC (English: Gate Integrated Circuit, Chinese: Gate driving chip) to perform display scanning driving, so as to save cost, shorten process time, and realize the effect of narrow frame.
[0003] However, abnormal display problems caused by static electricity may occur in the display panel. If BSM (English: Bottom Shelter Metal, Chinese: Bottom Shield Metal) is used to shield TFT (English: Thin Film Transistor, Chinese: Thin Film Transistor) in GOA, the static electricity problem can be solved, but the power consumption of GOA will increase. UTILITY MODEL CONTENT
[0004] The present application provides a display panel and a display device, aiming to at least solve the problem of GOA power consumption increase to some extent.
[0005] In the first aspect of the present application, a display panel is provided, comprising:
[0006] a substrate substrate having a display area and a non-display area located on one side of the display area;
[0007] a thin film transistor layer located on the substrate substrate, used to form a gate driving circuit in the non-display area; the gate driving circuit comprises a plurality of cascaded shift registers, the shift register comprises a plurality of thin film transistors, at least one thin film transistor in the plurality of thin film transistors is a target transistor; the thin film transistor layer comprises a first source-drain sub-layer, the first source-drain sub-layer is used to form a first electrode of the thin film transistor;
[0008] a shielding layer located between the thin film transistor layer and the substrate substrate; the shielding layer has a first projection area on the substrate substrate, the first source-drain sub-layer has a second projection area on the substrate substrate, and the second electrode of the target transistor has a third projection area on the substrate substrate, and the third projection area is at least partially not overlapped with the first projection area and / or the second projection area.
[0009] In some embodiments, the target transistor comprises a thin film transistor with the largest width-length ratio in the plurality of thin film transistors.
[0010] In some embodiments, the gate driving circuit further comprises a square wave signal line, and the second electrode of the target transistor is connected to the square wave signal line.
[0011] In some embodiments, a projection of the second electrode of the target transistor on the substrate substrate does not overlap, at least in part, with a projection of the shielding layer on the substrate substrate.
[0012] In some embodiments, a projection of the second electrode of the target transistor on the substrate substrate does not intersect with a projection of the shielding layer on the substrate substrate.
[0013] In some embodiments, a projection of the first electrode of the target transistor on the substrate substrate does not overlap, at least in part, with a projection of the shielding layer on the substrate substrate.
[0014] In some embodiments, each of the thin film transistors other than the target transistor is a common transistor, and a projection of the shielding layer on the substrate substrate comprises a projection of the common transistor on the substrate substrate.
[0015] In some embodiments, the first source-drain sub-layer is further used to form an electrode adapter of the target transistor, and the electrode adapter of the target transistor is connected to the active layer of the same target transistor through a communication hole.
[0016] The thin film transistor layer further comprises:
[0017] A second source-drain sub-layer is located on a side of the first source-drain sub-layer away from the substrate substrate, and is used to form a second electrode of the target transistor, and the second electrode of the target transistor is connected to the electrode adapter of the same target transistor through a communication hole.
[0018] In some embodiments, a projection of the electrode adapter of the target transistor on the substrate substrate partially overlaps with a projection of the second electrode of the same target transistor on the substrate substrate.
[0019] In some embodiments, two ends of the second electrode of the target transistor are respectively connected to the electrode adapters of the same target transistor through communication holes, and the electrode adapters connected to the two ends of the second electrode of the target transistor are different.
[0020] In some embodiments, projections of the two ends of the second electrode of the target transistor on the substrate substrate respectively comprise projections of the electrode adapters connected thereto on the substrate substrate.
[0021] In some embodiments, the electrode adapter of the target transistor is connected to the active layer of the same target transistor through two communication holes.
[0022] In some embodiments, the target transistor has two second electrodes, each end of each second electrode of the target transistor is connected to the electrode adapter of the same target transistor through a communication hole.
[0023] In some embodiments, the thin film transistor layer further comprises:
[0024] a semiconductor sub-layer located on the side of the first source-drain sub-layer close to the substrate; the semiconductor sub-layer is used for forming the active layer of the thin film transistor;
[0025] a gate sub-layer located between the semiconductor sub-layer and the first source-drain sub-layer; the gate sub-layer is used for forming the gate of the thin film transistor.
[0026] In some embodiments, the gate driving circuit further comprises a square wave signal line, the first source-drain sub-layer is further used for forming the square wave signal line; the gate sub-layer is further used for forming a signal adapter, the signal adapter is connected to the square wave signal line and the second electrode of the target transistor through communication holes respectively.
[0027] In some embodiments, each thin film transistor of the plurality of thin film transistors except the target transistor is a common transistor; the first source-drain sub-layer is further used for forming the second electrode of the common transistor, the second electrode of the common transistor is connected to the active layer of the same common transistor through a communication hole.
[0028] In the second aspect of the present application, a display device is provided, the display device comprising the display panel provided in the first aspect.
[0029] According to the display panel and the display device provided by one or more embodiments of the present application, the display panel comprises a substrate, a thin film transistor layer and a shielding layer. The substrate has a display area and a non-display area located at one side of the display area. The thin film transistor layer is located on the substrate and is used to form a gate drive circuit in the non-display area. The gate drive circuit comprises a plurality of cascaded shift registers, and each shift register comprises a plurality of thin film transistors. The shielding layer is located between the thin film transistor layer and the substrate, and can shield the TFTs in the GOA, thereby avoiding abnormal display of the display panel caused by static electricity. The thin film transistor layer comprises a first source-drain sub-layer used to form a first electrode of the thin film transistor. The orthographic projection of the first source-drain sub-layer on the substrate is a first projection area, the orthographic projection of the shielding layer on the substrate is a second projection area, and the orthographic projection of the second electrode of the target transistor on the substrate is a third projection area. The third projection area at least partially does not overlap with the first projection area and / or the second projection area, which can reduce the overlapping area of the area where the second electrode of the target transistor transmits signals to the active layer and the orthographic projection of the shielding layer on the substrate, thereby avoiding the increase of the capacitance caused by the overlapping of the signals transmitted by the signal line in the GOA and the signals transmitted by the shielding layer, and further reducing the power consumption of the GOA. Moreover, at least one of the plurality of thin film transistors is the target transistor, which can select the thin film transistor with a larger capacitance increase as the target transistor. On the one hand, this can effectively reduce the power consumption of the GOA, and on the other hand, the shielding layer can also shield most of the thin film transistors, which can also effectively improve the abnormal display problem of the display panel caused by static electricity. BRIEF DESCRIPTION OF DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0031] Figure 1 Part of the layout of the GOA in the related art is shown;
[0032] Figure 2 The structure schematic diagram of the display panel in one or more embodiments of the present application is shown.
[0033] Figure 3 The top view schematic diagram of the substrate of Figure 2 is shown.
[0034] Figure 4 The principle schematic diagram of the shift register of Figure 3 is shown.
[0035] Figure 5 is shown.Figure 4 a circuit distribution diagram of the shift register of
[0036] Figure 6 a partial structure diagram of the display panel of Figure 2
[0037] Figure 7 a distribution diagram of the semiconductor sub-layer of Figure 6
[0038] Figure 8 a distribution diagram of the gate sub-layer of Figure 6
[0039] Figure 9 a distribution diagram of the other gate sub-layer of Figure 6
[0040] Figure 10 a distribution diagram of the first source-drain sub-layer of Figure 6
[0041] Figure 11 a distribution diagram of the shielding layer of Figure 6
[0042] Figure 12 another circuit distribution diagram of the shift register of Figure 4
[0043] Figure 13 a further circuit distribution diagram of the shift register of Figure 4
[0044] Figure 14 a distribution diagram of the first source-drain sub-layer of Figure 13
[0045] Figure 15 a distribution diagram of the second source-drain sub-layer of Figure 13
[0046] Figure 16 a further circuit distribution diagram of the shift register of Figure 4 BRIEF DESCRIPTION OF THE DRAWINGS
[0047] 10': substrate substrate; 21': active layer; 22': gate; 23': first pole; 24': second pole; 30': shielding layer;
[0048]
[0049] 10: substrate substrate; 11: display area; 12: non-display area; 20: thin film transistor layer; 21: first source-drain sub-layer; 22: second source-drain sub-layer; 23: semiconductor sub-layer; 24: gate sub-layer; 30: shielding layer;
[0050] 100: gate drive circuit; 110: shift register; 111: thin film transistor; 112: target transistor; 113: common transistor; 120: square wave signal line. DETAILED DESCRIPTION
[0051] In order to make the person skilled in the art to which the present application belongs more clearly understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor fall within the scope of protection of the present application.
[0052] The display panel using GOA all has the problem of failing in static electricity test. The reason is that static electricity accumulates on the back of the panel to form an electric field after the test, causing the electrical characteristics of the TFT in the GOA to drift, causing the GOA output waveform to be abnormal, and causing abnormal display problems caused by static electricity. The most effective solution to the static electricity problem is to increase the BSM to shield the TFT in the GOA. Figure 1 For the partial layout diagram of the GOA in the related art, please refer to Figure 1 The TFT located on the substrate substrate 10' has an active layer 21', a gate 22', a first pole 23' and a second pole 24'. The gate 22' of the TFT is arranged on the active layer 21' of the TFT, and the first pole 23' and the second pole 24' of the TFT are connected with the active layer 21' of the TFT through the communication hole. The shielding layer 30' is located between the substrate substrate 10' and the TFT. The orthographic projection of the shielding layer 30' on the substrate substrate 10' contains the orthographic projection of each TFT on the substrate substrate 10'. Although this can solve the static electricity problem, it will also cause the power consumption of the GOA to rise.
[0053] In view of the problem of power consumption rise of the GOA in the related art, the inventors analyzed the power consumption of the GOA when the BSM shields different regions of the TFT, as shown in the following Table 1:
[0054] Table 1: Power consumption of GOA when different regions are shielded by BSM
[0055]
[0056] In some embodiments, the GOA can include a Gate GOA and an EM GOA. Illustratively, the Gate GOA can be connected to at least a TFT gate of a data writing sub-circuit in the pixel circuit, and can also be connected to a TFT gate of a compensation sub-circuit in the pixel circuit. The EM GOA can be connected to a TFT gate of a light emitting control sub-circuit in the pixel circuit.
[0057] As can be seen from Table 1, after the BSM shields the Gate GOA, the power consumption of the GOA increases by 16 mW. On this basis, the BSM shields the EM GOA, and the power consumption of the GOA does not increase significantly. Therefore, among the increased power consumption of the GOA, the power consumption increase caused by the BSM shielding the Gate GOA accounts for the majority, and the power consumption increase caused by the BSM shielding the EM GOA is relatively small.
[0058] On the basis of the above, the inventors further analyzed the load conditions of different TFTs in the Gate GOA without BSM shielding, and found that among the capacitances generated by the square wave signal and different TFTs, the capacitance generated by the TFT with the largest aspect ratio accounts for nearly 50%.
[0059] Then, the capacitance change of the TFT after the BSM shielding was analyzed, as shown in Table 2 below:
[0060] Table 2: Capacitance change of different regions of TFT
[0061]
[0062] As can be seen from Table 2, the capacitance change generated by the square wave signal of the Gate GOA increases from 200 pF to 287 pF after the BSM shielding, of which the capacitance generated between the BSM and the active layer is the main part. Therefore, the capacitance between the BSM and the active layer of the TFT with the largest aspect ratio increases the most. The capacitance between the BSM and the active layer of the TFT with the largest aspect ratio accounts for 50% x 67.4% ≈ 35%. The capacitance change generated by the square wave signal of the EM GOA after the BSM shielding is relatively small (22 pF), and the capacitance between the BSM and the active layer accounts for a small proportion.
[0063] Comparing the EM GOA with the Gate GOA, the main difference is that the input signal of the TFT with the largest aspect ratio (aspect ratio of 200 μm to 500 μm) in the Gate GOA is a square wave signal, the square wave signal has a long wire length in the active layer of this TFT, and the capacitance increases greatly after the BSM shielding, so the power consumption increases greatly. The input signal of the TFT with the largest aspect ratio in the EM GOA is a constant voltage signal, the capacitance increases relatively small after the BSM shielding, so the power consumption increases relatively small.
[0064] In summary, the main reason for the increase in GOA power consumption is that the square wave signal of the TFT with the largest width-length ratio in the Gate GOA overlaps with the BSM more.
[0065] Based on the above analysis, the first aspect of the present application provides a display panel. Figure 2 For the structural schematic diagram of the display panel in one or more embodiments of the present application, please refer to Figure 2 The display panel includes a substrate 10, a thin film transistor layer 20, and a shielding layer 30. The thin film transistor layer 20 is located on the substrate 10, and the shielding layer 30 is located between the thin film transistor layer 20 and the substrate 10.
[0066] Figure 3 For Figure 2 the top view schematic diagram of the substrate, please refer to Figure 3 The substrate 10 has a display area 11 and a non-display area 12 located on one side of the display area 11. The thin film transistor layer 20 is used to form a gate drive circuit 100 in the non-display area 12. The gate drive circuit 100 includes a plurality of shift registers 110 connected in cascade.
[0067] Figure 4 For Figure 3 the principle schematic diagram of the shift register, please refer to Figure 4 The shift register 110 includes a plurality of thin film transistors 111, and at least one of the plurality of thin film transistors 111 is a target transistor 112.
[0068] Figure 5 For Figure 4 the circuit distribution schematic diagram of the shift register, please refer to Figure 5 The thin film transistor layer 20 includes a first source-drain sub-layer 21, which is used to form the first pole of the thin film transistor 111. The orthogonal projection of the shielding layer 30 on the substrate 10 is a first projection area, the orthogonal projection of the first source-drain sub-layer 21 on the substrate 10 is a second projection area, and the orthogonal projection of the second pole of the target transistor 112 on the substrate 10 is a third projection area. The third projection area is at least partially not overlapped with the first projection area and / or the second projection area. That is, the third projection area can be at least partially not overlapped with the first projection area, and the second projection area contains the third projection area. Alternatively, the third projection area can be at least partially not overlapped with the second projection area, and the first projection area contains the third projection area. Alternatively, the third projection area can be at least partially not overlapped with the first projection area, and the third projection area can be at least partially not overlapped with the second projection area.
[0069] The display panel includes a substrate 10, a thin film transistor layer 20 and a shielding layer 30. The substrate 10 has a display area 11 and a non-display area 12 located at one side of the display area 11. The thin film transistor layer 20 is located on the substrate 10 and is used to form a gate drive circuit 100 in the non-display area 12. The gate drive circuit 100 includes a plurality of shift registers 110 connected in cascade, and each shift register 110 includes a plurality of thin film transistors 111. The shielding layer 30 is located between the thin film transistor layer 20 and the substrate 10, and can shield the TFTs in the GOA to avoid abnormal display problems of the display panel caused by static electricity. The thin film transistor layer 20 includes a first source-drain sub-layer 21 used to form the first poles of the thin film transistors 111. The shielding layer 30 has a first projection area on the substrate 10, the first source-drain sub-layer 21 has a second projection area on the substrate 10, and the second pole of a target transistor 112 has a third projection area on the substrate 10. The third projection area at least partially does not overlap with the first projection area and / or the second projection area, which can reduce the overlapping area between the area where the second pole of the target transistor 112 transmits signals to the active layer and the projection area of the shielding layer 30 on the substrate 10, thereby avoiding the increased capacitance caused by the overlapping of the signals transmitted by the signal line in the GOA (such as square wave signals) and the signals transmitted by the shielding layer 30 (i.e. BSM), and further reducing the power consumption of the GOA. Moreover, at least one of the plurality of thin film transistors 111 is the target transistor 112 (such as the TFT with the largest width-length ratio), which can select only the thin film transistors 111 with relatively large capacitance increase as the target transistors 112. On the one hand, this can effectively reduce the power consumption of the GOA, and on the other hand, the shielding layer 30 can also shield most of the thin film transistors, which can also effectively improve the abnormal display problems of the display panel caused by static electricity.
[0070] Exemplarily, the gate drive circuit 100 can be a Gate GOA.
[0071] Exemplarily, the thin film transistor 111 has an active layer, a gate, a first pole and a second pole. The gate of the thin film transistor 111 is arranged on the active layer of the same thin film transistor 111, and the first pole and the second pole of the thin film transistor 111 are connected to the active layer of the same thin film transistor 111 through the communication holes respectively. The projection of the gate, the first pole and the second pole of the thin film transistor 111 on the substrate 10 at least partially overlaps with the projection of the active layer of the thin film transistor 111 on the substrate 10.
[0072] Exemplarily, referring to Figure 4 , the shift register 110 can further include at least one capacitor and a plurality of signal lines.
[0073] For example, Figure 4For example, the shift register 110 includes eight thin film transistors 111, two capacitors and four signal lines. The eight thin film transistors 111 are respectively a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8. The two capacitors 120 are respectively a first capacitor C1 and a second capacitor C2. The four signal lines are respectively a first clock signal line CK, a second clock signal line CB, a first power signal line VGH and a second power signal line VGL.
[0074] The gate of the first transistor T1 is connected with the first clock signal line CK, the second electrode of the first transistor T1 is connected with a signal input end STV of the shift register 110, and the first electrode of the first transistor T1 is connected with a first node N1. The gate of the second transistor T2 is connected with the first node N1, the second electrode of the second transistor T2 is connected with the first clock signal line CK, and the first electrode of the second transistor T2 is connected with a second node N2. The gate of the third transistor T3 is connected with the first clock signal line CK, the second electrode of the third transistor T3 is connected with the second power signal line VGL, and the first electrode of the third transistor T3 is connected with the second node N2.
[0075] The gate of the sixth transistor T6 is connected with the second node N2, the second electrode of the sixth transistor T6 is connected with the first power connection line VGH, and the first electrode of the sixth transistor T6 is connected with a third node N3. The gate of the seventh transistor T7 is connected with the second clock signal line CB, the second electrode of the seventh transistor T7 is connected with the first node N1, and the first electrode of the seventh transistor T7 is connected with the third node N3. The gate of the eighth transistor T8 is connected with the second power signal line VGL, the second electrode of the eighth transistor T8 is connected with the first node N1, and the first electrode of the eighth transistor T8 is connected with a fourth node N4.
[0076] The gate of the fourth transistor T4 is connected with the second node N2, the second electrode of the fourth transistor T4 is connected with the first power signal line VGH, and the first electrode of the fourth transistor T4 is connected with a signal output end OUT of the shift register 110. The first end of the first capacitor C1 is connected with the first power signal line VGH, and the second end of the first capacitor C1 is connected with the signal output end OUT of the shift register 110. The gate of the fifth transistor T5 is connected with the fourth node N4, the second electrode of the fifth transistor T5 is connected with the second clock signal end CB, and the first electrode of the fifth transistor T5 is connected with the signal output end OUT of the shift register 110.
[0077] For example, the first node N1, the second node N2, the third node N3 and the fourth node N4 are connection points shared by at least two thin film transistors 111. For example, the first node N1, the second node N2, the third node N3 and the fourth node N4 are connection points shared by the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8. Figure 4For example, the first node N1 is a connection point common to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, the first electrode of the seventh transistor T7, and the first electrode of the eighth transistor T8. The second node N2 is a connection point common to the second electrode of the second transistor T2, the second electrode of the third transistor T3, the gate electrode of the fourth transistor T4, and the gate electrode of the sixth transistor T6. The third node N3 is a connection point common to the second electrode of the sixth transistor T6,
[0078] The thin film transistor 111 can be an N-type TFT or a P-type TFT. When the thin film transistor 111 is a P-type TFT, the first electrode is a drain electrode and the second electrode is a source electrode. When the thin film transistor 111 is an N-type TFT, the first electrode is a source electrode and the second electrode is a drain electrode. The signals transmitted by the first clock signal line CK and the second clock signal line CB can be complementary square wave signals. The signals transmitted by the first power signal line VGH and the second power signal line VGL can be constant voltage signals with different voltages, for example, the signal transmitted by the first power signal line VGH is a high-level signal and the signal transmitted by the second power signal line VGL is a low-level signal.
[0079] In some embodiments, referring to Figure 4 , the target transistor 112 can include a thin film transistor 111 with the largest width-length ratio among the plurality of thin film transistors 111. For example, Figure 4 the fifth transistor T5 is the target transistor 112.
[0080] As described above, the main reason for the increase in the power consumption of the GOA is that the square wave signal of the TFT with the largest width-length ratio in the gate drive circuit overlaps with the BSM more, and the target transistor 112 includes a thin film transistor 111 with the largest width-length ratio among the plurality of thin film transistors 111, that is, a thin film transistor 111 that most affects the power consumption of the GOA is selected as the target transistor 112. The orthographic projection of the shielding layer 30 on the substrate 10 is a first projection area, the orthographic projection of the first source-drain sub-layer 21 on the substrate 10 is a second projection area, and the orthographic projection of the second electrode of the target transistor 112 on the substrate 10 is a third projection area. Since the third projection area at least partially does not overlap with the first projection area and / or the second projection area, the capacitance of the target transistor 112 caused by the overlap of the square wave signal and the signal of the shielding layer 30 is less, and the power consumption of the added BSM rising is lower, thereby effectively reducing the power consumption of the GOA.
[0081] For example, referring to Figure 4 , the gate drive circuit 100 further includes a square wave signal line 120, and the second electrode of the target transistor 112 is connected to the square wave signal line 120. For example, Figure 4 the second clock signal line CB is the square wave signal line 120.
[0082] As previously mentioned, the main reason for the increase in GOA power consumption is that the square wave signal of the TFT with the largest aspect ratio in the gate drive circuit overlaps more with the BSM. The target transistor 112 is the TFT with the largest aspect ratio in the gate drive circuit. The second electrode of the target transistor 112 is connected to the square wave signal line 120, that is, the input signal of the target transistor 112 is a square wave signal. The orthographic projection of the shielding layer 30 on the base substrate 10 is the first projection area, the orthographic projection of the first source and drain sublayer 21 on the base substrate 10 is the second projection area, and the orthographic projection of the second electrode of the target transistor 112 on the base substrate 10 is the third projection area. Because the third projection area at least partially does not overlap with the first projection area and / or the second projection area, the capacitance increased by the overlap of the square wave signal of the target transistor 112 and the signal of the shielding layer 30 can be reduced, effectively reducing the power consumption increased by adding a BSM.
[0083] The following describes in detail the orthographic projection of the second electrode of the target transistor 112 on the base substrate 10, which at least partially does not overlap with the orthographic projection of the shielding layer 30 on the base substrate 10. In this case, the orthographic projection of the first source / drain sublayer 21 on the base substrate 10 may at least partially overlap with the orthographic projection of the second electrode of the target transistor 112 on the base substrate 10, or may not intersect with the orthographic projection of the second electrode of the target transistor 112 on the base substrate 10.
[0084] In order to facilitate identification of the active layer, gate, first electrode and second electrode of each thin film transistor 111, Figure 5 The distribution positions in the thin film transistor layer 20 are briefly introduced first. Figure 6 for Figure 2 For a partial structural diagram of the display panel, please refer to Figure 6 In some embodiments, the thin film transistor layer 20 may further include a semiconductor sublayer 23 and a gate sublayer 24. The semiconductor sublayer 23, the gate sublayer 24, and the first source / drain sublayer 21 are sequentially stacked on the side of the shielding layer 30 away from the base substrate 10. Insulating layers are provided between the shielding layer 30 and the semiconductor sublayer 23, between the semiconductor sublayer 23 and the gate sublayer 24, and between the gate sublayer 24 and the first source / drain sublayer 21. Connecting holes may be provided in the insulating layer to achieve connections between different layers on both sides of the insulating layer.
[0085] Figure 7 for Figure 6 For a schematic diagram of the distribution of semiconductor sublayers, see Figure 7 The semiconductor sublayer 23 is used to form an active layer of the thin film transistor 111. Figure 8 for Figure 6 Schematic diagram of the distribution of a gate sublayer, Figure 9 for Figure 6 For a schematic diagram of the distribution of another gate sublayer, see Figure 8and Figure 9 The thin film transistor layer 20 can include two gate sub-layers 24, one of which is used to form the gate of the thin film transistor 111, and the other of which is used to form two electrodes of a capacitor. Figure 10 For Figure 6 the distribution of the first source-drain sub-layer, please refer to Figure 10 The first source-drain sub-layer 21 can be used to form the first and second poles of the thin film transistor 111, and part of the signal lines (such as the first clock signal line CK and the second clock signal line CB). Figure 11 For Figure 6 the distribution of the shielding layer, please refer to Figure 11 The shielding layer 30 is used to form the BSM and part of the signal lines (such as the second power signal line VGL).
[0086] In some embodiments, please refer to Figure 5 The orthogonal projection of the second pole of the target transistor 112 on the substrate 10 can at least partially not overlap with the orthogonal projection of the shielding layer 30 on the substrate 10. That is, the orthogonal projection of the second pole of the target transistor 112 on the substrate 10 can partially overlap with the orthogonal projection of the shielding layer 30 on the substrate 10, and the other part can not overlap with the orthogonal projection of the shielding layer 30 on the substrate 10, or can not intersect with the orthogonal projection of the shielding layer 30 on the substrate 10. By the orthogonal projection of the second pole of the target transistor 112 on the substrate 10, at least partially not overlapping with the orthogonal projection of the shielding layer 30 on the substrate 10, the orthogonal projection of the second pole of the target transistor 112 on the substrate 10 can be achieved. at least partially not overlapping with the orthogonal projection of the shielding layer 30 on the substrate 10.
[0087] Exemplarily, please refer to Figure 5 The orthogonal projection of the second pole of the target transistor 112 on the substrate 10 can not intersect with the orthogonal projection of the shielding layer 30 on the substrate 10.
[0088] In one possible embodiment, please refer to Figure 5 The orthogonal projection of the shielding layer 30 on the substrate 10 can include the orthogonal projection of the gate and the first pole of the target transistor 112 on the substrate 10.
[0089] Compared with Figure 5 and Figure 1 The capacitance generated by the overlap of the square wave signal and the shielding layer 30 signal is reduced by 93%, and the power consumption of the GOA rise is reduced by 93%.
[0090] Figure 12 For another circuit distribution of the shift register of Figure 4 , please refer to Figure 12In another possible embodiment, the orthogonal projection of the first electrode of the target transistor 112 on the substrate 10 can at least partially not overlap with the orthogonal projection of the shielding layer 30 on the substrate 10. That is, the orthogonal projection of the first electrode of the target transistor 112 on the substrate 10 can partially overlap with the orthogonal projection of the shielding layer 30 on the substrate 10, and partially not overlap with the orthogonal projection of the shielding layer 30 on the substrate 10, or partially not intersect with the orthogonal projection of the shielding layer 30 on the substrate 10.
[0091] For example, referring to Figure 12 , the orthogonal projection of the shielding layer 30 on the substrate 10 can contain the orthogonal projection of the gate of the target transistor 112 on the substrate 10.
[0092] Shielding the gate of the thin film transistor 111 by the shielding layer 30 can affect the number of carriers in the thin film transistor 111, and directly affect the active layer characteristics of the shielding layer 30. Therefore, the effect of shielding the gate of the thin film transistor 111 by the shielding layer 30 is greater than the effect of shielding the source and drain of the thin film transistor 111. In the two possible embodiments, the orthogonal projection of the shielding layer 30 on the substrate 10 contains the orthogonal projection of the gate of the target transistor 112 on the substrate 10, which can effectively control the drift of the electrical characteristics of the thin film transistor 111, and ensure the improvement effect of abnormal display caused by static electricity.
[0093] In some embodiments, referring to Figure 4 , each of the plurality of thin film transistors 111 except the target transistor 112 is a common transistor 113. Referring to Figure 5 , the orthogonal projection of the shielding layer 30 on the substrate 10 can contain the orthogonal projection of the common transistor 113 on the substrate 10. That is, the orthogonal projection of the shielding layer 30 on the substrate 10 contains the orthogonal projection of the active layer, the gate, the first electrode and the second electrode of the common transistor 113 on the substrate 10.
[0094] In the above embodiments, each of the plurality of thin film transistors 111 except the target transistor 112 can be completely shielded by the shielding layer 30, which can effectively improve the static problem of the display panel, while having little effect on the increase of GOA power consumption.
[0095] The orthogonal projection of the second electrode of the target transistor 112 on the substrate 10 at least partially does not overlap with the orthogonal projection of the first source-drain sub-layer 21 on the substrate 10. At this time, the orthogonal projection of the shielding layer 30 on the substrate 10 can at least partially overlap with the orthogonal projection of the second electrode of the target transistor 112 on the substrate 10, or not intersect with the orthogonal projection of the second electrode of the target transistor 112 on the substrate 10.
[0096] Figure 13 Another circuit distribution diagram of the shift register of Figure 4 Figure 14 Another circuit distribution diagram of the first source-drain sub-layer of Figure 13 Figure 15 Another circuit distribution diagram of the second source-drain sub-layer of Figure 13 Figure 13 Figure 14 Figure 15 In some embodiments, the first source-drain sub-layer 21 can also be used to form an electrode adapter of the target transistor 112, and the electrode adapter of the target transistor 112 is connected to the active layer of the same target transistor 112 through a communication hole.
[0097] The thin film transistor layer 20 further comprises a second source-drain sub-layer 22, which is located on the side of the first source-drain sub-layer 21 away from the substrate 10. The second source-drain sub-layer 22 is used to form a second electrode of the target transistor 112, and the second electrode of the target transistor 112 is connected to the electrode adapter of the same target transistor 112 through a communication hole.
[0098] By forming the electrode adapter of the target transistor 112 through the first source-drain sub-layer 21, the second electrode of the target transistor 112 can be transferred from the first source-drain sub-layer 21 to the second source-drain sub-layer 22, and the second electrode of the target transistor 112 located in the second source-drain sub-layer 22 can be connected to the active layer of the same target transistor 112 through the electrode adapter located in the first source-drain sub-layer 21, so that the normal projection of the second electrode of the target transistor 112 on the substrate 10 can be realized, and at least part of the normal projection of the first source-drain sub-layer 21 on the substrate 10 does not overlap.
[0099] In some embodiments, referring to Figure 13 The normal projection of the electrode adapter of the target transistor 112 on the substrate 10 can partially overlap with the normal projection of the second electrode of the same target transistor 112 on the substrate 10, so as to facilitate the connection of the second electrode of the target transistor 112 to the electrode adapter of the same target transistor 112 through a communication hole.
[0100] For example, referring to Figure 13 Both ends of the second electrode of the target transistor 112 can be connected to the electrode adapters of the same target transistor 112 through communication holes, and the electrode adapters connected to both ends of the second electrode of the target transistor 112 are different.
[0101] For example, referring to Figure 13 The normal projection of the second electrode of the target transistor 112 on the substrate 10 at both ends thereof, respectively, comprises the normal projection of the electrode adapter on the substrate 10 connected thereto, facilitating the connection of the second electrode of the target transistor 112 to the electrode adapter of the same target transistor 112 through the communication hole.
[0102] Exemplarily, please refer to Figure 13 The electrode adapter of the target transistor 112 is connected to the active layer of the same target transistor 112 through two communication holes. By reducing the number of communication holes from six to two, the contact area of the first source-drain sub-layer 21 and the semiconductor sub-layer 23 can be reduced, avoiding the overlap between the square wave signal input from the source electrode of the target transistor 112 and the signal of the shielding layer 30, thereby reducing the power consumption of the GOA.
[0103] Exemplarily, please refer to Figure 13 The target transistor 112 has two second electrodes, and each end of each second electrode of the target transistor 112 is connected to the electrode adapter of the same target transistor 112 through the communication hole.
[0104] In some embodiments, please refer to Figure 13 The thin film transistor layer 20 can further comprise a semiconductor sub-layer 23 and a gate sub-layer 24. The semiconductor sub-layer 23 is located on the side of the first source-drain sub-layer 21 close to the substrate 10. The semiconductor sub-layer 23 is used to form the active layer of the thin film transistor 111. The gate sub-layer 24 is located between the semiconductor sub-layer 23 and the first source-drain sub-layer 21. The gate sub-layer 24 is used to form the gate electrode of the thin film transistor 111.
[0105] Exemplarily, please refer to Figure 13 The gate drive circuit 100 can further comprise a square wave signal line 120, and the first source-drain sub-layer 21 is further used to form the square wave signal line 120. The gate sub-layer 24 is further used to form a signal adapter, and the signal adapter is connected to the square wave signal line 120 and the second electrode of the target transistor 112 through the communication hole, respectively.
[0106] In some embodiments, please refer to Figure 4 Each thin film transistor 111 in the plurality of thin film transistors 111 except the target transistor 112 is a common transistor 113. Please refer to Figure 13 The first source-drain sub-layer 21 can be further used to form the second electrode of the common transistor 113, and the second electrode of the common transistor 113 is connected to the active layer of the same common transistor 113 through the communication hole.
[0107] Compared with Figure 13 and Figure 1 The capacitance generated by the overlap of the square wave signal and the signal of the shielding layer 30 is reduced by 76%, and the power consumption of the GOA is reduced by 76%.
[0108] Figure 16 For Figure 4 Another circuit distribution diagram of the shift register of Figure 16 In some embodiments, the second pole of the target transistor 112 is at least partially not overlapped with the normal projection of the shielding layer 30 on the substrate 10, and at least partially not overlapped with the normal projection of the first source-drain sub-layer 21 on the substrate 10.
[0109] Compared with Figure 16 Compared with Figure 1 Compared with the square wave signal, the capacitance generated by the overlap of the shielding layer 30 signal is reduced by 99%, and the power consumption of the GOA is reduced by 99%.
[0110] In a second aspect, an embodiment of the present application provides a display device, which comprises the display panel provided in the first aspect.
[0111] In the present application, unless specifically defined and limited otherwise, the first feature is "on" or "under" the second feature, which can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature is "on", "above" and "on the surface" of the second feature, which includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature is "under", "below" and "under" the second feature, which includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.
[0112] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" indicate the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.
[0113] In the present application, unless specifically defined and limited otherwise, the terms "connection", "fixing" and the like should be understood broadly, for example, "fixing" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate medium; can be internal connection of two elements or interaction relationship of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0114] In addition, the descriptions in the present application such as "first", "second", etc. are only for the purpose of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.
[0115] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the claims and their equivalents.
Claims
1. A display panel, characterized by, The display panel comprises: a substrate (10) having a display area (11) and a non-display area (12) located at one side of the display area (11); a thin film transistor layer (20) located on the substrate (10) and used for forming a gate drive circuit (100) in the non-display area (12); the gate drive circuit (100) comprises a plurality of cascaded shift registers (110), each of the shift registers (110) comprises a plurality of thin film transistors (111), at least one of the thin film transistors (111) is a target transistor (112); the thin film transistor layer (20) comprises a first source-drain sub-layer (21) used for forming a first electrode of the thin film transistor (111); a shielding layer (30) located between the thin film transistor layer (20) and the substrate (10); a normal projection of the shielding layer (30) on the substrate (10) is a first projection area, a normal projection of the first source-drain sub-layer (21) on the substrate (10) is a second projection area, and a normal projection of a second electrode of the target transistor (112) on the substrate (10) is a third projection area, and the third projection area at least partially does not overlap with the first projection area and / or the second projection area.
2. The display panel of claim 1, wherein, The target transistor (112) comprises a thin film transistor (111) with the largest width-length ratio among the plurality of thin film transistors (111).
3. The display panel of claim 2, wherein, The gate drive circuit (100) further comprises a square wave signal line (120), and the second electrode of the target transistor (112) is connected with the square wave signal line (120).
4. The display panel according to any one of claims 1-3, characterized in that, The normal projection of the second electrode of the target transistor (112) on the substrate (10) at least partially does not overlap with the normal projection of the shielding layer (30) on the substrate (10).
5. The display panel of claim 4, wherein, The normal projection of the second electrode of the target transistor (112) on the substrate (10) does not intersect with the normal projection of the shielding layer (30) on the substrate (10).
6. The display panel of claim 4, wherein, The normal projection of the first electrode of the target transistor (112) on the substrate (10) at least partially does not overlap with the normal projection of the shielding layer (30) on the substrate (10).
7. The display panel of claim 4, wherein, Each of the thin film transistors (111) except the target transistor (112) is a common transistor (113); the normal projection of the shielding layer (30) on the substrate (10) comprises the normal projection of the common transistor (113) on the substrate (10).
8. The display panel of any of claims 1-3, wherein, The first source-drain sub-layer (21) is further used for forming an electrode switching part of the target transistor (112), and the electrode switching part of the target transistor (112) is connected with an active layer of the same target transistor (112) through a communication hole; The thin film transistor layer (20) further comprises: A second source-drain sub-layer (22) is located on the side of the first source-drain sub-layer (21) away from the substrate (10), and is used to form a second electrode of the target transistor (112), and the second electrode of the target transistor (112) is connected to the electrode adapter of the same target transistor (112) through a communication hole.
9. The display panel of claim 8, wherein, The orthogonal projection of the electrode adapter of the target transistor (112) on the substrate (10) partially overlaps with the orthogonal projection of the second electrode of the same target transistor (112) on the substrate (10).
10. The display panel of claim 9, wherein, The two ends of the second electrode of the target transistor (112) are respectively connected to the electrode adapters of the same target transistor (112) through communication holes, and the electrode adapters connected to the two ends of the second electrode of the target transistor (112) are different.
11. The display panel of claim 10, wherein, The orthogonal projections of the two ends of the second electrode of the target transistor (112) on the substrate (10) respectively include the orthogonal projections of the electrode adapters connected thereto on the substrate (10).
12. The display panel of claim 11, wherein, The electrode adapter of the target transistor (112) is connected to the active layer of the same target transistor (112) through two communication holes.
13. The display panel of claim 10, wherein, The target transistor (112) has two second electrodes, and each end of each second electrode of the target transistor (112) is connected to the electrode adapter of the same target transistor (112) through a communication hole.
14. The display panel of claim 8, wherein, The thin film transistor layer (20) further comprises: A semiconductor sub-layer (23) is located on the side of the first source-drain sub-layer (21) close to the substrate (10), and is used to form an active layer of the thin film transistor (111). A gate sub-layer (24) is located between the semiconductor sub-layer (23) and the first source-drain sub-layer (21), and is used to form a gate of the thin film transistor (111).
15. The display panel of claim 14, wherein, The gate driving circuit (100) further comprises a square wave signal line (120), and the first source-drain sub-layer (21) is further used to form the square wave signal line (120); the gate sub-layer (24) is further used to form a signal adapter, and the signal adapter is connected to the square wave signal line (120) and the second electrode of the target transistor (112) through communication holes, respectively.
16. The display panel of claim 8, wherein, Each thin film transistor (111) in the plurality of thin film transistors (111) except the target transistor (112) is a common transistor (113); the first source-drain sub-layer (21) is further used to form a second electrode of the common transistor (113), and the second electrode of the common transistor (113) is connected to the active layer of the same common transistor (113) through a communication hole.
17. A display device comprising: The display device comprises the display panel according to any one of claims 1-16.